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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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0788f1e973
The arm_pmu::handle_irq() callback has the same prototype as a generic IRQ handler, taking the IRQ number and a void pointer argument which it must convert to an arm_pmu pointer. This means that all arm_pmu::handle_irq() take an IRQ number they never use, and all must explicitly cast the void pointer to an arm_pmu pointer. Instead, let's change arm_pmu::handle_irq to take an arm_pmu pointer, allowing these casts to be removed. The redundant IRQ number parameter is also removed. Suggested-by: Hoeun Ryu <hoeun.ryu@lge.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
888 lines
21 KiB
C
888 lines
21 KiB
C
#undef DEBUG
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/*
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* ARM performance counter support.
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*
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* Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
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* Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
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*
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* This code is based on the sparc64 perf event code, which is in turn based
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* on the x86 code.
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*/
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#define pr_fmt(fmt) "hw perfevents: " fmt
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#include <linux/bitmap.h>
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#include <linux/cpumask.h>
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#include <linux/cpu_pm.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/perf/arm_pmu.h>
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#include <linux/slab.h>
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#include <linux/sched/clock.h>
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#include <linux/spinlock.h>
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#include <linux/irq.h>
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#include <linux/irqdesc.h>
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#include <asm/irq_regs.h>
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static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
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static DEFINE_PER_CPU(int, cpu_irq);
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static int
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armpmu_map_cache_event(const unsigned (*cache_map)
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX],
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u64 config)
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{
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unsigned int cache_type, cache_op, cache_result, ret;
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cache_type = (config >> 0) & 0xff;
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if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
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return -EINVAL;
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cache_op = (config >> 8) & 0xff;
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if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
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return -EINVAL;
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cache_result = (config >> 16) & 0xff;
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if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return -EINVAL;
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if (!cache_map)
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return -ENOENT;
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ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
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if (ret == CACHE_OP_UNSUPPORTED)
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return -ENOENT;
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return ret;
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}
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static int
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armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
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{
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int mapping;
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if (config >= PERF_COUNT_HW_MAX)
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return -EINVAL;
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if (!event_map)
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return -ENOENT;
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mapping = (*event_map)[config];
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return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
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}
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static int
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armpmu_map_raw_event(u32 raw_event_mask, u64 config)
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{
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return (int)(config & raw_event_mask);
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}
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int
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armpmu_map_event(struct perf_event *event,
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const unsigned (*event_map)[PERF_COUNT_HW_MAX],
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const unsigned (*cache_map)
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX],
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u32 raw_event_mask)
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{
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u64 config = event->attr.config;
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int type = event->attr.type;
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if (type == event->pmu->type)
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return armpmu_map_raw_event(raw_event_mask, config);
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switch (type) {
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case PERF_TYPE_HARDWARE:
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return armpmu_map_hw_event(event_map, config);
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case PERF_TYPE_HW_CACHE:
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return armpmu_map_cache_event(cache_map, config);
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case PERF_TYPE_RAW:
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return armpmu_map_raw_event(raw_event_mask, config);
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}
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return -ENOENT;
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}
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int armpmu_event_set_period(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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s64 left = local64_read(&hwc->period_left);
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s64 period = hwc->sample_period;
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int ret = 0;
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if (unlikely(left <= -period)) {
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left = period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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ret = 1;
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}
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if (unlikely(left <= 0)) {
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left += period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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ret = 1;
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}
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/*
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* Limit the maximum period to prevent the counter value
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* from overtaking the one we are about to program. In
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* effect we are reducing max_period to account for
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* interrupt latency (and we are being very conservative).
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*/
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if (left > (armpmu->max_period >> 1))
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left = armpmu->max_period >> 1;
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local64_set(&hwc->prev_count, (u64)-left);
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armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
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perf_event_update_userpage(event);
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return ret;
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}
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u64 armpmu_event_update(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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u64 delta, prev_raw_count, new_raw_count;
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again:
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prev_raw_count = local64_read(&hwc->prev_count);
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new_raw_count = armpmu->read_counter(event);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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goto again;
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delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
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local64_add(delta, &event->count);
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local64_sub(delta, &hwc->period_left);
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return new_raw_count;
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}
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static void
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armpmu_read(struct perf_event *event)
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{
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armpmu_event_update(event);
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}
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static void
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armpmu_stop(struct perf_event *event, int flags)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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/*
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* ARM pmu always has to update the counter, so ignore
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* PERF_EF_UPDATE, see comments in armpmu_start().
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*/
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if (!(hwc->state & PERF_HES_STOPPED)) {
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armpmu->disable(event);
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armpmu_event_update(event);
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hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
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}
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}
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static void armpmu_start(struct perf_event *event, int flags)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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/*
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* ARM pmu always has to reprogram the period, so ignore
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* PERF_EF_RELOAD, see the comment below.
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*/
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if (flags & PERF_EF_RELOAD)
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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/*
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* Set the period again. Some counters can't be stopped, so when we
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* were stopped we simply disabled the IRQ source and the counter
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* may have been left counting. If we don't do this step then we may
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* get an interrupt too soon or *way* too late if the overflow has
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* happened since disabling.
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*/
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armpmu_event_set_period(event);
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armpmu->enable(event);
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}
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static void
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armpmu_del(struct perf_event *event, int flags)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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armpmu_stop(event, PERF_EF_UPDATE);
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hw_events->events[idx] = NULL;
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clear_bit(idx, hw_events->used_mask);
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if (armpmu->clear_event_idx)
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armpmu->clear_event_idx(hw_events, event);
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perf_event_update_userpage(event);
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}
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static int
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armpmu_add(struct perf_event *event, int flags)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx;
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/* An event following a process won't be stopped earlier */
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if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
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return -ENOENT;
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/* If we don't have a space for the counter then finish early. */
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idx = armpmu->get_event_idx(hw_events, event);
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if (idx < 0)
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return idx;
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/*
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* If there is an event in the counter we are going to use then make
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* sure it is disabled.
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*/
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event->hw.idx = idx;
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armpmu->disable(event);
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hw_events->events[idx] = event;
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hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
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if (flags & PERF_EF_START)
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armpmu_start(event, PERF_EF_RELOAD);
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/* Propagate our changes to the userspace mapping. */
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perf_event_update_userpage(event);
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return 0;
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}
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static int
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validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
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struct perf_event *event)
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{
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struct arm_pmu *armpmu;
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if (is_software_event(event))
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return 1;
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/*
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* Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
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* core perf code won't check that the pmu->ctx == leader->ctx
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* until after pmu->event_init(event).
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*/
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if (event->pmu != pmu)
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return 0;
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if (event->state < PERF_EVENT_STATE_OFF)
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return 1;
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if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
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return 1;
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armpmu = to_arm_pmu(event->pmu);
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return armpmu->get_event_idx(hw_events, event) >= 0;
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}
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static int
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validate_group(struct perf_event *event)
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{
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struct perf_event *sibling, *leader = event->group_leader;
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struct pmu_hw_events fake_pmu;
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/*
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* Initialise the fake PMU. We only need to populate the
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* used_mask for the purposes of validation.
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*/
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memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
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if (!validate_event(event->pmu, &fake_pmu, leader))
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return -EINVAL;
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for_each_sibling_event(sibling, leader) {
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if (!validate_event(event->pmu, &fake_pmu, sibling))
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return -EINVAL;
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}
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if (!validate_event(event->pmu, &fake_pmu, event))
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return -EINVAL;
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return 0;
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}
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static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
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{
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struct arm_pmu *armpmu;
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int ret;
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u64 start_clock, finish_clock;
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/*
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* we request the IRQ with a (possibly percpu) struct arm_pmu**, but
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* the handlers expect a struct arm_pmu*. The percpu_irq framework will
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* do any necessary shifting, we just need to perform the first
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* dereference.
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*/
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armpmu = *(void **)dev;
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if (WARN_ON_ONCE(!armpmu))
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return IRQ_NONE;
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start_clock = sched_clock();
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ret = armpmu->handle_irq(armpmu);
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finish_clock = sched_clock();
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perf_sample_event_took(finish_clock - start_clock);
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return ret;
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}
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static int
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event_requires_mode_exclusion(struct perf_event_attr *attr)
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{
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return attr->exclude_idle || attr->exclude_user ||
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attr->exclude_kernel || attr->exclude_hv;
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}
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static int
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__hw_perf_event_init(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int mapping;
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mapping = armpmu->map_event(event);
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if (mapping < 0) {
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pr_debug("event %x:%llx not supported\n", event->attr.type,
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event->attr.config);
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return mapping;
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}
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/*
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* We don't assign an index until we actually place the event onto
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* hardware. Use -1 to signify that we haven't decided where to put it
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* yet. For SMP systems, each core has it's own PMU so we can't do any
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* clever allocation or constraints checking at this point.
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*/
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hwc->idx = -1;
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hwc->config_base = 0;
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hwc->config = 0;
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hwc->event_base = 0;
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/*
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* Check whether we need to exclude the counter from certain modes.
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*/
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if ((!armpmu->set_event_filter ||
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armpmu->set_event_filter(hwc, &event->attr)) &&
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event_requires_mode_exclusion(&event->attr)) {
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pr_debug("ARM performance counters do not support "
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"mode exclusion\n");
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return -EOPNOTSUPP;
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}
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/*
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* Store the event encoding into the config_base field.
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*/
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hwc->config_base |= (unsigned long)mapping;
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if (!is_sampling_event(event)) {
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/*
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* For non-sampling runs, limit the sample_period to half
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* of the counter width. That way, the new counter value
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* is far less likely to overtake the previous one unless
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* you have some serious IRQ latency issues.
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*/
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hwc->sample_period = armpmu->max_period >> 1;
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hwc->last_period = hwc->sample_period;
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local64_set(&hwc->period_left, hwc->sample_period);
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}
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if (event->group_leader != event) {
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if (validate_group(event) != 0)
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return -EINVAL;
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}
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return 0;
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}
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static int armpmu_event_init(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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/*
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* Reject CPU-affine events for CPUs that are of a different class to
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* that which this PMU handles. Process-following events (where
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* event->cpu == -1) can be migrated between CPUs, and thus we have to
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* reject them later (in armpmu_add) if they're scheduled on a
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* different class of CPU.
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*/
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if (event->cpu != -1 &&
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!cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
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return -ENOENT;
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/* does not support taken branch sampling */
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if (has_branch_stack(event))
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return -EOPNOTSUPP;
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if (armpmu->map_event(event) == -ENOENT)
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return -ENOENT;
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return __hw_perf_event_init(event);
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}
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static void armpmu_enable(struct pmu *pmu)
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{
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struct arm_pmu *armpmu = to_arm_pmu(pmu);
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struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
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int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
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/* For task-bound events we may be called on other CPUs */
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if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
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return;
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if (enabled)
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armpmu->start(armpmu);
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}
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static void armpmu_disable(struct pmu *pmu)
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{
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struct arm_pmu *armpmu = to_arm_pmu(pmu);
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/* For task-bound events we may be called on other CPUs */
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if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
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return;
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armpmu->stop(armpmu);
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}
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/*
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* In heterogeneous systems, events are specific to a particular
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* microarchitecture, and aren't suitable for another. Thus, only match CPUs of
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* the same microarchitecture.
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*/
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static int armpmu_filter_match(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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unsigned int cpu = smp_processor_id();
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return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
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}
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static ssize_t armpmu_cpumask_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
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return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
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}
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static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL);
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static struct attribute *armpmu_common_attrs[] = {
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&dev_attr_cpus.attr,
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NULL,
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};
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static struct attribute_group armpmu_common_attr_group = {
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.attrs = armpmu_common_attrs,
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};
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/* Set at runtime when we know what CPU type we are. */
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static struct arm_pmu *__oprofile_cpu_pmu;
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/*
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* Despite the names, these two functions are CPU-specific and are used
|
|
* by the OProfile/perf code.
|
|
*/
|
|
const char *perf_pmu_name(void)
|
|
{
|
|
if (!__oprofile_cpu_pmu)
|
|
return NULL;
|
|
|
|
return __oprofile_cpu_pmu->name;
|
|
}
|
|
EXPORT_SYMBOL_GPL(perf_pmu_name);
|
|
|
|
int perf_num_counters(void)
|
|
{
|
|
int max_events = 0;
|
|
|
|
if (__oprofile_cpu_pmu != NULL)
|
|
max_events = __oprofile_cpu_pmu->num_events;
|
|
|
|
return max_events;
|
|
}
|
|
EXPORT_SYMBOL_GPL(perf_num_counters);
|
|
|
|
static int armpmu_count_irq_users(const int irq)
|
|
{
|
|
int cpu, count = 0;
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
if (per_cpu(cpu_irq, cpu) == irq)
|
|
count++;
|
|
}
|
|
|
|
return count;
|
|
}
|
|
|
|
void armpmu_free_irq(int irq, int cpu)
|
|
{
|
|
if (per_cpu(cpu_irq, cpu) == 0)
|
|
return;
|
|
if (WARN_ON(irq != per_cpu(cpu_irq, cpu)))
|
|
return;
|
|
|
|
if (!irq_is_percpu_devid(irq))
|
|
free_irq(irq, per_cpu_ptr(&cpu_armpmu, cpu));
|
|
else if (armpmu_count_irq_users(irq) == 1)
|
|
free_percpu_irq(irq, &cpu_armpmu);
|
|
|
|
per_cpu(cpu_irq, cpu) = 0;
|
|
}
|
|
|
|
int armpmu_request_irq(int irq, int cpu)
|
|
{
|
|
int err = 0;
|
|
const irq_handler_t handler = armpmu_dispatch_irq;
|
|
if (!irq)
|
|
return 0;
|
|
|
|
if (!irq_is_percpu_devid(irq)) {
|
|
unsigned long irq_flags;
|
|
|
|
err = irq_force_affinity(irq, cpumask_of(cpu));
|
|
|
|
if (err && num_possible_cpus() > 1) {
|
|
pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
|
|
irq, cpu);
|
|
goto err_out;
|
|
}
|
|
|
|
irq_flags = IRQF_PERCPU |
|
|
IRQF_NOBALANCING |
|
|
IRQF_NO_THREAD;
|
|
|
|
irq_set_status_flags(irq, IRQ_NOAUTOEN);
|
|
err = request_irq(irq, handler, irq_flags, "arm-pmu",
|
|
per_cpu_ptr(&cpu_armpmu, cpu));
|
|
} else if (armpmu_count_irq_users(irq) == 0) {
|
|
err = request_percpu_irq(irq, handler, "arm-pmu",
|
|
&cpu_armpmu);
|
|
}
|
|
|
|
if (err)
|
|
goto err_out;
|
|
|
|
per_cpu(cpu_irq, cpu) = irq;
|
|
return 0;
|
|
|
|
err_out:
|
|
pr_err("unable to request IRQ%d for ARM PMU counters\n", irq);
|
|
return err;
|
|
}
|
|
|
|
static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
|
|
{
|
|
struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
|
|
return per_cpu(hw_events->irq, cpu);
|
|
}
|
|
|
|
/*
|
|
* PMU hardware loses all context when a CPU goes offline.
|
|
* When a CPU is hotplugged back in, since some hardware registers are
|
|
* UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
|
|
* junk values out of them.
|
|
*/
|
|
static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
|
|
{
|
|
struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
|
|
int irq;
|
|
|
|
if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
|
|
return 0;
|
|
if (pmu->reset)
|
|
pmu->reset(pmu);
|
|
|
|
per_cpu(cpu_armpmu, cpu) = pmu;
|
|
|
|
irq = armpmu_get_cpu_irq(pmu, cpu);
|
|
if (irq) {
|
|
if (irq_is_percpu_devid(irq))
|
|
enable_percpu_irq(irq, IRQ_TYPE_NONE);
|
|
else
|
|
enable_irq(irq);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
|
|
{
|
|
struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
|
|
int irq;
|
|
|
|
if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
|
|
return 0;
|
|
|
|
irq = armpmu_get_cpu_irq(pmu, cpu);
|
|
if (irq) {
|
|
if (irq_is_percpu_devid(irq))
|
|
disable_percpu_irq(irq);
|
|
else
|
|
disable_irq_nosync(irq);
|
|
}
|
|
|
|
per_cpu(cpu_armpmu, cpu) = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_CPU_PM
|
|
static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
|
|
{
|
|
struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
|
|
struct perf_event *event;
|
|
int idx;
|
|
|
|
for (idx = 0; idx < armpmu->num_events; idx++) {
|
|
/*
|
|
* If the counter is not used skip it, there is no
|
|
* need of stopping/restarting it.
|
|
*/
|
|
if (!test_bit(idx, hw_events->used_mask))
|
|
continue;
|
|
|
|
event = hw_events->events[idx];
|
|
|
|
switch (cmd) {
|
|
case CPU_PM_ENTER:
|
|
/*
|
|
* Stop and update the counter
|
|
*/
|
|
armpmu_stop(event, PERF_EF_UPDATE);
|
|
break;
|
|
case CPU_PM_EXIT:
|
|
case CPU_PM_ENTER_FAILED:
|
|
/*
|
|
* Restore and enable the counter.
|
|
* armpmu_start() indirectly calls
|
|
*
|
|
* perf_event_update_userpage()
|
|
*
|
|
* that requires RCU read locking to be functional,
|
|
* wrap the call within RCU_NONIDLE to make the
|
|
* RCU subsystem aware this cpu is not idle from
|
|
* an RCU perspective for the armpmu_start() call
|
|
* duration.
|
|
*/
|
|
RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
|
|
void *v)
|
|
{
|
|
struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
|
|
struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
|
|
int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
|
|
|
|
if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
|
|
return NOTIFY_DONE;
|
|
|
|
/*
|
|
* Always reset the PMU registers on power-up even if
|
|
* there are no events running.
|
|
*/
|
|
if (cmd == CPU_PM_EXIT && armpmu->reset)
|
|
armpmu->reset(armpmu);
|
|
|
|
if (!enabled)
|
|
return NOTIFY_OK;
|
|
|
|
switch (cmd) {
|
|
case CPU_PM_ENTER:
|
|
armpmu->stop(armpmu);
|
|
cpu_pm_pmu_setup(armpmu, cmd);
|
|
break;
|
|
case CPU_PM_EXIT:
|
|
cpu_pm_pmu_setup(armpmu, cmd);
|
|
case CPU_PM_ENTER_FAILED:
|
|
armpmu->start(armpmu);
|
|
break;
|
|
default:
|
|
return NOTIFY_DONE;
|
|
}
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
|
|
{
|
|
cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
|
|
return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
|
|
}
|
|
|
|
static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
|
|
{
|
|
cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
|
|
}
|
|
#else
|
|
static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
|
|
static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
|
|
#endif
|
|
|
|
static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
int err;
|
|
|
|
err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
|
|
&cpu_pmu->node);
|
|
if (err)
|
|
goto out;
|
|
|
|
err = cpu_pm_pmu_register(cpu_pmu);
|
|
if (err)
|
|
goto out_unregister;
|
|
|
|
return 0;
|
|
|
|
out_unregister:
|
|
cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
|
|
&cpu_pmu->node);
|
|
out:
|
|
return err;
|
|
}
|
|
|
|
static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
|
|
{
|
|
cpu_pm_pmu_unregister(cpu_pmu);
|
|
cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
|
|
&cpu_pmu->node);
|
|
}
|
|
|
|
static struct arm_pmu *__armpmu_alloc(gfp_t flags)
|
|
{
|
|
struct arm_pmu *pmu;
|
|
int cpu;
|
|
|
|
pmu = kzalloc(sizeof(*pmu), flags);
|
|
if (!pmu) {
|
|
pr_info("failed to allocate PMU device!\n");
|
|
goto out;
|
|
}
|
|
|
|
pmu->hw_events = alloc_percpu_gfp(struct pmu_hw_events, flags);
|
|
if (!pmu->hw_events) {
|
|
pr_info("failed to allocate per-cpu PMU data.\n");
|
|
goto out_free_pmu;
|
|
}
|
|
|
|
pmu->pmu = (struct pmu) {
|
|
.pmu_enable = armpmu_enable,
|
|
.pmu_disable = armpmu_disable,
|
|
.event_init = armpmu_event_init,
|
|
.add = armpmu_add,
|
|
.del = armpmu_del,
|
|
.start = armpmu_start,
|
|
.stop = armpmu_stop,
|
|
.read = armpmu_read,
|
|
.filter_match = armpmu_filter_match,
|
|
.attr_groups = pmu->attr_groups,
|
|
/*
|
|
* This is a CPU PMU potentially in a heterogeneous
|
|
* configuration (e.g. big.LITTLE). This is not an uncore PMU,
|
|
* and we have taken ctx sharing into account (e.g. with our
|
|
* pmu::filter_match callback and pmu::event_init group
|
|
* validation).
|
|
*/
|
|
.capabilities = PERF_PMU_CAP_HETEROGENEOUS_CPUS,
|
|
};
|
|
|
|
pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
|
|
&armpmu_common_attr_group;
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
struct pmu_hw_events *events;
|
|
|
|
events = per_cpu_ptr(pmu->hw_events, cpu);
|
|
raw_spin_lock_init(&events->pmu_lock);
|
|
events->percpu_pmu = pmu;
|
|
}
|
|
|
|
return pmu;
|
|
|
|
out_free_pmu:
|
|
kfree(pmu);
|
|
out:
|
|
return NULL;
|
|
}
|
|
|
|
struct arm_pmu *armpmu_alloc(void)
|
|
{
|
|
return __armpmu_alloc(GFP_KERNEL);
|
|
}
|
|
|
|
struct arm_pmu *armpmu_alloc_atomic(void)
|
|
{
|
|
return __armpmu_alloc(GFP_ATOMIC);
|
|
}
|
|
|
|
|
|
void armpmu_free(struct arm_pmu *pmu)
|
|
{
|
|
free_percpu(pmu->hw_events);
|
|
kfree(pmu);
|
|
}
|
|
|
|
int armpmu_register(struct arm_pmu *pmu)
|
|
{
|
|
int ret;
|
|
|
|
ret = cpu_pmu_init(pmu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
|
|
if (ret)
|
|
goto out_destroy;
|
|
|
|
if (!__oprofile_cpu_pmu)
|
|
__oprofile_cpu_pmu = pmu;
|
|
|
|
pr_info("enabled with %s PMU driver, %d counters available\n",
|
|
pmu->name, pmu->num_events);
|
|
|
|
return 0;
|
|
|
|
out_destroy:
|
|
cpu_pmu_destroy(pmu);
|
|
return ret;
|
|
}
|
|
|
|
static int arm_pmu_hp_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
|
|
"perf/arm/pmu:starting",
|
|
arm_perf_starting_cpu,
|
|
arm_perf_teardown_cpu);
|
|
if (ret)
|
|
pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
subsys_initcall(arm_pmu_hp_init);
|