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![Thomas Gleixner](/assets/img/avatar_default.png)
Pull clockevents updates from Daniel Lezcano - Provide a framework to handle errata gracefuly for arm_arch_timer (Mark Zyngier) - Clarify the DT properties for the rockchip timer and add the clocksource as an alternative to the bogus architected timer (Alexander Kochetkov) - Rename the Gemini timer to Faraday timer fttmr010 and provide a specific initialization for Gemini (Linus Walleij) - Add missing newlines in the error message in the timers (Rafał Miłecki) - Read the clock once and implement the delay timer on Orion (Russell King)
424 lines
12 KiB
C
424 lines
12 KiB
C
/*
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* (C) Copyright 2009 Intel Corporation
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* Author: Jacob Pan (jacob.jun.pan@intel.com)
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*
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* Shared with ARM platforms, Jamie Iles, Picochip 2011
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Support for the Synopsys DesignWare APB Timers.
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*/
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#include <linux/dw_apb_timer.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#define APBT_MIN_PERIOD 4
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#define APBT_MIN_DELTA_USEC 200
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#define APBTMR_N_LOAD_COUNT 0x00
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#define APBTMR_N_CURRENT_VALUE 0x04
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#define APBTMR_N_CONTROL 0x08
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#define APBTMR_N_EOI 0x0c
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#define APBTMR_N_INT_STATUS 0x10
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#define APBTMRS_INT_STATUS 0xa0
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#define APBTMRS_EOI 0xa4
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#define APBTMRS_RAW_INT_STATUS 0xa8
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#define APBTMRS_COMP_VERSION 0xac
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#define APBTMR_CONTROL_ENABLE (1 << 0)
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/* 1: periodic, 0:free running. */
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#define APBTMR_CONTROL_MODE_PERIODIC (1 << 1)
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#define APBTMR_CONTROL_INT (1 << 2)
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static inline struct dw_apb_clock_event_device *
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ced_to_dw_apb_ced(struct clock_event_device *evt)
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{
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return container_of(evt, struct dw_apb_clock_event_device, ced);
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}
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static inline struct dw_apb_clocksource *
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clocksource_to_dw_apb_clocksource(struct clocksource *cs)
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{
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return container_of(cs, struct dw_apb_clocksource, cs);
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}
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static inline u32 apbt_readl(struct dw_apb_timer *timer, unsigned long offs)
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{
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return readl(timer->base + offs);
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}
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static inline void apbt_writel(struct dw_apb_timer *timer, u32 val,
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unsigned long offs)
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{
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writel(val, timer->base + offs);
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}
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static inline u32 apbt_readl_relaxed(struct dw_apb_timer *timer, unsigned long offs)
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{
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return readl_relaxed(timer->base + offs);
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}
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static inline void apbt_writel_relaxed(struct dw_apb_timer *timer, u32 val,
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unsigned long offs)
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{
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writel_relaxed(val, timer->base + offs);
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}
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static void apbt_disable_int(struct dw_apb_timer *timer)
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{
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u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
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ctrl |= APBTMR_CONTROL_INT;
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apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
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}
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/**
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* dw_apb_clockevent_pause() - stop the clock_event_device from running
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*
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* @dw_ced: The APB clock to stop generating events.
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*/
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void dw_apb_clockevent_pause(struct dw_apb_clock_event_device *dw_ced)
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{
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disable_irq(dw_ced->timer.irq);
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apbt_disable_int(&dw_ced->timer);
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}
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static void apbt_eoi(struct dw_apb_timer *timer)
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{
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apbt_readl_relaxed(timer, APBTMR_N_EOI);
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}
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static irqreturn_t dw_apb_clockevent_irq(int irq, void *data)
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{
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struct clock_event_device *evt = data;
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struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
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if (!evt->event_handler) {
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pr_info("Spurious APBT timer interrupt %d\n", irq);
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return IRQ_NONE;
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}
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if (dw_ced->eoi)
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dw_ced->eoi(&dw_ced->timer);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static void apbt_enable_int(struct dw_apb_timer *timer)
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{
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u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
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/* clear pending intr */
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apbt_readl(timer, APBTMR_N_EOI);
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ctrl &= ~APBTMR_CONTROL_INT;
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apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
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}
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static int apbt_shutdown(struct clock_event_device *evt)
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{
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struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
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u32 ctrl;
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pr_debug("%s CPU %d state=shutdown\n", __func__,
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cpumask_first(evt->cpumask));
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ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
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ctrl &= ~APBTMR_CONTROL_ENABLE;
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apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
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return 0;
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}
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static int apbt_set_oneshot(struct clock_event_device *evt)
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{
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struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
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u32 ctrl;
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pr_debug("%s CPU %d state=oneshot\n", __func__,
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cpumask_first(evt->cpumask));
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ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
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/*
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* set free running mode, this mode will let timer reload max
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* timeout which will give time (3min on 25MHz clock) to rearm
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* the next event, therefore emulate the one-shot mode.
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*/
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ctrl &= ~APBTMR_CONTROL_ENABLE;
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ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
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apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
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/* write again to set free running mode */
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apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
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/*
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* DW APB p. 46, load counter with all 1s before starting free
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* running mode.
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*/
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apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
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ctrl &= ~APBTMR_CONTROL_INT;
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ctrl |= APBTMR_CONTROL_ENABLE;
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apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
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return 0;
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}
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static int apbt_set_periodic(struct clock_event_device *evt)
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{
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struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
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unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
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u32 ctrl;
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pr_debug("%s CPU %d state=periodic\n", __func__,
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cpumask_first(evt->cpumask));
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ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
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ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
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apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
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/*
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* DW APB p. 46, have to disable timer before load counter,
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* may cause sync problem.
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*/
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ctrl &= ~APBTMR_CONTROL_ENABLE;
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apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
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udelay(1);
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pr_debug("Setting clock period %lu for HZ %d\n", period, HZ);
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apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
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ctrl |= APBTMR_CONTROL_ENABLE;
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apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
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return 0;
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}
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static int apbt_resume(struct clock_event_device *evt)
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{
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struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
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pr_debug("%s CPU %d state=resume\n", __func__,
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cpumask_first(evt->cpumask));
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apbt_enable_int(&dw_ced->timer);
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return 0;
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}
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static int apbt_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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u32 ctrl;
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struct dw_apb_clock_event_device *dw_ced = ced_to_dw_apb_ced(evt);
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/* Disable timer */
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ctrl = apbt_readl_relaxed(&dw_ced->timer, APBTMR_N_CONTROL);
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ctrl &= ~APBTMR_CONTROL_ENABLE;
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apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
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/* write new count */
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apbt_writel_relaxed(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT);
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ctrl |= APBTMR_CONTROL_ENABLE;
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apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
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return 0;
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}
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/**
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* dw_apb_clockevent_init() - use an APB timer as a clock_event_device
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*
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* @cpu: The CPU the events will be targeted at.
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* @name: The name used for the timer and the IRQ for it.
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* @rating: The rating to give the timer.
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* @base: I/O base for the timer registers.
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* @irq: The interrupt number to use for the timer.
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* @freq: The frequency that the timer counts at.
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*
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* This creates a clock_event_device for using with the generic clock layer
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* but does not start and register it. This should be done with
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* dw_apb_clockevent_register() as the next step. If this is the first time
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* it has been called for a timer then the IRQ will be requested, if not it
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* just be enabled to allow CPU hotplug to avoid repeatedly requesting and
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* releasing the IRQ.
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*/
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struct dw_apb_clock_event_device *
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dw_apb_clockevent_init(int cpu, const char *name, unsigned rating,
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void __iomem *base, int irq, unsigned long freq)
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{
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struct dw_apb_clock_event_device *dw_ced =
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kzalloc(sizeof(*dw_ced), GFP_KERNEL);
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int err;
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if (!dw_ced)
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return NULL;
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dw_ced->timer.base = base;
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dw_ced->timer.irq = irq;
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dw_ced->timer.freq = freq;
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clockevents_calc_mult_shift(&dw_ced->ced, freq, APBT_MIN_PERIOD);
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dw_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff,
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&dw_ced->ced);
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dw_ced->ced.max_delta_ticks = 0x7fffffff;
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dw_ced->ced.min_delta_ns = clockevent_delta2ns(5000, &dw_ced->ced);
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dw_ced->ced.min_delta_ticks = 5000;
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dw_ced->ced.cpumask = cpumask_of(cpu);
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dw_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
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dw_ced->ced.set_state_shutdown = apbt_shutdown;
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dw_ced->ced.set_state_periodic = apbt_set_periodic;
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dw_ced->ced.set_state_oneshot = apbt_set_oneshot;
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dw_ced->ced.set_state_oneshot_stopped = apbt_shutdown;
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dw_ced->ced.tick_resume = apbt_resume;
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dw_ced->ced.set_next_event = apbt_next_event;
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dw_ced->ced.irq = dw_ced->timer.irq;
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dw_ced->ced.rating = rating;
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dw_ced->ced.name = name;
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dw_ced->irqaction.name = dw_ced->ced.name;
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dw_ced->irqaction.handler = dw_apb_clockevent_irq;
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dw_ced->irqaction.dev_id = &dw_ced->ced;
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dw_ced->irqaction.irq = irq;
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dw_ced->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL |
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IRQF_NOBALANCING;
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dw_ced->eoi = apbt_eoi;
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err = setup_irq(irq, &dw_ced->irqaction);
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if (err) {
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pr_err("failed to request timer irq\n");
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kfree(dw_ced);
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dw_ced = NULL;
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}
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return dw_ced;
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}
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/**
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* dw_apb_clockevent_resume() - resume a clock that has been paused.
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*
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* @dw_ced: The APB clock to resume.
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*/
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void dw_apb_clockevent_resume(struct dw_apb_clock_event_device *dw_ced)
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{
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enable_irq(dw_ced->timer.irq);
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}
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/**
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* dw_apb_clockevent_stop() - stop the clock_event_device and release the IRQ.
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*
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* @dw_ced: The APB clock to stop generating the events.
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*/
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void dw_apb_clockevent_stop(struct dw_apb_clock_event_device *dw_ced)
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{
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free_irq(dw_ced->timer.irq, &dw_ced->ced);
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}
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/**
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* dw_apb_clockevent_register() - register the clock with the generic layer
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*
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* @dw_ced: The APB clock to register as a clock_event_device.
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*/
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void dw_apb_clockevent_register(struct dw_apb_clock_event_device *dw_ced)
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{
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apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL);
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clockevents_register_device(&dw_ced->ced);
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apbt_enable_int(&dw_ced->timer);
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}
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/**
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* dw_apb_clocksource_start() - start the clocksource counting.
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*
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* @dw_cs: The clocksource to start.
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*
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* This is used to start the clocksource before registration and can be used
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* to enable calibration of timers.
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*/
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void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs)
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{
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/*
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* start count down from 0xffff_ffff. this is done by toggling the
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* enable bit then load initial load count to ~0.
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*/
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u32 ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL);
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ctrl &= ~APBTMR_CONTROL_ENABLE;
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apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
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apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT);
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/* enable, mask interrupt */
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ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
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ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
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apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
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/* read it once to get cached counter value initialized */
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dw_apb_clocksource_read(dw_cs);
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}
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static u64 __apbt_read_clocksource(struct clocksource *cs)
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{
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u32 current_count;
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struct dw_apb_clocksource *dw_cs =
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clocksource_to_dw_apb_clocksource(cs);
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current_count = apbt_readl_relaxed(&dw_cs->timer,
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APBTMR_N_CURRENT_VALUE);
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return (u64)~current_count;
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}
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static void apbt_restart_clocksource(struct clocksource *cs)
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{
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struct dw_apb_clocksource *dw_cs =
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clocksource_to_dw_apb_clocksource(cs);
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dw_apb_clocksource_start(dw_cs);
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}
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/**
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* dw_apb_clocksource_init() - use an APB timer as a clocksource.
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*
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* @rating: The rating to give the clocksource.
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* @name: The name for the clocksource.
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* @base: The I/O base for the timer registers.
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* @freq: The frequency that the timer counts at.
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*
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* This creates a clocksource using an APB timer but does not yet register it
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* with the clocksource system. This should be done with
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* dw_apb_clocksource_register() as the next step.
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*/
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struct dw_apb_clocksource *
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dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base,
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unsigned long freq)
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{
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struct dw_apb_clocksource *dw_cs = kzalloc(sizeof(*dw_cs), GFP_KERNEL);
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if (!dw_cs)
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return NULL;
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dw_cs->timer.base = base;
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dw_cs->timer.freq = freq;
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dw_cs->cs.name = name;
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dw_cs->cs.rating = rating;
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dw_cs->cs.read = __apbt_read_clocksource;
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dw_cs->cs.mask = CLOCKSOURCE_MASK(32);
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dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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dw_cs->cs.resume = apbt_restart_clocksource;
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return dw_cs;
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}
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/**
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* dw_apb_clocksource_register() - register the APB clocksource.
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*
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* @dw_cs: The clocksource to register.
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*/
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void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs)
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{
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clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);
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}
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/**
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* dw_apb_clocksource_read() - read the current value of a clocksource.
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*
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* @dw_cs: The clocksource to read.
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*/
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u64 dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs)
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{
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return (u64)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);
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}
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