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5fae405838
This patch does the following: 1. Corrects the common platform code for external interrupts for using the VIC mask/unmask bits also. 2. Moves the common defines related to external interrupt for plat-s5p to common files. 3. Based on the new common defines, corresponding changes are made in the affected platforms (S5P6440, S5P6442 and S5PC100). Signed-off-by: Pannaga Bhushan <p.bhushan@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
97 lines
3.1 KiB
C
97 lines
3.1 KiB
C
/* linux/arch/arm/plat-s5p/include/plat/irqs.h
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*
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* Copyright (c) 2009 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P Common IRQ support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PLAT_S5P_IRQS_H
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#define __ASM_PLAT_S5P_IRQS_H __FILE__
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/* we keep the first set of CPU IRQs out of the range of
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* the ISA space, so that the PC104 has them to itself
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* and we don't end up having to do horrible things to the
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* standard ISA drivers....
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*
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* note, since we're using the VICs, our start must be a
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* mulitple of 32 to allow the common code to work
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*/
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#define S5P_IRQ_OFFSET (32)
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#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET)
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#define S5P_VIC0_BASE S5P_IRQ(0)
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#define S5P_VIC1_BASE S5P_IRQ(32)
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#define S5P_VIC2_BASE S5P_IRQ(64)
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#define S5P_VIC3_BASE S5P_IRQ(96)
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#define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32))
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#define IRQ_VIC0_BASE S5P_VIC0_BASE
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#define IRQ_VIC1_BASE S5P_VIC1_BASE
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#define IRQ_VIC2_BASE S5P_VIC2_BASE
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/* UART interrupts, each UART has 4 intterupts per channel so
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* use the space between the ISA and S3C main interrupts. Note, these
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* are not in the same order as the S3C24XX series! */
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#define IRQ_S5P_UART_BASE0 (16)
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#define IRQ_S5P_UART_BASE1 (20)
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#define IRQ_S5P_UART_BASE2 (24)
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#define IRQ_S5P_UART_BASE3 (28)
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#define UART_IRQ_RXD (0)
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#define UART_IRQ_ERR (1)
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#define UART_IRQ_TXD (2)
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#define IRQ_S5P_UART_RX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_RXD)
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#define IRQ_S5P_UART_TX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_TXD)
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#define IRQ_S5P_UART_ERR0 (IRQ_S5P_UART_BASE0 + UART_IRQ_ERR)
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#define IRQ_S5P_UART_RX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_RXD)
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#define IRQ_S5P_UART_TX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_TXD)
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#define IRQ_S5P_UART_ERR1 (IRQ_S5P_UART_BASE1 + UART_IRQ_ERR)
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#define IRQ_S5P_UART_RX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_RXD)
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#define IRQ_S5P_UART_TX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_TXD)
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#define IRQ_S5P_UART_ERR2 (IRQ_S5P_UART_BASE2 + UART_IRQ_ERR)
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#define IRQ_S5P_UART_RX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_RXD)
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#define IRQ_S5P_UART_TX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_TXD)
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#define IRQ_S5P_UART_ERR3 (IRQ_S5P_UART_BASE3 + UART_IRQ_ERR)
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/* S3C compatibilty defines */
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#define IRQ_S3CUART_RX0 IRQ_S5P_UART_RX0
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#define IRQ_S3CUART_RX1 IRQ_S5P_UART_RX1
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#define IRQ_S3CUART_RX2 IRQ_S5P_UART_RX2
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#define IRQ_S3CUART_RX3 IRQ_S5P_UART_RX3
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/* VIC based IRQs */
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#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
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#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x))
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#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
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#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
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#define S5P_TIMER_IRQ(x) (11 + (x))
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#define IRQ_TIMER0 S5P_TIMER_IRQ(0)
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#define IRQ_TIMER1 S5P_TIMER_IRQ(1)
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#define IRQ_TIMER2 S5P_TIMER_IRQ(2)
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#define IRQ_TIMER3 S5P_TIMER_IRQ(3)
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#define IRQ_TIMER4 S5P_TIMER_IRQ(4)
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#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
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: ((x) - 16 + S5P_EINT_BASE2))
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#define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \
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((irq) - S5P_EINT_BASE1) : \
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((irq) + 16 - S5P_EINT_BASE2))
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#endif /* __ASM_PLAT_S5P_IRQS_H */
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