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![Manuel Lauss](/assets/img/avatar_default.png)
Raise the DMA block size limit from 2048 bytes to the maximum supported by the DMA controllers on the chip (64KB on Au1100, 4MB on Au1200). This gives a very small performance boost and apparently fixes an oops when MMC-DMA and network traffic are active at the same time. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
1206 lines
28 KiB
C
1206 lines
28 KiB
C
/*
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* linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
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*
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* Copyright (c) 2005, Advanced Micro Devices, Inc.
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*
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* Developed with help from the 2.4.30 MMC AU1XXX controller including
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* the following copyright notices:
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* Copyright (c) 2003-2004 Embedded Edge, LLC.
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* Portions Copyright (C) 2002 Embedix, Inc
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* Copyright 2002 Hewlett-Packard Company
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* 2.6 version of this driver inspired by:
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* (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
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* All Rights Reserved.
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* (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/* Why don't we use the SD controllers' carddetect feature?
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*
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* From the AU1100 MMC application guide:
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* If the Au1100-based design is intended to support both MultiMediaCards
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* and 1- or 4-data bit SecureDigital cards, then the solution is to
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* connect a weak (560KOhm) pull-up resistor to connector pin 1.
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* In doing so, a MMC card never enters SPI-mode communications,
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* but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
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* (the low to high transition will not occur).
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/scatterlist.h>
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#include <linux/leds.h>
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#include <linux/mmc/host.h>
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#include <asm/io.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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#include <asm/mach-au1x00/au1100_mmc.h>
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#define DRIVER_NAME "au1xxx-mmc"
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/* Set this to enable special debugging macros */
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/* #define DEBUG */
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#ifdef DEBUG
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#define DBG(fmt, idx, args...) \
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printk(KERN_DEBUG "au1xmmc(%d): DEBUG: " fmt, idx, ##args)
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#else
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#define DBG(fmt, idx, args...) do {} while (0)
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#endif
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/* Hardware definitions */
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#define AU1XMMC_DESCRIPTOR_COUNT 1
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/* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
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#ifdef CONFIG_SOC_AU1100
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#define AU1XMMC_DESCRIPTOR_SIZE 0x0000ffff
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#else /* Au1200 */
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#define AU1XMMC_DESCRIPTOR_SIZE 0x003fffff
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#endif
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#define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
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MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
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MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
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/* This gives us a hard value for the stop command that we can write directly
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* to the command register.
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*/
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#define STOP_CMD \
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(SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
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/* This is the set of interrupts that we configure by default. */
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#define AU1XMMC_INTERRUPTS \
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(SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \
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SD_CONFIG_CR | SD_CONFIG_I)
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/* The poll event (looking for insert/remove events runs twice a second. */
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#define AU1XMMC_DETECT_TIMEOUT (HZ/2)
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struct au1xmmc_host {
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struct mmc_host *mmc;
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struct mmc_request *mrq;
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u32 flags;
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u32 iobase;
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u32 clock;
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u32 bus_width;
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u32 power_mode;
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int status;
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struct {
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int len;
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int dir;
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} dma;
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struct {
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int index;
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int offset;
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int len;
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} pio;
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u32 tx_chan;
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u32 rx_chan;
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int irq;
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struct tasklet_struct finish_task;
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struct tasklet_struct data_task;
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struct au1xmmc_platform_data *platdata;
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struct platform_device *pdev;
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struct resource *ioarea;
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};
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/* Status flags used by the host structure */
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#define HOST_F_XMIT 0x0001
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#define HOST_F_RECV 0x0002
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#define HOST_F_DMA 0x0010
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#define HOST_F_ACTIVE 0x0100
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#define HOST_F_STOP 0x1000
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#define HOST_S_IDLE 0x0001
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#define HOST_S_CMD 0x0002
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#define HOST_S_DATA 0x0003
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#define HOST_S_STOP 0x0004
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/* Easy access macros */
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#define HOST_STATUS(h) ((h)->iobase + SD_STATUS)
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#define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG)
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#define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE)
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#define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT)
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#define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT)
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#define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG)
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#define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
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#define HOST_CMD(h) ((h)->iobase + SD_CMD)
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#define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
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#define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
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#define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG)
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#define DMA_CHANNEL(h) \
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(((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
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static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
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{
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u32 val = au_readl(HOST_CONFIG(host));
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val |= mask;
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au_writel(val, HOST_CONFIG(host));
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au_sync();
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}
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static inline void FLUSH_FIFO(struct au1xmmc_host *host)
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{
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u32 val = au_readl(HOST_CONFIG2(host));
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au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
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au_sync_delay(1);
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/* SEND_STOP will turn off clock control - this re-enables it */
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val &= ~SD_CONFIG2_DF;
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au_writel(val, HOST_CONFIG2(host));
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au_sync();
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}
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static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
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{
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u32 val = au_readl(HOST_CONFIG(host));
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val &= ~mask;
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au_writel(val, HOST_CONFIG(host));
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au_sync();
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}
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static inline void SEND_STOP(struct au1xmmc_host *host)
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{
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u32 config2;
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WARN_ON(host->status != HOST_S_DATA);
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host->status = HOST_S_STOP;
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config2 = au_readl(HOST_CONFIG2(host));
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au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
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au_sync();
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/* Send the stop commmand */
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au_writel(STOP_CMD, HOST_CMD(host));
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}
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static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
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{
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if (host->platdata && host->platdata->set_power)
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host->platdata->set_power(host->mmc, state);
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}
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static int au1xmmc_card_inserted(struct mmc_host *mmc)
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{
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struct au1xmmc_host *host = mmc_priv(mmc);
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if (host->platdata && host->platdata->card_inserted)
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return !!host->platdata->card_inserted(host->mmc);
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return -ENOSYS;
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}
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static int au1xmmc_card_readonly(struct mmc_host *mmc)
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{
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struct au1xmmc_host *host = mmc_priv(mmc);
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if (host->platdata && host->platdata->card_readonly)
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return !!host->platdata->card_readonly(mmc);
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return -ENOSYS;
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}
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static void au1xmmc_finish_request(struct au1xmmc_host *host)
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{
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struct mmc_request *mrq = host->mrq;
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host->mrq = NULL;
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host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
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host->dma.len = 0;
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host->dma.dir = 0;
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host->pio.index = 0;
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host->pio.offset = 0;
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host->pio.len = 0;
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host->status = HOST_S_IDLE;
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mmc_request_done(host->mmc, mrq);
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}
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static void au1xmmc_tasklet_finish(unsigned long param)
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{
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struct au1xmmc_host *host = (struct au1xmmc_host *) param;
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au1xmmc_finish_request(host);
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}
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static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
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struct mmc_command *cmd, struct mmc_data *data)
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{
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u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
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switch (mmc_resp_type(cmd)) {
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case MMC_RSP_NONE:
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break;
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case MMC_RSP_R1:
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mmccmd |= SD_CMD_RT_1;
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break;
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case MMC_RSP_R1B:
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mmccmd |= SD_CMD_RT_1B;
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break;
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case MMC_RSP_R2:
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mmccmd |= SD_CMD_RT_2;
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break;
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case MMC_RSP_R3:
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mmccmd |= SD_CMD_RT_3;
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break;
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default:
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printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
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mmc_resp_type(cmd));
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return -EINVAL;
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}
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if (data) {
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if (data->flags & MMC_DATA_READ) {
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if (data->blocks > 1)
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mmccmd |= SD_CMD_CT_4;
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else
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mmccmd |= SD_CMD_CT_2;
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} else if (data->flags & MMC_DATA_WRITE) {
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if (data->blocks > 1)
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mmccmd |= SD_CMD_CT_3;
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else
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mmccmd |= SD_CMD_CT_1;
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}
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}
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au_writel(cmd->arg, HOST_CMDARG(host));
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au_sync();
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if (wait)
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IRQ_OFF(host, SD_CONFIG_CR);
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au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
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au_sync();
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/* Wait for the command to go on the line */
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while (au_readl(HOST_CMD(host)) & SD_CMD_GO)
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/* nop */;
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/* Wait for the command to come back */
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if (wait) {
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u32 status = au_readl(HOST_STATUS(host));
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while (!(status & SD_STATUS_CR))
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status = au_readl(HOST_STATUS(host));
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/* Clear the CR status */
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au_writel(SD_STATUS_CR, HOST_STATUS(host));
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IRQ_ON(host, SD_CONFIG_CR);
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}
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return 0;
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}
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static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
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{
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struct mmc_request *mrq = host->mrq;
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struct mmc_data *data;
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u32 crc;
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WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
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if (host->mrq == NULL)
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return;
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data = mrq->cmd->data;
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if (status == 0)
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status = au_readl(HOST_STATUS(host));
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/* The transaction is really over when the SD_STATUS_DB bit is clear */
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while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
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status = au_readl(HOST_STATUS(host));
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data->error = 0;
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dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
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/* Process any errors */
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crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
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if (host->flags & HOST_F_XMIT)
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crc |= ((status & 0x07) == 0x02) ? 0 : 1;
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if (crc)
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data->error = -EILSEQ;
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/* Clear the CRC bits */
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au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
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data->bytes_xfered = 0;
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if (!data->error) {
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if (host->flags & HOST_F_DMA) {
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#ifdef CONFIG_SOC_AU1200 /* DBDMA */
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u32 chan = DMA_CHANNEL(host);
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chan_tab_t *c = *((chan_tab_t **)chan);
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au1x_dma_chan_t *cp = c->chan_ptr;
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data->bytes_xfered = cp->ddma_bytecnt;
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#endif
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} else
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data->bytes_xfered =
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(data->blocks * data->blksz) - host->pio.len;
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}
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au1xmmc_finish_request(host);
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}
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static void au1xmmc_tasklet_data(unsigned long param)
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{
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struct au1xmmc_host *host = (struct au1xmmc_host *)param;
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u32 status = au_readl(HOST_STATUS(host));
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au1xmmc_data_complete(host, status);
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}
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#define AU1XMMC_MAX_TRANSFER 8
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static void au1xmmc_send_pio(struct au1xmmc_host *host)
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{
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struct mmc_data *data;
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int sg_len, max, count;
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unsigned char *sg_ptr, val;
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u32 status;
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struct scatterlist *sg;
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data = host->mrq->data;
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if (!(host->flags & HOST_F_XMIT))
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return;
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/* This is the pointer to the data buffer */
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sg = &data->sg[host->pio.index];
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sg_ptr = sg_virt(sg) + host->pio.offset;
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/* This is the space left inside the buffer */
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sg_len = data->sg[host->pio.index].length - host->pio.offset;
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/* Check if we need less than the size of the sg_buffer */
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max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
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if (max > AU1XMMC_MAX_TRANSFER)
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max = AU1XMMC_MAX_TRANSFER;
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for (count = 0; count < max; count++) {
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status = au_readl(HOST_STATUS(host));
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if (!(status & SD_STATUS_TH))
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break;
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val = *sg_ptr++;
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au_writel((unsigned long)val, HOST_TXPORT(host));
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au_sync();
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}
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host->pio.len -= count;
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host->pio.offset += count;
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if (count == sg_len) {
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host->pio.index++;
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host->pio.offset = 0;
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}
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if (host->pio.len == 0) {
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IRQ_OFF(host, SD_CONFIG_TH);
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if (host->flags & HOST_F_STOP)
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SEND_STOP(host);
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tasklet_schedule(&host->data_task);
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}
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}
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static void au1xmmc_receive_pio(struct au1xmmc_host *host)
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{
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struct mmc_data *data;
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int max, count, sg_len = 0;
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unsigned char *sg_ptr = NULL;
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u32 status, val;
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struct scatterlist *sg;
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data = host->mrq->data;
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if (!(host->flags & HOST_F_RECV))
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return;
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max = host->pio.len;
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if (host->pio.index < host->dma.len) {
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sg = &data->sg[host->pio.index];
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sg_ptr = sg_virt(sg) + host->pio.offset;
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/* This is the space left inside the buffer */
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sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
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/* Check if we need less than the size of the sg_buffer */
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if (sg_len < max)
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max = sg_len;
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}
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if (max > AU1XMMC_MAX_TRANSFER)
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max = AU1XMMC_MAX_TRANSFER;
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for (count = 0; count < max; count++) {
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status = au_readl(HOST_STATUS(host));
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if (!(status & SD_STATUS_NE))
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break;
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if (status & SD_STATUS_RC) {
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DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
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host->pio.len, count);
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break;
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}
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if (status & SD_STATUS_RO) {
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DBG("RX Overrun [%d + %d]\n", host->pdev->id,
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host->pio.len, count);
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break;
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}
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else if (status & SD_STATUS_RU) {
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DBG("RX Underrun [%d + %d]\n", host->pdev->id,
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host->pio.len, count);
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break;
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}
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val = au_readl(HOST_RXPORT(host));
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if (sg_ptr)
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*sg_ptr++ = (unsigned char)(val & 0xFF);
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}
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host->pio.len -= count;
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host->pio.offset += count;
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if (sg_len && count == sg_len) {
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host->pio.index++;
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host->pio.offset = 0;
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}
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if (host->pio.len == 0) {
|
|
/* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
|
|
IRQ_OFF(host, SD_CONFIG_NE);
|
|
|
|
if (host->flags & HOST_F_STOP)
|
|
SEND_STOP(host);
|
|
|
|
tasklet_schedule(&host->data_task);
|
|
}
|
|
}
|
|
|
|
/* This is called when a command has been completed - grab the response
|
|
* and check for errors. Then start the data transfer if it is indicated.
|
|
*/
|
|
static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
|
|
{
|
|
struct mmc_request *mrq = host->mrq;
|
|
struct mmc_command *cmd;
|
|
u32 r[4];
|
|
int i, trans;
|
|
|
|
if (!host->mrq)
|
|
return;
|
|
|
|
cmd = mrq->cmd;
|
|
cmd->error = 0;
|
|
|
|
if (cmd->flags & MMC_RSP_PRESENT) {
|
|
if (cmd->flags & MMC_RSP_136) {
|
|
r[0] = au_readl(host->iobase + SD_RESP3);
|
|
r[1] = au_readl(host->iobase + SD_RESP2);
|
|
r[2] = au_readl(host->iobase + SD_RESP1);
|
|
r[3] = au_readl(host->iobase + SD_RESP0);
|
|
|
|
/* The CRC is omitted from the response, so really
|
|
* we only got 120 bytes, but the engine expects
|
|
* 128 bits, so we have to shift things up.
|
|
*/
|
|
for (i = 0; i < 4; i++) {
|
|
cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
|
|
if (i != 3)
|
|
cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
|
|
}
|
|
} else {
|
|
/* Techincally, we should be getting all 48 bits of
|
|
* the response (SD_RESP1 + SD_RESP2), but because
|
|
* our response omits the CRC, our data ends up
|
|
* being shifted 8 bits to the right. In this case,
|
|
* that means that the OSR data starts at bit 31,
|
|
* so we can just read RESP0 and return that.
|
|
*/
|
|
cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
|
|
}
|
|
}
|
|
|
|
/* Figure out errors */
|
|
if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
|
|
cmd->error = -EILSEQ;
|
|
|
|
trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
|
|
|
|
if (!trans || cmd->error) {
|
|
IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
|
|
tasklet_schedule(&host->finish_task);
|
|
return;
|
|
}
|
|
|
|
host->status = HOST_S_DATA;
|
|
|
|
if (host->flags & HOST_F_DMA) {
|
|
#ifdef CONFIG_SOC_AU1200 /* DBDMA */
|
|
u32 channel = DMA_CHANNEL(host);
|
|
|
|
/* Start the DMA as soon as the buffer gets something in it */
|
|
|
|
if (host->flags & HOST_F_RECV) {
|
|
u32 mask = SD_STATUS_DB | SD_STATUS_NE;
|
|
|
|
while((status & mask) != mask)
|
|
status = au_readl(HOST_STATUS(host));
|
|
}
|
|
|
|
au1xxx_dbdma_start(channel);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
|
|
{
|
|
unsigned int pbus = get_au1x00_speed();
|
|
unsigned int divisor;
|
|
u32 config;
|
|
|
|
/* From databook:
|
|
* divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
|
|
*/
|
|
pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
|
|
pbus /= 2;
|
|
divisor = ((pbus / rate) / 2) - 1;
|
|
|
|
config = au_readl(HOST_CONFIG(host));
|
|
|
|
config &= ~(SD_CONFIG_DIV);
|
|
config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
|
|
|
|
au_writel(config, HOST_CONFIG(host));
|
|
au_sync();
|
|
}
|
|
|
|
static int au1xmmc_prepare_data(struct au1xmmc_host *host,
|
|
struct mmc_data *data)
|
|
{
|
|
int datalen = data->blocks * data->blksz;
|
|
|
|
if (data->flags & MMC_DATA_READ)
|
|
host->flags |= HOST_F_RECV;
|
|
else
|
|
host->flags |= HOST_F_XMIT;
|
|
|
|
if (host->mrq->stop)
|
|
host->flags |= HOST_F_STOP;
|
|
|
|
host->dma.dir = DMA_BIDIRECTIONAL;
|
|
|
|
host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
|
|
data->sg_len, host->dma.dir);
|
|
|
|
if (host->dma.len == 0)
|
|
return -ETIMEDOUT;
|
|
|
|
au_writel(data->blksz - 1, HOST_BLKSIZE(host));
|
|
|
|
if (host->flags & HOST_F_DMA) {
|
|
#ifdef CONFIG_SOC_AU1200 /* DBDMA */
|
|
int i;
|
|
u32 channel = DMA_CHANNEL(host);
|
|
|
|
au1xxx_dbdma_stop(channel);
|
|
|
|
for (i = 0; i < host->dma.len; i++) {
|
|
u32 ret = 0, flags = DDMA_FLAGS_NOIE;
|
|
struct scatterlist *sg = &data->sg[i];
|
|
int sg_len = sg->length;
|
|
|
|
int len = (datalen > sg_len) ? sg_len : datalen;
|
|
|
|
if (i == host->dma.len - 1)
|
|
flags = DDMA_FLAGS_IE;
|
|
|
|
if (host->flags & HOST_F_XMIT) {
|
|
ret = au1xxx_dbdma_put_source_flags(channel,
|
|
(void *)sg_virt(sg), len, flags);
|
|
} else {
|
|
ret = au1xxx_dbdma_put_dest_flags(channel,
|
|
(void *)sg_virt(sg), len, flags);
|
|
}
|
|
|
|
if (!ret)
|
|
goto dataerr;
|
|
|
|
datalen -= len;
|
|
}
|
|
#endif
|
|
} else {
|
|
host->pio.index = 0;
|
|
host->pio.offset = 0;
|
|
host->pio.len = datalen;
|
|
|
|
if (host->flags & HOST_F_XMIT)
|
|
IRQ_ON(host, SD_CONFIG_TH);
|
|
else
|
|
IRQ_ON(host, SD_CONFIG_NE);
|
|
/* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
|
|
}
|
|
|
|
return 0;
|
|
|
|
dataerr:
|
|
dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
|
|
host->dma.dir);
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
/* This actually starts a command or data transaction */
|
|
static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
|
|
{
|
|
struct au1xmmc_host *host = mmc_priv(mmc);
|
|
int ret = 0;
|
|
|
|
WARN_ON(irqs_disabled());
|
|
WARN_ON(host->status != HOST_S_IDLE);
|
|
|
|
host->mrq = mrq;
|
|
host->status = HOST_S_CMD;
|
|
|
|
/* fail request immediately if no card is present */
|
|
if (0 == au1xmmc_card_inserted(mmc)) {
|
|
mrq->cmd->error = -ENOMEDIUM;
|
|
au1xmmc_finish_request(host);
|
|
return;
|
|
}
|
|
|
|
if (mrq->data) {
|
|
FLUSH_FIFO(host);
|
|
ret = au1xmmc_prepare_data(host, mrq->data);
|
|
}
|
|
|
|
if (!ret)
|
|
ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
|
|
|
|
if (ret) {
|
|
mrq->cmd->error = ret;
|
|
au1xmmc_finish_request(host);
|
|
}
|
|
}
|
|
|
|
static void au1xmmc_reset_controller(struct au1xmmc_host *host)
|
|
{
|
|
/* Apply the clock */
|
|
au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
|
|
au_sync_delay(1);
|
|
|
|
au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
|
|
au_sync_delay(5);
|
|
|
|
au_writel(~0, HOST_STATUS(host));
|
|
au_sync();
|
|
|
|
au_writel(0, HOST_BLKSIZE(host));
|
|
au_writel(0x001fffff, HOST_TIMEOUT(host));
|
|
au_sync();
|
|
|
|
au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
|
|
au_sync();
|
|
|
|
au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
|
|
au_sync_delay(1);
|
|
|
|
au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
|
|
au_sync();
|
|
|
|
/* Configure interrupts */
|
|
au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
|
|
au_sync();
|
|
}
|
|
|
|
|
|
static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
struct au1xmmc_host *host = mmc_priv(mmc);
|
|
u32 config2;
|
|
|
|
if (ios->power_mode == MMC_POWER_OFF)
|
|
au1xmmc_set_power(host, 0);
|
|
else if (ios->power_mode == MMC_POWER_ON) {
|
|
au1xmmc_set_power(host, 1);
|
|
}
|
|
|
|
if (ios->clock && ios->clock != host->clock) {
|
|
au1xmmc_set_clock(host, ios->clock);
|
|
host->clock = ios->clock;
|
|
}
|
|
|
|
config2 = au_readl(HOST_CONFIG2(host));
|
|
switch (ios->bus_width) {
|
|
case MMC_BUS_WIDTH_4:
|
|
config2 |= SD_CONFIG2_WB;
|
|
break;
|
|
case MMC_BUS_WIDTH_1:
|
|
config2 &= ~SD_CONFIG2_WB;
|
|
break;
|
|
}
|
|
au_writel(config2, HOST_CONFIG2(host));
|
|
au_sync();
|
|
}
|
|
|
|
#define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
|
|
#define STATUS_DATA_IN (SD_STATUS_NE)
|
|
#define STATUS_DATA_OUT (SD_STATUS_TH)
|
|
|
|
static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
|
|
{
|
|
struct au1xmmc_host *host = dev_id;
|
|
u32 status;
|
|
|
|
status = au_readl(HOST_STATUS(host));
|
|
|
|
if (!(status & SD_STATUS_I))
|
|
return IRQ_NONE; /* not ours */
|
|
|
|
if (status & SD_STATUS_SI) /* SDIO */
|
|
mmc_signal_sdio_irq(host->mmc);
|
|
|
|
if (host->mrq && (status & STATUS_TIMEOUT)) {
|
|
if (status & SD_STATUS_RAT)
|
|
host->mrq->cmd->error = -ETIMEDOUT;
|
|
else if (status & SD_STATUS_DT)
|
|
host->mrq->data->error = -ETIMEDOUT;
|
|
|
|
/* In PIO mode, interrupts might still be enabled */
|
|
IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
|
|
|
|
/* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
|
|
tasklet_schedule(&host->finish_task);
|
|
}
|
|
#if 0
|
|
else if (status & SD_STATUS_DD) {
|
|
/* Sometimes we get a DD before a NE in PIO mode */
|
|
if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
|
|
au1xmmc_receive_pio(host);
|
|
else {
|
|
au1xmmc_data_complete(host, status);
|
|
/* tasklet_schedule(&host->data_task); */
|
|
}
|
|
}
|
|
#endif
|
|
else if (status & SD_STATUS_CR) {
|
|
if (host->status == HOST_S_CMD)
|
|
au1xmmc_cmd_complete(host, status);
|
|
|
|
} else if (!(host->flags & HOST_F_DMA)) {
|
|
if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
|
|
au1xmmc_send_pio(host);
|
|
else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
|
|
au1xmmc_receive_pio(host);
|
|
|
|
} else if (status & 0x203F3C70) {
|
|
DBG("Unhandled status %8.8x\n", host->pdev->id,
|
|
status);
|
|
}
|
|
|
|
au_writel(status, HOST_STATUS(host));
|
|
au_sync();
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
#ifdef CONFIG_SOC_AU1200
|
|
/* 8bit memory DMA device */
|
|
static dbdev_tab_t au1xmmc_mem_dbdev = {
|
|
.dev_id = DSCR_CMD0_ALWAYS,
|
|
.dev_flags = DEV_FLAGS_ANYUSE,
|
|
.dev_tsize = 0,
|
|
.dev_devwidth = 8,
|
|
.dev_physaddr = 0x00000000,
|
|
.dev_intlevel = 0,
|
|
.dev_intpolarity = 0,
|
|
};
|
|
static int memid;
|
|
|
|
static void au1xmmc_dbdma_callback(int irq, void *dev_id)
|
|
{
|
|
struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
|
|
|
|
/* Avoid spurious interrupts */
|
|
if (!host->mrq)
|
|
return;
|
|
|
|
if (host->flags & HOST_F_STOP)
|
|
SEND_STOP(host);
|
|
|
|
tasklet_schedule(&host->data_task);
|
|
}
|
|
|
|
static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
|
|
{
|
|
struct resource *res;
|
|
int txid, rxid;
|
|
|
|
res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
|
|
if (!res)
|
|
return -ENODEV;
|
|
txid = res->start;
|
|
|
|
res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
|
|
if (!res)
|
|
return -ENODEV;
|
|
rxid = res->start;
|
|
|
|
if (!memid)
|
|
return -ENODEV;
|
|
|
|
host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
|
|
au1xmmc_dbdma_callback, (void *)host);
|
|
if (!host->tx_chan) {
|
|
dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
|
|
au1xmmc_dbdma_callback, (void *)host);
|
|
if (!host->rx_chan) {
|
|
dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
|
|
au1xxx_dbdma_chan_free(host->tx_chan);
|
|
return -ENODEV;
|
|
}
|
|
|
|
au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
|
|
au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
|
|
|
|
au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
|
|
au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
|
|
|
|
/* DBDMA is good to go */
|
|
host->flags |= HOST_F_DMA;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
|
|
{
|
|
if (host->flags & HOST_F_DMA) {
|
|
host->flags &= ~HOST_F_DMA;
|
|
au1xxx_dbdma_chan_free(host->tx_chan);
|
|
au1xxx_dbdma_chan_free(host->rx_chan);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
|
|
{
|
|
struct au1xmmc_host *host = mmc_priv(mmc);
|
|
|
|
if (en)
|
|
IRQ_ON(host, SD_CONFIG_SI);
|
|
else
|
|
IRQ_OFF(host, SD_CONFIG_SI);
|
|
}
|
|
|
|
static const struct mmc_host_ops au1xmmc_ops = {
|
|
.request = au1xmmc_request,
|
|
.set_ios = au1xmmc_set_ios,
|
|
.get_ro = au1xmmc_card_readonly,
|
|
.get_cd = au1xmmc_card_inserted,
|
|
.enable_sdio_irq = au1xmmc_enable_sdio_irq,
|
|
};
|
|
|
|
static int __devinit au1xmmc_probe(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc;
|
|
struct au1xmmc_host *host;
|
|
struct resource *r;
|
|
int ret;
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
|
|
if (!mmc) {
|
|
dev_err(&pdev->dev, "no memory for mmc_host\n");
|
|
ret = -ENOMEM;
|
|
goto out0;
|
|
}
|
|
|
|
host = mmc_priv(mmc);
|
|
host->mmc = mmc;
|
|
host->platdata = pdev->dev.platform_data;
|
|
host->pdev = pdev;
|
|
|
|
ret = -ENODEV;
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!r) {
|
|
dev_err(&pdev->dev, "no mmio defined\n");
|
|
goto out1;
|
|
}
|
|
|
|
host->ioarea = request_mem_region(r->start, r->end - r->start + 1,
|
|
pdev->name);
|
|
if (!host->ioarea) {
|
|
dev_err(&pdev->dev, "mmio already in use\n");
|
|
goto out1;
|
|
}
|
|
|
|
host->iobase = (unsigned long)ioremap(r->start, 0x3c);
|
|
if (!host->iobase) {
|
|
dev_err(&pdev->dev, "cannot remap mmio\n");
|
|
goto out2;
|
|
}
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
if (!r) {
|
|
dev_err(&pdev->dev, "no IRQ defined\n");
|
|
goto out3;
|
|
}
|
|
|
|
host->irq = r->start;
|
|
/* IRQ is shared among both SD controllers */
|
|
ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
|
|
DRIVER_NAME, host);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "cannot grab IRQ\n");
|
|
goto out3;
|
|
}
|
|
|
|
mmc->ops = &au1xmmc_ops;
|
|
|
|
mmc->f_min = 450000;
|
|
mmc->f_max = 24000000;
|
|
|
|
mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
|
|
mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
|
|
|
|
mmc->max_blk_size = 2048;
|
|
mmc->max_blk_count = 512;
|
|
|
|
mmc->ocr_avail = AU1XMMC_OCR;
|
|
mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
|
|
|
|
host->status = HOST_S_IDLE;
|
|
|
|
/* board-specific carddetect setup, if any */
|
|
if (host->platdata && host->platdata->cd_setup) {
|
|
ret = host->platdata->cd_setup(mmc, 1);
|
|
if (ret) {
|
|
dev_warn(&pdev->dev, "board CD setup failed\n");
|
|
mmc->caps |= MMC_CAP_NEEDS_POLL;
|
|
}
|
|
} else
|
|
mmc->caps |= MMC_CAP_NEEDS_POLL;
|
|
|
|
tasklet_init(&host->data_task, au1xmmc_tasklet_data,
|
|
(unsigned long)host);
|
|
|
|
tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
|
|
(unsigned long)host);
|
|
|
|
#ifdef CONFIG_SOC_AU1200
|
|
ret = au1xmmc_dbdma_init(host);
|
|
if (ret)
|
|
printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n");
|
|
#endif
|
|
|
|
#ifdef CONFIG_LEDS_CLASS
|
|
if (host->platdata && host->platdata->led) {
|
|
struct led_classdev *led = host->platdata->led;
|
|
led->name = mmc_hostname(mmc);
|
|
led->brightness = LED_OFF;
|
|
led->default_trigger = mmc_hostname(mmc);
|
|
ret = led_classdev_register(mmc_dev(mmc), led);
|
|
if (ret)
|
|
goto out5;
|
|
}
|
|
#endif
|
|
|
|
au1xmmc_reset_controller(host);
|
|
|
|
ret = mmc_add_host(mmc);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "cannot add mmc host\n");
|
|
goto out6;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, host);
|
|
|
|
printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X"
|
|
" (mode=%s)\n", pdev->id, host->iobase,
|
|
host->flags & HOST_F_DMA ? "dma" : "pio");
|
|
|
|
return 0; /* all ok */
|
|
|
|
out6:
|
|
#ifdef CONFIG_LEDS_CLASS
|
|
if (host->platdata && host->platdata->led)
|
|
led_classdev_unregister(host->platdata->led);
|
|
out5:
|
|
#endif
|
|
au_writel(0, HOST_ENABLE(host));
|
|
au_writel(0, HOST_CONFIG(host));
|
|
au_writel(0, HOST_CONFIG2(host));
|
|
au_sync();
|
|
|
|
#ifdef CONFIG_SOC_AU1200
|
|
au1xmmc_dbdma_shutdown(host);
|
|
#endif
|
|
|
|
tasklet_kill(&host->data_task);
|
|
tasklet_kill(&host->finish_task);
|
|
|
|
if (host->platdata && host->platdata->cd_setup &&
|
|
!(mmc->caps & MMC_CAP_NEEDS_POLL))
|
|
host->platdata->cd_setup(mmc, 0);
|
|
|
|
free_irq(host->irq, host);
|
|
out3:
|
|
iounmap((void *)host->iobase);
|
|
out2:
|
|
release_resource(host->ioarea);
|
|
kfree(host->ioarea);
|
|
out1:
|
|
mmc_free_host(mmc);
|
|
out0:
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit au1xmmc_remove(struct platform_device *pdev)
|
|
{
|
|
struct au1xmmc_host *host = platform_get_drvdata(pdev);
|
|
|
|
if (host) {
|
|
mmc_remove_host(host->mmc);
|
|
|
|
#ifdef CONFIG_LEDS_CLASS
|
|
if (host->platdata && host->platdata->led)
|
|
led_classdev_unregister(host->platdata->led);
|
|
#endif
|
|
|
|
if (host->platdata && host->platdata->cd_setup &&
|
|
!(host->mmc->caps & MMC_CAP_NEEDS_POLL))
|
|
host->platdata->cd_setup(host->mmc, 0);
|
|
|
|
au_writel(0, HOST_ENABLE(host));
|
|
au_writel(0, HOST_CONFIG(host));
|
|
au_writel(0, HOST_CONFIG2(host));
|
|
au_sync();
|
|
|
|
tasklet_kill(&host->data_task);
|
|
tasklet_kill(&host->finish_task);
|
|
|
|
#ifdef CONFIG_SOC_AU1200
|
|
au1xmmc_dbdma_shutdown(host);
|
|
#endif
|
|
au1xmmc_set_power(host, 0);
|
|
|
|
free_irq(host->irq, host);
|
|
iounmap((void *)host->iobase);
|
|
release_resource(host->ioarea);
|
|
kfree(host->ioarea);
|
|
|
|
mmc_free_host(host->mmc);
|
|
platform_set_drvdata(pdev, NULL);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
struct au1xmmc_host *host = platform_get_drvdata(pdev);
|
|
int ret;
|
|
|
|
ret = mmc_suspend_host(host->mmc, state);
|
|
if (ret)
|
|
return ret;
|
|
|
|
au_writel(0, HOST_CONFIG2(host));
|
|
au_writel(0, HOST_CONFIG(host));
|
|
au_writel(0xffffffff, HOST_STATUS(host));
|
|
au_writel(0, HOST_ENABLE(host));
|
|
au_sync();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int au1xmmc_resume(struct platform_device *pdev)
|
|
{
|
|
struct au1xmmc_host *host = platform_get_drvdata(pdev);
|
|
|
|
au1xmmc_reset_controller(host);
|
|
|
|
return mmc_resume_host(host->mmc);
|
|
}
|
|
#else
|
|
#define au1xmmc_suspend NULL
|
|
#define au1xmmc_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver au1xmmc_driver = {
|
|
.probe = au1xmmc_probe,
|
|
.remove = au1xmmc_remove,
|
|
.suspend = au1xmmc_suspend,
|
|
.resume = au1xmmc_resume,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init au1xmmc_init(void)
|
|
{
|
|
#ifdef CONFIG_SOC_AU1200
|
|
/* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
|
|
* of 8 bits. And since devices are shared, we need to create
|
|
* our own to avoid freaking out other devices.
|
|
*/
|
|
memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
|
|
if (!memid)
|
|
printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n");
|
|
#endif
|
|
return platform_driver_register(&au1xmmc_driver);
|
|
}
|
|
|
|
static void __exit au1xmmc_exit(void)
|
|
{
|
|
#ifdef CONFIG_SOC_AU1200
|
|
if (memid)
|
|
au1xxx_ddma_del_device(memid);
|
|
#endif
|
|
platform_driver_unregister(&au1xmmc_driver);
|
|
}
|
|
|
|
module_init(au1xmmc_init);
|
|
module_exit(au1xmmc_exit);
|
|
|
|
MODULE_AUTHOR("Advanced Micro Devices, Inc");
|
|
MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:au1xxx-mmc");
|