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30c7e5b123
Zhang Rui reported that a Surface Pro 4 will fail to boot with lapic=notscdeadline. Part of the problem is that that machine doesn't have a PIT. If, for some reason, the TSC init has to fall back to TSC calibration, it relies on the PIT to be present. Allow TSC calibration to reliably fall back to HPET. The below results in an accurate TSC measurement when forced on a IVB: tsc: Unable to calibrate against PIT tsc: No reference (HPET/PMTIMER) available tsc: Unable to calibrate against PIT tsc: using HPET reference calibration tsc: Detected 2792.451 MHz processor Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: len.brown@intel.com Cc: rui.zhang@intel.com Link: https://lkml.kernel.org/r/20171222092243.333145937@infradead.org
82 lines
1.9 KiB
C
82 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_I8259_H
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#define _ASM_X86_I8259_H
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#include <linux/delay.h>
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extern unsigned int cached_irq_mask;
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#define __byte(x, y) (((unsigned char *)&(y))[x])
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#define cached_master_mask (__byte(0, cached_irq_mask))
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#define cached_slave_mask (__byte(1, cached_irq_mask))
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/* i8259A PIC registers */
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#define PIC_MASTER_CMD 0x20
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#define PIC_MASTER_IMR 0x21
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#define PIC_MASTER_ISR PIC_MASTER_CMD
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#define PIC_MASTER_POLL PIC_MASTER_ISR
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#define PIC_MASTER_OCW3 PIC_MASTER_ISR
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#define PIC_SLAVE_CMD 0xa0
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#define PIC_SLAVE_IMR 0xa1
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/* i8259A PIC related value */
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#define PIC_CASCADE_IR 2
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#define MASTER_ICW4_DEFAULT 0x01
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#define SLAVE_ICW4_DEFAULT 0x01
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#define PIC_ICW4_AEOI 2
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extern raw_spinlock_t i8259A_lock;
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/* the PIC may need a careful delay on some platforms, hence specific calls */
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static inline unsigned char inb_pic(unsigned int port)
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{
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unsigned char value = inb(port);
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/*
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* delay for some accesses to PIC on motherboard or in chipset
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* must be at least one microsecond, so be safe here:
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*/
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udelay(2);
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return value;
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}
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static inline void outb_pic(unsigned char value, unsigned int port)
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{
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outb(value, port);
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/*
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* delay for some accesses to PIC on motherboard or in chipset
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* must be at least one microsecond, so be safe here:
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*/
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udelay(2);
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}
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extern struct irq_chip i8259A_chip;
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struct legacy_pic {
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int nr_legacy_irqs;
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struct irq_chip *chip;
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void (*mask)(unsigned int irq);
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void (*unmask)(unsigned int irq);
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void (*mask_all)(void);
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void (*restore_mask)(void);
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void (*init)(int auto_eoi);
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int (*probe)(void);
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int (*irq_pending)(unsigned int irq);
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void (*make_irq)(unsigned int irq);
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};
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extern struct legacy_pic *legacy_pic;
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extern struct legacy_pic null_legacy_pic;
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static inline bool has_legacy_pic(void)
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{
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return legacy_pic != &null_legacy_pic;
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}
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static inline int nr_legacy_irqs(void)
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{
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return legacy_pic->nr_legacy_irqs;
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}
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#endif /* _ASM_X86_I8259_H */
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