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![Philip, Avinash](/assets/img/avatar_default.png)
EHRPWM hardware supports 2 independent PWM channels. However the device uses only one register to handle period setting for both channels. So both channels should be configured for same period (in nsec). Fix the same by returning error for conflicting period values. However, allow 1. Configuration of period settings if not conflicting with other channels 2. Re-configuring of period settings if no other channels being configured Signed-off-by: Philip, Avinash <avinashphilip@ti.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
438 lines
12 KiB
C
438 lines
12 KiB
C
/*
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* EHRPWM PWM driver
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*
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* Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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/* EHRPWM registers and bits definitions */
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/* Time base module registers */
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#define TBCTL 0x00
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#define TBPRD 0x0A
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#define TBCTL_RUN_MASK (BIT(15) | BIT(14))
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#define TBCTL_STOP_NEXT 0
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#define TBCTL_STOP_ON_CYCLE BIT(14)
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#define TBCTL_FREE_RUN (BIT(15) | BIT(14))
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#define TBCTL_PRDLD_MASK BIT(3)
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#define TBCTL_PRDLD_SHDW 0
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#define TBCTL_PRDLD_IMDT BIT(3)
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#define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \
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BIT(8) | BIT(7))
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#define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0))
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#define TBCTL_CTRMODE_UP 0
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#define TBCTL_CTRMODE_DOWN BIT(0)
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#define TBCTL_CTRMODE_UPDOWN BIT(1)
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#define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0))
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#define TBCTL_HSPCLKDIV_SHIFT 7
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#define TBCTL_CLKDIV_SHIFT 10
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#define CLKDIV_MAX 7
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#define HSPCLKDIV_MAX 7
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#define PERIOD_MAX 0xFFFF
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/* compare module registers */
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#define CMPA 0x12
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#define CMPB 0x14
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/* Action qualifier module registers */
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#define AQCTLA 0x16
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#define AQCTLB 0x18
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#define AQSFRC 0x1A
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#define AQCSFRC 0x1C
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#define AQCTL_CBU_MASK (BIT(9) | BIT(8))
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#define AQCTL_CBU_FRCLOW BIT(8)
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#define AQCTL_CBU_FRCHIGH BIT(9)
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#define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8))
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#define AQCTL_CAU_MASK (BIT(5) | BIT(4))
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#define AQCTL_CAU_FRCLOW BIT(4)
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#define AQCTL_CAU_FRCHIGH BIT(5)
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#define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4))
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#define AQCTL_PRD_MASK (BIT(3) | BIT(2))
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#define AQCTL_PRD_FRCLOW BIT(2)
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#define AQCTL_PRD_FRCHIGH BIT(3)
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#define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2))
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#define AQCTL_ZRO_MASK (BIT(1) | BIT(0))
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#define AQCTL_ZRO_FRCLOW BIT(0)
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#define AQCTL_ZRO_FRCHIGH BIT(1)
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#define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0))
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#define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6))
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#define AQSFRC_RLDCSF_ZRO 0
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#define AQSFRC_RLDCSF_PRD BIT(6)
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#define AQSFRC_RLDCSF_ZROPRD BIT(7)
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#define AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6))
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#define AQCSFRC_CSFB_MASK (BIT(3) | BIT(2))
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#define AQCSFRC_CSFB_FRCDIS 0
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#define AQCSFRC_CSFB_FRCLOW BIT(2)
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#define AQCSFRC_CSFB_FRCHIGH BIT(3)
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#define AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2))
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#define AQCSFRC_CSFA_MASK (BIT(1) | BIT(0))
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#define AQCSFRC_CSFA_FRCDIS 0
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#define AQCSFRC_CSFA_FRCLOW BIT(0)
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#define AQCSFRC_CSFA_FRCHIGH BIT(1)
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#define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0))
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#define NUM_PWM_CHANNEL 2 /* EHRPWM channels */
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struct ehrpwm_pwm_chip {
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struct pwm_chip chip;
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unsigned int clk_rate;
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void __iomem *mmio_base;
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unsigned long period_cycles[NUM_PWM_CHANNEL];
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};
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static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct ehrpwm_pwm_chip, chip);
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}
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static void ehrpwm_write(void *base, int offset, unsigned int val)
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{
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writew(val & 0xFFFF, base + offset);
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}
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static void ehrpwm_modify(void *base, int offset,
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unsigned short mask, unsigned short val)
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{
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unsigned short regval;
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regval = readw(base + offset);
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regval &= ~mask;
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regval |= val & mask;
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writew(regval, base + offset);
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}
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/**
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* set_prescale_div - Set up the prescaler divider function
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* @rqst_prescaler: prescaler value min
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* @prescale_div: prescaler value set
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* @tb_clk_div: Time Base Control prescaler bits
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*/
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static int set_prescale_div(unsigned long rqst_prescaler,
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unsigned short *prescale_div, unsigned short *tb_clk_div)
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{
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unsigned int clkdiv, hspclkdiv;
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for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) {
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for (hspclkdiv = 0; hspclkdiv <= HSPCLKDIV_MAX; hspclkdiv++) {
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/*
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* calculations for prescaler value :
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* prescale_div = HSPCLKDIVIDER * CLKDIVIDER.
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* HSPCLKDIVIDER = 2 ** hspclkdiv
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* CLKDIVIDER = (1), if clkdiv == 0 *OR*
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* (2 * clkdiv), if clkdiv != 0
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*
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* Configure prescale_div value such that period
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* register value is less than 65535.
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*/
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*prescale_div = (1 << clkdiv) *
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(hspclkdiv ? (hspclkdiv * 2) : 1);
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if (*prescale_div > rqst_prescaler) {
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*tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) |
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(hspclkdiv << TBCTL_HSPCLKDIV_SHIFT);
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return 0;
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}
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}
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}
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return 1;
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}
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static void configure_chans(struct ehrpwm_pwm_chip *pc, int chan,
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unsigned long duty_cycles)
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{
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int cmp_reg, aqctl_reg;
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unsigned short aqctl_val, aqctl_mask;
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/*
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* Channels can be configured from action qualifier module.
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* Channel 0 configured with compare A register and for
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* up-counter mode.
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* Channel 1 configured with compare B register and for
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* up-counter mode.
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*/
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if (chan == 1) {
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aqctl_reg = AQCTLB;
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cmp_reg = CMPB;
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/* Configure PWM Low from compare B value */
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aqctl_val = AQCTL_CBU_FRCLOW;
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aqctl_mask = AQCTL_CBU_MASK;
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} else {
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cmp_reg = CMPA;
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aqctl_reg = AQCTLA;
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/* Configure PWM Low from compare A value*/
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aqctl_val = AQCTL_CAU_FRCLOW;
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aqctl_mask = AQCTL_CAU_MASK;
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}
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/* Configure PWM High from period value and zero value */
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aqctl_val |= AQCTL_PRD_FRCHIGH | AQCTL_ZRO_FRCHIGH;
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aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK;
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ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);
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ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);
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}
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/*
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* period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE
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* duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE
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*/
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static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
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unsigned long long c;
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unsigned long period_cycles, duty_cycles;
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unsigned short ps_divval, tb_divval;
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int i;
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if (period_ns < 0 || duty_ns < 0 || period_ns > NSEC_PER_SEC)
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return -ERANGE;
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c = pc->clk_rate;
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c = c * period_ns;
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do_div(c, NSEC_PER_SEC);
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period_cycles = (unsigned long)c;
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if (period_cycles < 1) {
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period_cycles = 1;
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duty_cycles = 1;
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} else {
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c = pc->clk_rate;
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c = c * duty_ns;
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do_div(c, NSEC_PER_SEC);
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duty_cycles = (unsigned long)c;
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}
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/*
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* Period values should be same for multiple PWM channels as IP uses
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* same period register for multiple channels.
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*/
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for (i = 0; i < NUM_PWM_CHANNEL; i++) {
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if (pc->period_cycles[i] &&
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(pc->period_cycles[i] != period_cycles)) {
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/*
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* Allow channel to reconfigure period if no other
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* channels being configured.
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*/
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if (i == pwm->hwpwm)
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continue;
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dev_err(chip->dev, "Period value conflicts with channel %d\n",
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i);
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return -EINVAL;
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}
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}
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pc->period_cycles[pwm->hwpwm] = period_cycles;
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/* Configure clock prescaler to support Low frequency PWM wave */
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if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval,
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&tb_divval)) {
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dev_err(chip->dev, "Unsupported values\n");
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return -EINVAL;
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}
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pm_runtime_get_sync(chip->dev);
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/* Update clock prescaler values */
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ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval);
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/* Update period & duty cycle with presacler division */
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period_cycles = period_cycles / ps_divval;
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duty_cycles = duty_cycles / ps_divval;
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/* Configure shadow loading on Period register */
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ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW);
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ehrpwm_write(pc->mmio_base, TBPRD, period_cycles);
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/* Configure ehrpwm counter for up-count mode */
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ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,
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TBCTL_CTRMODE_UP);
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/* Configure the channel for duty cycle */
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configure_chans(pc, pwm->hwpwm, duty_cycles);
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pm_runtime_put_sync(chip->dev);
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return 0;
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}
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static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
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unsigned short aqcsfrc_val, aqcsfrc_mask;
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/* Leave clock enabled on enabling PWM */
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pm_runtime_get_sync(chip->dev);
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/* Disabling Action Qualifier on PWM output */
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if (pwm->hwpwm) {
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aqcsfrc_val = AQCSFRC_CSFB_FRCDIS;
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aqcsfrc_mask = AQCSFRC_CSFB_MASK;
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} else {
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aqcsfrc_val = AQCSFRC_CSFA_FRCDIS;
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aqcsfrc_mask = AQCSFRC_CSFA_MASK;
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}
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/* Changes to shadow mode */
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ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
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AQSFRC_RLDCSF_ZRO);
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ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
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/* Enable time counter for free_run */
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ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN);
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return 0;
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}
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static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
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unsigned short aqcsfrc_val, aqcsfrc_mask;
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/* Action Qualifier puts PWM output low forcefully */
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if (pwm->hwpwm) {
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aqcsfrc_val = AQCSFRC_CSFB_FRCLOW;
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aqcsfrc_mask = AQCSFRC_CSFB_MASK;
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} else {
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aqcsfrc_val = AQCSFRC_CSFA_FRCLOW;
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aqcsfrc_mask = AQCSFRC_CSFA_MASK;
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}
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/*
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* Changes to immediate action on Action Qualifier. This puts
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* Action Qualifier control on PWM output from next TBCLK
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*/
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ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
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AQSFRC_RLDCSF_IMDT);
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ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
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/* Stop Time base counter */
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ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_STOP_NEXT);
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/* Disable clock on PWM disable */
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pm_runtime_put_sync(chip->dev);
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}
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static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);
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if (test_bit(PWMF_ENABLED, &pwm->flags)) {
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dev_warn(chip->dev, "Removing PWM device without disabling\n");
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pm_runtime_put_sync(chip->dev);
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}
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/* set period value to zero on free */
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pc->period_cycles[pwm->hwpwm] = 0;
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}
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static const struct pwm_ops ehrpwm_pwm_ops = {
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.free = ehrpwm_pwm_free,
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.config = ehrpwm_pwm_config,
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.enable = ehrpwm_pwm_enable,
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.disable = ehrpwm_pwm_disable,
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.owner = THIS_MODULE,
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};
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static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev)
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{
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int ret;
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struct resource *r;
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struct clk *clk;
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struct ehrpwm_pwm_chip *pc;
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pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
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if (!pc) {
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dev_err(&pdev->dev, "failed to allocate memory\n");
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return -ENOMEM;
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}
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clk = devm_clk_get(&pdev->dev, "fck");
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "failed to get clock\n");
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return PTR_ERR(clk);
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}
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pc->clk_rate = clk_get_rate(clk);
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if (!pc->clk_rate) {
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dev_err(&pdev->dev, "failed to get clock rate\n");
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return -EINVAL;
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}
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pc->chip.dev = &pdev->dev;
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pc->chip.ops = &ehrpwm_pwm_ops;
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pc->chip.base = -1;
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pc->chip.npwm = NUM_PWM_CHANNEL;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pdev->dev, "no memory resource defined\n");
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return -ENODEV;
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}
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pc->mmio_base = devm_request_and_ioremap(&pdev->dev, r);
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if (!pc->mmio_base)
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return -EADDRNOTAVAIL;
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ret = pwmchip_add(&pc->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
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return ret;
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}
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pm_runtime_enable(&pdev->dev);
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platform_set_drvdata(pdev, pc);
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return 0;
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}
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static int __devexit ehrpwm_pwm_remove(struct platform_device *pdev)
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{
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struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev);
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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return pwmchip_remove(&pc->chip);
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}
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static struct platform_driver ehrpwm_pwm_driver = {
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.driver = {
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.name = "ehrpwm",
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},
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.probe = ehrpwm_pwm_probe,
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.remove = __devexit_p(ehrpwm_pwm_remove),
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};
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module_platform_driver(ehrpwm_pwm_driver);
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MODULE_DESCRIPTION("EHRPWM PWM driver");
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MODULE_AUTHOR("Texas Instruments");
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MODULE_LICENSE("GPL");
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