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![Navin P](/assets/img/avatar_default.png)
Signed-off-by: Navin P <zicrim@gmail.com> Cc: Alessandro Zummo <a.zummo@towertech.it> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
540 lines
14 KiB
C
540 lines
14 KiB
C
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/rtc.h>
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#include <linux/pm.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/mfd/pm8xxx/core.h>
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#include <linux/mfd/pm8xxx/rtc.h>
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/* RTC Register offsets from RTC CTRL REG */
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#define PM8XXX_ALARM_CTRL_OFFSET 0x01
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#define PM8XXX_RTC_WRITE_OFFSET 0x02
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#define PM8XXX_RTC_READ_OFFSET 0x06
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#define PM8XXX_ALARM_RW_OFFSET 0x0A
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/* RTC_CTRL register bit fields */
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#define PM8xxx_RTC_ENABLE BIT(7)
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#define PM8xxx_RTC_ALARM_ENABLE BIT(1)
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#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
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#define NUM_8_BIT_RTC_REGS 0x4
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/**
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* struct pm8xxx_rtc - rtc driver internal structure
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* @rtc: rtc device for this driver.
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* @rtc_alarm_irq: rtc alarm irq number.
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* @rtc_base: address of rtc control register.
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* @rtc_read_base: base address of read registers.
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* @rtc_write_base: base address of write registers.
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* @alarm_rw_base: base address of alarm registers.
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* @ctrl_reg: rtc control register.
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* @rtc_dev: device structure.
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* @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
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*/
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struct pm8xxx_rtc {
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struct rtc_device *rtc;
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int rtc_alarm_irq;
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int rtc_base;
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int rtc_read_base;
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int rtc_write_base;
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int alarm_rw_base;
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u8 ctrl_reg;
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struct device *rtc_dev;
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spinlock_t ctrl_reg_lock;
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};
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/*
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* The RTC registers need to be read/written one byte at a time. This is a
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* hardware limitation.
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*/
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static int pm8xxx_read_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val,
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int base, int count)
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{
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int i, rc;
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struct device *parent = rtc_dd->rtc_dev->parent;
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for (i = 0; i < count; i++) {
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rc = pm8xxx_readb(parent, base + i, &rtc_val[i]);
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if (rc < 0) {
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dev_err(rtc_dd->rtc_dev, "PMIC read failed\n");
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return rc;
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}
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}
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return 0;
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}
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static int pm8xxx_write_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val,
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int base, int count)
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{
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int i, rc;
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struct device *parent = rtc_dd->rtc_dev->parent;
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for (i = 0; i < count; i++) {
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rc = pm8xxx_writeb(parent, base + i, rtc_val[i]);
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if (rc < 0) {
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dev_err(rtc_dd->rtc_dev, "PMIC write failed\n");
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return rc;
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}
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}
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return 0;
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}
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/*
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* Steps to write the RTC registers.
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* 1. Disable alarm if enabled.
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* 2. Write 0x00 to LSB.
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* 3. Write Byte[1], Byte[2], Byte[3] then Byte[0].
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* 4. Enable alarm if disabled in step 1.
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*/
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static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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int rc, i;
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unsigned long secs, irq_flags;
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u8 value[NUM_8_BIT_RTC_REGS], reg = 0, alarm_enabled = 0, ctrl_reg;
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
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rtc_tm_to_time(tm, &secs);
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for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
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value[i] = secs & 0xFF;
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secs >>= 8;
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}
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dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
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spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
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ctrl_reg = rtc_dd->ctrl_reg;
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if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) {
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alarm_enabled = 1;
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ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
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rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base,
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1);
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if (rc < 0) {
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dev_err(dev, "Write to RTC control register "
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"failed\n");
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goto rtc_rw_fail;
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}
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rtc_dd->ctrl_reg = ctrl_reg;
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} else
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
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/* Write 0 to Byte[0] */
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reg = 0;
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rc = pm8xxx_write_wrapper(rtc_dd, ®, rtc_dd->rtc_write_base, 1);
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if (rc < 0) {
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dev_err(dev, "Write to RTC write data register failed\n");
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goto rtc_rw_fail;
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}
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/* Write Byte[1], Byte[2], Byte[3] */
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rc = pm8xxx_write_wrapper(rtc_dd, value + 1,
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rtc_dd->rtc_write_base + 1, 3);
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if (rc < 0) {
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dev_err(dev, "Write to RTC write data register failed\n");
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goto rtc_rw_fail;
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}
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/* Write Byte[0] */
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rc = pm8xxx_write_wrapper(rtc_dd, value, rtc_dd->rtc_write_base, 1);
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if (rc < 0) {
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dev_err(dev, "Write to RTC write data register failed\n");
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goto rtc_rw_fail;
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}
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if (alarm_enabled) {
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ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
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rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base,
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1);
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if (rc < 0) {
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dev_err(dev, "Write to RTC control register "
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"failed\n");
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goto rtc_rw_fail;
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}
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rtc_dd->ctrl_reg = ctrl_reg;
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}
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rtc_rw_fail:
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if (alarm_enabled)
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
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return rc;
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}
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static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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int rc;
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u8 value[NUM_8_BIT_RTC_REGS], reg;
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unsigned long secs;
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
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rc = pm8xxx_read_wrapper(rtc_dd, value, rtc_dd->rtc_read_base,
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NUM_8_BIT_RTC_REGS);
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if (rc < 0) {
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dev_err(dev, "RTC read data register failed\n");
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return rc;
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}
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/*
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* Read the LSB again and check if there has been a carry over.
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* If there is, redo the read operation.
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*/
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rc = pm8xxx_read_wrapper(rtc_dd, ®, rtc_dd->rtc_read_base, 1);
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if (rc < 0) {
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dev_err(dev, "RTC read data register failed\n");
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return rc;
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}
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if (unlikely(reg < value[0])) {
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rc = pm8xxx_read_wrapper(rtc_dd, value,
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rtc_dd->rtc_read_base, NUM_8_BIT_RTC_REGS);
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if (rc < 0) {
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dev_err(dev, "RTC read data register failed\n");
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return rc;
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}
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}
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secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
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rtc_time_to_tm(secs, tm);
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rc = rtc_valid_tm(tm);
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if (rc < 0) {
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dev_err(dev, "Invalid time read from RTC\n");
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return rc;
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}
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dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n",
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secs, tm->tm_hour, tm->tm_min, tm->tm_sec,
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tm->tm_mday, tm->tm_mon, tm->tm_year);
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return 0;
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}
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static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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int rc, i;
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u8 value[NUM_8_BIT_RTC_REGS], ctrl_reg;
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unsigned long secs, irq_flags;
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
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rtc_tm_to_time(&alarm->time, &secs);
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for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
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value[i] = secs & 0xFF;
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secs >>= 8;
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}
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spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
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rc = pm8xxx_write_wrapper(rtc_dd, value, rtc_dd->alarm_rw_base,
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NUM_8_BIT_RTC_REGS);
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if (rc < 0) {
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dev_err(dev, "Write to RTC ALARM register failed\n");
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goto rtc_rw_fail;
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}
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ctrl_reg = rtc_dd->ctrl_reg;
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ctrl_reg = alarm->enabled ? (ctrl_reg | PM8xxx_RTC_ALARM_ENABLE) :
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(ctrl_reg & ~PM8xxx_RTC_ALARM_ENABLE);
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rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1);
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if (rc < 0) {
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dev_err(dev, "Write to RTC control register failed\n");
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goto rtc_rw_fail;
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}
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rtc_dd->ctrl_reg = ctrl_reg;
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dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
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alarm->time.tm_hour, alarm->time.tm_min,
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alarm->time.tm_sec, alarm->time.tm_mday,
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alarm->time.tm_mon, alarm->time.tm_year);
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rtc_rw_fail:
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
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return rc;
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}
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static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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int rc;
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u8 value[NUM_8_BIT_RTC_REGS];
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unsigned long secs;
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
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rc = pm8xxx_read_wrapper(rtc_dd, value, rtc_dd->alarm_rw_base,
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NUM_8_BIT_RTC_REGS);
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if (rc < 0) {
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dev_err(dev, "RTC alarm time read failed\n");
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return rc;
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}
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secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
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rtc_time_to_tm(secs, &alarm->time);
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rc = rtc_valid_tm(&alarm->time);
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if (rc < 0) {
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dev_err(dev, "Invalid alarm time read from RTC\n");
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return rc;
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}
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dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
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alarm->time.tm_hour, alarm->time.tm_min,
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alarm->time.tm_sec, alarm->time.tm_mday,
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alarm->time.tm_mon, alarm->time.tm_year);
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return 0;
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}
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static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
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{
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int rc;
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unsigned long irq_flags;
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
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u8 ctrl_reg;
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spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
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ctrl_reg = rtc_dd->ctrl_reg;
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ctrl_reg = (enable) ? (ctrl_reg | PM8xxx_RTC_ALARM_ENABLE) :
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(ctrl_reg & ~PM8xxx_RTC_ALARM_ENABLE);
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rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1);
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if (rc < 0) {
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dev_err(dev, "Write to RTC control register failed\n");
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goto rtc_rw_fail;
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}
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rtc_dd->ctrl_reg = ctrl_reg;
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rtc_rw_fail:
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
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return rc;
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}
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static struct rtc_class_ops pm8xxx_rtc_ops = {
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.read_time = pm8xxx_rtc_read_time,
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.set_alarm = pm8xxx_rtc_set_alarm,
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.read_alarm = pm8xxx_rtc_read_alarm,
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.alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
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};
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static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
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{
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struct pm8xxx_rtc *rtc_dd = dev_id;
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u8 ctrl_reg;
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int rc;
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unsigned long irq_flags;
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rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
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spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
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/* Clear the alarm enable bit */
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ctrl_reg = rtc_dd->ctrl_reg;
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ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
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rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1);
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if (rc < 0) {
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
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dev_err(rtc_dd->rtc_dev, "Write to RTC control register "
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"failed\n");
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goto rtc_alarm_handled;
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}
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rtc_dd->ctrl_reg = ctrl_reg;
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
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/* Clear RTC alarm register */
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rc = pm8xxx_read_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base +
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PM8XXX_ALARM_CTRL_OFFSET, 1);
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if (rc < 0) {
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dev_err(rtc_dd->rtc_dev, "RTC Alarm control register read "
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"failed\n");
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goto rtc_alarm_handled;
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}
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ctrl_reg &= ~PM8xxx_RTC_ALARM_CLEAR;
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rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base +
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PM8XXX_ALARM_CTRL_OFFSET, 1);
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if (rc < 0)
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dev_err(rtc_dd->rtc_dev, "Write to RTC Alarm control register"
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" failed\n");
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rtc_alarm_handled:
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return IRQ_HANDLED;
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}
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static int __devinit pm8xxx_rtc_probe(struct platform_device *pdev)
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{
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int rc;
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u8 ctrl_reg;
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bool rtc_write_enable = false;
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struct pm8xxx_rtc *rtc_dd;
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struct resource *rtc_resource;
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const struct pm8xxx_rtc_platform_data *pdata =
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dev_get_platdata(&pdev->dev);
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if (pdata != NULL)
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rtc_write_enable = pdata->rtc_write_enable;
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rtc_dd = kzalloc(sizeof(*rtc_dd), GFP_KERNEL);
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if (rtc_dd == NULL) {
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dev_err(&pdev->dev, "Unable to allocate memory!\n");
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return -ENOMEM;
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}
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/* Initialise spinlock to protect RTC control register */
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spin_lock_init(&rtc_dd->ctrl_reg_lock);
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rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
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if (rtc_dd->rtc_alarm_irq < 0) {
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dev_err(&pdev->dev, "Alarm IRQ resource absent!\n");
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rc = -ENXIO;
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goto fail_rtc_enable;
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}
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rtc_resource = platform_get_resource_byname(pdev, IORESOURCE_IO,
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"pmic_rtc_base");
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if (!(rtc_resource && rtc_resource->start)) {
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dev_err(&pdev->dev, "RTC IO resource absent!\n");
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rc = -ENXIO;
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goto fail_rtc_enable;
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}
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rtc_dd->rtc_base = rtc_resource->start;
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/* Setup RTC register addresses */
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rtc_dd->rtc_write_base = rtc_dd->rtc_base + PM8XXX_RTC_WRITE_OFFSET;
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rtc_dd->rtc_read_base = rtc_dd->rtc_base + PM8XXX_RTC_READ_OFFSET;
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rtc_dd->alarm_rw_base = rtc_dd->rtc_base + PM8XXX_ALARM_RW_OFFSET;
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rtc_dd->rtc_dev = &pdev->dev;
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/* Check if the RTC is on, else turn it on */
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rc = pm8xxx_read_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1);
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if (rc < 0) {
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dev_err(&pdev->dev, "RTC control register read failed!\n");
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goto fail_rtc_enable;
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}
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if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
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ctrl_reg |= PM8xxx_RTC_ENABLE;
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rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base,
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1);
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if (rc < 0) {
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dev_err(&pdev->dev, "Write to RTC control register "
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"failed\n");
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goto fail_rtc_enable;
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}
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}
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rtc_dd->ctrl_reg = ctrl_reg;
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if (rtc_write_enable == true)
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pm8xxx_rtc_ops.set_time = pm8xxx_rtc_set_time;
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platform_set_drvdata(pdev, rtc_dd);
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/* Register the RTC device */
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rtc_dd->rtc = rtc_device_register("pm8xxx_rtc", &pdev->dev,
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&pm8xxx_rtc_ops, THIS_MODULE);
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if (IS_ERR(rtc_dd->rtc)) {
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dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
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__func__, PTR_ERR(rtc_dd->rtc));
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rc = PTR_ERR(rtc_dd->rtc);
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goto fail_rtc_enable;
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}
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/* Request the alarm IRQ */
|
|
rc = request_any_context_irq(rtc_dd->rtc_alarm_irq,
|
|
pm8xxx_alarm_trigger, IRQF_TRIGGER_RISING,
|
|
"pm8xxx_rtc_alarm", rtc_dd);
|
|
if (rc < 0) {
|
|
dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
|
|
goto fail_req_irq;
|
|
}
|
|
|
|
device_init_wakeup(&pdev->dev, 1);
|
|
|
|
dev_dbg(&pdev->dev, "Probe success !!\n");
|
|
|
|
return 0;
|
|
|
|
fail_req_irq:
|
|
rtc_device_unregister(rtc_dd->rtc);
|
|
fail_rtc_enable:
|
|
platform_set_drvdata(pdev, NULL);
|
|
kfree(rtc_dd);
|
|
return rc;
|
|
}
|
|
|
|
static int __devexit pm8xxx_rtc_remove(struct platform_device *pdev)
|
|
{
|
|
struct pm8xxx_rtc *rtc_dd = platform_get_drvdata(pdev);
|
|
|
|
device_init_wakeup(&pdev->dev, 0);
|
|
free_irq(rtc_dd->rtc_alarm_irq, rtc_dd);
|
|
rtc_device_unregister(rtc_dd->rtc);
|
|
platform_set_drvdata(pdev, NULL);
|
|
kfree(rtc_dd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int pm8xxx_rtc_resume(struct device *dev)
|
|
{
|
|
struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
|
|
|
|
if (device_may_wakeup(dev))
|
|
disable_irq_wake(rtc_dd->rtc_alarm_irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pm8xxx_rtc_suspend(struct device *dev)
|
|
{
|
|
struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
|
|
|
|
if (device_may_wakeup(dev))
|
|
enable_irq_wake(rtc_dd->rtc_alarm_irq);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops, pm8xxx_rtc_suspend, pm8xxx_rtc_resume);
|
|
|
|
static struct platform_driver pm8xxx_rtc_driver = {
|
|
.probe = pm8xxx_rtc_probe,
|
|
.remove = __devexit_p(pm8xxx_rtc_remove),
|
|
.driver = {
|
|
.name = PM8XXX_RTC_DEV_NAME,
|
|
.owner = THIS_MODULE,
|
|
.pm = &pm8xxx_rtc_pm_ops,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(pm8xxx_rtc_driver);
|
|
|
|
MODULE_ALIAS("platform:rtc-pm8xxx");
|
|
MODULE_DESCRIPTION("PMIC8xxx RTC driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
|