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343e64a6c4
Add all RZ/G1C Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2 ("List of Clocks [RZ/G1C]") of the RZ/G1C Hardware User's
Manual.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
[geert: Use consecutive numbering]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
36 lines
992 B
C
36 lines
992 B
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a77470 CPG Core Clocks */
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#define R8A77470_CLK_Z2 0
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#define R8A77470_CLK_ZTR 1
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#define R8A77470_CLK_ZTRD2 2
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#define R8A77470_CLK_ZT 3
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#define R8A77470_CLK_ZX 4
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#define R8A77470_CLK_ZS 5
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#define R8A77470_CLK_HP 6
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#define R8A77470_CLK_B 7
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#define R8A77470_CLK_LB 8
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#define R8A77470_CLK_P 9
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#define R8A77470_CLK_CL 10
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#define R8A77470_CLK_CP 11
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#define R8A77470_CLK_M2 12
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#define R8A77470_CLK_ZB3 13
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#define R8A77470_CLK_SDH 14
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#define R8A77470_CLK_SD0 15
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#define R8A77470_CLK_SD1 16
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#define R8A77470_CLK_SD2 17
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#define R8A77470_CLK_MP 18
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#define R8A77470_CLK_QSPI 19
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#define R8A77470_CLK_CPEX 20
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#define R8A77470_CLK_RCAN 21
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#define R8A77470_CLK_R 22
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#define R8A77470_CLK_OSC 23
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#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */
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