Chris Wilson f4ce766f28 drm/i915: Align "unfenced" tiled access on gen2, early gen3 ... Old devices have quite severe restrictions for using fences, and unlike more recent device (anything from Pineview onwards) we need to enforce those restrictions even for unfenced tiled access from the render pipeline. Fixes: 944397f04f ("drm/i915: Store required fence size/alignment for GGTT vma") Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: <drm-intel-fixes@lists.freedesktop.org> # v4.11-rc1+ Link: http://patchwork.freedesktop.org/patch/msgid/20170325113243.16438-1-chris@chris-wilson.co.uk Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>		2017-03-27 12:48:45 +01:00
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drm	drm/i915: Align "unfenced" tiled access on gen2, early gen3	2017-03-27 12:48:45 +01:00
host1x	gpu: host1x: Set OF node for new host1x devices	2017-01-30 11:47:44 +01:00
ipu-v3	gpu: ipu-v3: only set non-zero AXI ID for IC when PRG is absent	2017-03-16 10:14:49 +01:00
vga	Pointer for Markus's image conversion work.	2017-03-14 15:07:33 +01:00
Makefile