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c9c2877d08
The firmare in most parisc machines maintains a Page Deallocation Table (PDT) which holds a list of physical memory addresses where hardware detected memory errors (single bit and double bit errors). This patch adds the missing PDC firmware calls and the logic to read the PDT from firmware, report all current PDT entries and exclude the reported bad memory from being used by Linux. Signed-off-by: Helge Deller <deller@gmx.de>
427 lines
15 KiB
C
427 lines
15 KiB
C
#ifndef _UAPI_PARISC_PDC_H
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#define _UAPI_PARISC_PDC_H
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/*
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* PDC return values ...
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* All PDC calls return a subset of these errors.
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*/
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#define PDC_WARN 3 /* Call completed with a warning */
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#define PDC_REQ_ERR_1 2 /* See above */
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#define PDC_REQ_ERR_0 1 /* Call would generate a requestor error */
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#define PDC_OK 0 /* Call completed successfully */
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#define PDC_BAD_PROC -1 /* Called non-existent procedure*/
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#define PDC_BAD_OPTION -2 /* Called with non-existent option */
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#define PDC_ERROR -3 /* Call could not complete without an error */
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#define PDC_NE_MOD -5 /* Module not found */
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#define PDC_NE_CELL_MOD -7 /* Cell module not found */
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#define PDC_INVALID_ARG -10 /* Called with an invalid argument */
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#define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */
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#define PDC_NOT_NARROW -17 /* Narrow mode not supported */
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/*
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* PDC entry points...
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*/
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#define PDC_POW_FAIL 1 /* perform a power-fail */
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#define PDC_POW_FAIL_PREPARE 0 /* prepare for powerfail */
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#define PDC_CHASSIS 2 /* PDC-chassis functions */
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#define PDC_CHASSIS_DISP 0 /* update chassis display */
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#define PDC_CHASSIS_WARN 1 /* return chassis warnings */
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#define PDC_CHASSIS_DISPWARN 2 /* update&return chassis status */
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#define PDC_RETURN_CHASSIS_INFO 128 /* HVERSION dependent: return chassis LED/LCD info */
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#define PDC_PIM 3 /* Get PIM data */
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#define PDC_PIM_HPMC 0 /* Transfer HPMC data */
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#define PDC_PIM_RETURN_SIZE 1 /* Get Max buffer needed for PIM*/
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#define PDC_PIM_LPMC 2 /* Transfer HPMC data */
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#define PDC_PIM_SOFT_BOOT 3 /* Transfer Soft Boot data */
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#define PDC_PIM_TOC 4 /* Transfer TOC data */
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#define PDC_MODEL 4 /* PDC model information call */
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#define PDC_MODEL_INFO 0 /* returns information */
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#define PDC_MODEL_BOOTID 1 /* set the BOOT_ID */
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#define PDC_MODEL_VERSIONS 2 /* returns cpu-internal versions*/
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#define PDC_MODEL_SYSMODEL 3 /* return system model info */
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#define PDC_MODEL_ENSPEC 4 /* enable specific option */
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#define PDC_MODEL_DISPEC 5 /* disable specific option */
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#define PDC_MODEL_CPU_ID 6 /* returns cpu-id (only newer machines!) */
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#define PDC_MODEL_CAPABILITIES 7 /* returns OS32/OS64-flags */
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/* Values for PDC_MODEL_CAPABILITIES non-equivalent virtual aliasing support */
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#define PDC_MODEL_OS64 (1 << 0)
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#define PDC_MODEL_OS32 (1 << 1)
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#define PDC_MODEL_IOPDIR_FDC (1 << 2)
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#define PDC_MODEL_NVA_MASK (3 << 4)
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#define PDC_MODEL_NVA_SUPPORTED (0 << 4)
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#define PDC_MODEL_NVA_SLOW (1 << 4)
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#define PDC_MODEL_NVA_UNSUPPORTED (3 << 4)
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#define PDC_MODEL_GET_BOOT__OP 8 /* returns boot test options */
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#define PDC_MODEL_SET_BOOT__OP 9 /* set boot test options */
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#define PA89_INSTRUCTION_SET 0x4 /* capabilities returned */
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#define PA90_INSTRUCTION_SET 0x8
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#define PDC_CACHE 5 /* return/set cache (& TLB) info*/
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#define PDC_CACHE_INFO 0 /* returns information */
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#define PDC_CACHE_SET_COH 1 /* set coherence state */
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#define PDC_CACHE_RET_SPID 2 /* returns space-ID bits */
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#define PDC_HPA 6 /* return HPA of processor */
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#define PDC_HPA_PROCESSOR 0
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#define PDC_HPA_MODULES 1
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#define PDC_COPROC 7 /* Co-Processor (usually FP unit(s)) */
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#define PDC_COPROC_CFG 0 /* Co-Processor Cfg (FP unit(s) enabled?) */
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#define PDC_IODC 8 /* talk to IODC */
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#define PDC_IODC_READ 0 /* read IODC entry point */
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/* PDC_IODC_RI_ * INDEX parameter of PDC_IODC_READ */
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#define PDC_IODC_RI_DATA_BYTES 0 /* IODC Data Bytes */
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/* 1, 2 obsolete - HVERSION dependent*/
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#define PDC_IODC_RI_INIT 3 /* Initialize module */
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#define PDC_IODC_RI_IO 4 /* Module input/output */
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#define PDC_IODC_RI_SPA 5 /* Module input/output */
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#define PDC_IODC_RI_CONFIG 6 /* Module input/output */
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/* 7 obsolete - HVERSION dependent */
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#define PDC_IODC_RI_TEST 8 /* Module input/output */
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#define PDC_IODC_RI_TLB 9 /* Module input/output */
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#define PDC_IODC_NINIT 2 /* non-destructive init */
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#define PDC_IODC_DINIT 3 /* destructive init */
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#define PDC_IODC_MEMERR 4 /* check for memory errors */
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#define PDC_IODC_INDEX_DATA 0 /* get first 16 bytes from mod IODC */
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#define PDC_IODC_BUS_ERROR -4 /* bus error return value */
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#define PDC_IODC_INVALID_INDEX -5 /* invalid index return value */
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#define PDC_IODC_COUNT -6 /* count is too small */
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#define PDC_TOD 9 /* time-of-day clock (TOD) */
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#define PDC_TOD_READ 0 /* read TOD */
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#define PDC_TOD_WRITE 1 /* write TOD */
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#define PDC_STABLE 10 /* stable storage (sprockets) */
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#define PDC_STABLE_READ 0
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#define PDC_STABLE_WRITE 1
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#define PDC_STABLE_RETURN_SIZE 2
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#define PDC_STABLE_VERIFY_CONTENTS 3
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#define PDC_STABLE_INITIALIZE 4
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#define PDC_NVOLATILE 11 /* often not implemented */
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#define PDC_ADD_VALID 12 /* Memory validation PDC call */
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#define PDC_ADD_VALID_VERIFY 0 /* Make PDC_ADD_VALID verify region */
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#define PDC_INSTR 15 /* get instr to invoke PDCE_CHECK() */
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#define PDC_PROC 16 /* (sprockets) */
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#define PDC_CONFIG 16 /* (sprockets) */
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#define PDC_CONFIG_DECONFIG 0
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#define PDC_CONFIG_DRECONFIG 1
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#define PDC_CONFIG_DRETURN_CONFIG 2
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#define PDC_BLOCK_TLB 18 /* manage hardware block-TLB */
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#define PDC_BTLB_INFO 0 /* returns parameter */
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#define PDC_BTLB_INSERT 1 /* insert BTLB entry */
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#define PDC_BTLB_PURGE 2 /* purge BTLB entries */
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#define PDC_BTLB_PURGE_ALL 3 /* purge all BTLB entries */
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#define PDC_TLB 19 /* manage hardware TLB miss handling */
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#define PDC_TLB_INFO 0 /* returns parameter */
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#define PDC_TLB_SETUP 1 /* set up miss handling */
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#define PDC_MEM 20 /* Manage memory */
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#define PDC_MEM_MEMINFO 0 /* Return PDT info */
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#define PDC_MEM_ADD_PAGE 1 /* Add page to PDT */
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#define PDC_MEM_CLEAR_PDT 2 /* Clear PDT */
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#define PDC_MEM_READ_PDT 3 /* Read PDT entry */
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#define PDC_MEM_RESET_CLEAR 4 /* Reset PDT clear flag */
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#define PDC_MEM_GOODMEM 5 /* Set good_mem value */
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#define PDC_MEM_TABLE 128 /* Non contig mem map (sprockets) */
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#define PDC_MEM_RETURN_ADDRESS_TABLE PDC_MEM_TABLE
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#define PDC_MEM_GET_MEMORY_SYSTEM_TABLES_SIZE 131
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#define PDC_MEM_GET_MEMORY_SYSTEM_TABLES 132
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#define PDC_MEM_GET_PHYSICAL_LOCATION_FROM_MEMORY_ADDRESS 133
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#define PDC_MEM_RET_SBE_REPLACED 5 /* PDC_MEM return values */
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#define PDC_MEM_RET_DUPLICATE_ENTRY 4
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#define PDC_MEM_RET_BUF_SIZE_SMALL 1
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#define PDC_MEM_RET_PDT_FULL -11
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#define PDC_MEM_RET_INVALID_PHYSICAL_LOCATION ~0ULL
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#define PDC_PSW 21 /* Get/Set default System Mask */
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#define PDC_PSW_MASK 0 /* Return mask */
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#define PDC_PSW_GET_DEFAULTS 1 /* Return defaults */
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#define PDC_PSW_SET_DEFAULTS 2 /* Set default */
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#define PDC_PSW_ENDIAN_BIT 1 /* set for big endian */
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#define PDC_PSW_WIDE_BIT 2 /* set for wide mode */
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#define PDC_SYSTEM_MAP 22 /* find system modules */
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#define PDC_FIND_MODULE 0
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#define PDC_FIND_ADDRESS 1
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#define PDC_TRANSLATE_PATH 2
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#define PDC_SOFT_POWER 23 /* soft power switch */
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#define PDC_SOFT_POWER_INFO 0 /* return info about the soft power switch */
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#define PDC_SOFT_POWER_ENABLE 1 /* enable/disable soft power switch */
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/* HVERSION dependent */
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/* The PDC_MEM_MAP calls */
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#define PDC_MEM_MAP 128 /* on s700: return page info */
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#define PDC_MEM_MAP_HPA 0 /* returns hpa of a module */
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#define PDC_EEPROM 129 /* EEPROM access */
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#define PDC_EEPROM_READ_WORD 0
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#define PDC_EEPROM_WRITE_WORD 1
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#define PDC_EEPROM_READ_BYTE 2
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#define PDC_EEPROM_WRITE_BYTE 3
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#define PDC_EEPROM_EEPROM_PASSWORD -1000
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#define PDC_NVM 130 /* NVM (non-volatile memory) access */
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#define PDC_NVM_READ_WORD 0
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#define PDC_NVM_WRITE_WORD 1
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#define PDC_NVM_READ_BYTE 2
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#define PDC_NVM_WRITE_BYTE 3
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#define PDC_SEED_ERROR 132 /* (sprockets) */
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#define PDC_IO 135 /* log error info, reset IO system */
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#define PDC_IO_READ_AND_CLEAR_ERRORS 0
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#define PDC_IO_RESET 1
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#define PDC_IO_RESET_DEVICES 2
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/* sets bits 6&7 (little endian) of the HcControl Register */
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#define PDC_IO_USB_SUSPEND 0xC000000000000000
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#define PDC_IO_EEPROM_IO_ERR_TABLE_FULL -5 /* return value */
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#define PDC_IO_NO_SUSPEND -6 /* return value */
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#define PDC_BROADCAST_RESET 136 /* reset all processors */
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#define PDC_DO_RESET 0 /* option: perform a broadcast reset */
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#define PDC_DO_FIRM_TEST_RESET 1 /* Do broadcast reset with bitmap */
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#define PDC_BR_RECONFIGURATION 2 /* reset w/reconfiguration */
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#define PDC_FIRM_TEST_MAGIC 0xab9ec36fUL /* for this reboot only */
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#define PDC_LAN_STATION_ID 138 /* Hversion dependent mechanism for */
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#define PDC_LAN_STATION_ID_READ 0 /* getting the lan station address */
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#define PDC_LAN_STATION_ID_SIZE 6
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#define PDC_CHECK_RANGES 139 /* (sprockets) */
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#define PDC_NV_SECTIONS 141 /* (sprockets) */
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#define PDC_PERFORMANCE 142 /* performance monitoring */
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#define PDC_SYSTEM_INFO 143 /* system information */
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#define PDC_SYSINFO_RETURN_INFO_SIZE 0
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#define PDC_SYSINFO_RRETURN_SYS_INFO 1
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#define PDC_SYSINFO_RRETURN_ERRORS 2
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#define PDC_SYSINFO_RRETURN_WARNINGS 3
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#define PDC_SYSINFO_RETURN_REVISIONS 4
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#define PDC_SYSINFO_RRETURN_DIAGNOSE 5
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#define PDC_SYSINFO_RRETURN_HV_DIAGNOSE 1005
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#define PDC_RDR 144 /* (sprockets) */
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#define PDC_RDR_READ_BUFFER 0
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#define PDC_RDR_READ_SINGLE 1
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#define PDC_RDR_WRITE_SINGLE 2
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#define PDC_INTRIGUE 145 /* (sprockets) */
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#define PDC_INTRIGUE_WRITE_BUFFER 0
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#define PDC_INTRIGUE_GET_SCRATCH_BUFSIZE 1
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#define PDC_INTRIGUE_START_CPU_COUNTERS 2
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#define PDC_INTRIGUE_STOP_CPU_COUNTERS 3
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#define PDC_STI 146 /* STI access */
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/* same as PDC_PCI_XXX values (see below) */
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/* Legacy PDC definitions for same stuff */
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#define PDC_PCI_INDEX 147
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#define PDC_PCI_INTERFACE_INFO 0
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#define PDC_PCI_SLOT_INFO 1
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#define PDC_PCI_INFLIGHT_BYTES 2
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#define PDC_PCI_READ_CONFIG 3
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#define PDC_PCI_WRITE_CONFIG 4
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#define PDC_PCI_READ_PCI_IO 5
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#define PDC_PCI_WRITE_PCI_IO 6
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#define PDC_PCI_READ_CONFIG_DELAY 7
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#define PDC_PCI_UPDATE_CONFIG_DELAY 8
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#define PDC_PCI_PCI_PATH_TO_PCI_HPA 9
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#define PDC_PCI_PCI_HPA_TO_PCI_PATH 10
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#define PDC_PCI_PCI_PATH_TO_PCI_BUS 11
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#define PDC_PCI_PCI_RESERVED 12
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#define PDC_PCI_PCI_INT_ROUTE_SIZE 13
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#define PDC_PCI_GET_INT_TBL_SIZE PDC_PCI_PCI_INT_ROUTE_SIZE
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#define PDC_PCI_PCI_INT_ROUTE 14
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#define PDC_PCI_GET_INT_TBL PDC_PCI_PCI_INT_ROUTE
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#define PDC_PCI_READ_MON_TYPE 15
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#define PDC_PCI_WRITE_MON_TYPE 16
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/* Get SCSI Interface Card info: SDTR, SCSI ID, mode (SE vs LVD) */
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#define PDC_INITIATOR 163
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#define PDC_GET_INITIATOR 0
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#define PDC_SET_INITIATOR 1
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#define PDC_DELETE_INITIATOR 2
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#define PDC_RETURN_TABLE_SIZE 3
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#define PDC_RETURN_TABLE 4
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#define PDC_LINK 165 /* (sprockets) */
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#define PDC_LINK_PCI_ENTRY_POINTS 0 /* list (Arg1) = 0 */
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#define PDC_LINK_USB_ENTRY_POINTS 1 /* list (Arg1) = 1 */
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/* cl_class
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* page 3-33 of IO-Firmware ARS
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* IODC ENTRY_INIT(Search first) RET[1]
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*/
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#define CL_NULL 0 /* invalid */
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#define CL_RANDOM 1 /* random access (as disk) */
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#define CL_SEQU 2 /* sequential access (as tape) */
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#define CL_DUPLEX 7 /* full-duplex point-to-point (RS-232, Net) */
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#define CL_KEYBD 8 /* half-duplex console (HIL Keyboard) */
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#define CL_DISPL 9 /* half-duplex console (display) */
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#define CL_FC 10 /* FiberChannel access media */
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/* IODC ENTRY_INIT() */
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#define ENTRY_INIT_SRCH_FRST 2
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#define ENTRY_INIT_SRCH_NEXT 3
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#define ENTRY_INIT_MOD_DEV 4
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#define ENTRY_INIT_DEV 5
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#define ENTRY_INIT_MOD 6
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#define ENTRY_INIT_MSG 9
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/* IODC ENTRY_IO() */
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#define ENTRY_IO_BOOTIN 0
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#define ENTRY_IO_BOOTOUT 1
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#define ENTRY_IO_CIN 2
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#define ENTRY_IO_COUT 3
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#define ENTRY_IO_CLOSE 4
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#define ENTRY_IO_GETMSG 9
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#define ENTRY_IO_BBLOCK_IN 16
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#define ENTRY_IO_BBLOCK_OUT 17
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/* IODC ENTRY_SPA() */
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/* IODC ENTRY_CONFIG() */
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/* IODC ENTRY_TEST() */
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/* IODC ENTRY_TLB() */
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/* constants for OS (NVM...) */
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#define OS_ID_NONE 0 /* Undefined OS ID */
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#define OS_ID_HPUX 1 /* HP-UX OS */
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#define OS_ID_MPEXL 2 /* MPE XL OS */
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#define OS_ID_OSF 3 /* OSF OS */
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#define OS_ID_HPRT 4 /* HP-RT OS */
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#define OS_ID_NOVEL 5 /* NOVELL OS */
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#define OS_ID_LINUX 6 /* Linux */
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/* constants for PDC_CHASSIS */
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#define OSTAT_OFF 0
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#define OSTAT_FLT 1
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#define OSTAT_TEST 2
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#define OSTAT_INIT 3
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#define OSTAT_SHUT 4
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#define OSTAT_WARN 5
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#define OSTAT_RUN 6
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#define OSTAT_ON 7
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/* Page Zero constant offsets used by the HPMC handler */
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#define BOOT_CONSOLE_HPA_OFFSET 0x3c0
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#define BOOT_CONSOLE_SPA_OFFSET 0x3c4
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#define BOOT_CONSOLE_PATH_OFFSET 0x3a8
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/* size of the pdc_result buffer for firmware.c */
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#define NUM_PDC_RESULT 32
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#if !defined(__ASSEMBLY__)
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#include <linux/types.h>
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/* flags of the device_path */
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#define PF_AUTOBOOT 0x80
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#define PF_AUTOSEARCH 0x40
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#define PF_TIMER 0x0F
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struct device_path { /* page 1-69 */
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unsigned char flags; /* flags see above! */
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unsigned char bc[6]; /* bus converter routing info */
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unsigned char mod;
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unsigned int layers[6];/* device-specific layer-info */
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} __attribute__((aligned(8))) ;
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struct pz_device {
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struct device_path dp; /* see above */
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/* struct iomod *hpa; */
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unsigned int hpa; /* HPA base address */
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/* char *spa; */
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unsigned int spa; /* SPA base address */
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/* int (*iodc_io)(struct iomod*, ...); */
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unsigned int iodc_io; /* device entry point */
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short pad; /* reserved */
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unsigned short cl_class;/* see below */
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} __attribute__((aligned(8))) ;
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struct zeropage {
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/* [0x000] initialize vectors (VEC) */
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unsigned int vec_special; /* must be zero */
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/* int (*vec_pow_fail)(void);*/
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unsigned int vec_pow_fail; /* power failure handler */
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/* int (*vec_toc)(void); */
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unsigned int vec_toc;
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unsigned int vec_toclen;
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/* int (*vec_rendz)(void); */
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unsigned int vec_rendz;
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int vec_pow_fail_flen;
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int vec_pad[10];
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/* [0x040] reserved processor dependent */
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int pad0[112];
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/* [0x200] reserved */
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int pad1[84];
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/* [0x350] memory configuration (MC) */
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int memc_cont; /* contiguous mem size (bytes) */
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int memc_phsize; /* physical memory size */
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int memc_adsize; /* additional mem size, bytes of SPA space used by PDC */
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unsigned int mem_pdc_hi; /* used for 64-bit */
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/* [0x360] various parameters for the boot-CPU */
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/* unsigned int *mem_booterr[8]; */
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unsigned int mem_booterr[8]; /* ptr to boot errors */
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unsigned int mem_free; /* first location, where OS can be loaded */
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/* struct iomod *mem_hpa; */
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unsigned int mem_hpa; /* HPA of the boot-CPU */
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/* int (*mem_pdc)(int, ...); */
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unsigned int mem_pdc; /* PDC entry point */
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unsigned int mem_10msec; /* number of clock ticks in 10msec */
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/* [0x390] initial memory module (IMM) */
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/* struct iomod *imm_hpa; */
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unsigned int imm_hpa; /* HPA of the IMM */
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int imm_soft_boot; /* 0 = was hard boot, 1 = was soft boot */
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unsigned int imm_spa_size; /* SPA size of the IMM in bytes */
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unsigned int imm_max_mem; /* bytes of mem in IMM */
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/* [0x3A0] boot console, display device and keyboard */
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struct pz_device mem_cons; /* description of console device */
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struct pz_device mem_boot; /* description of boot device */
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struct pz_device mem_kbd; /* description of keyboard device */
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/* [0x430] reserved */
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int pad430[116];
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/* [0x600] processor dependent */
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__u32 pad600[1];
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__u32 proc_sti; /* pointer to STI ROM */
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__u32 pad608[126];
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};
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#endif /* !defined(__ASSEMBLY__) */
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#endif /* _UAPI_PARISC_PDC_H */
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