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![Sebastian Andrzej Siewior](/assets/img/avatar_default.png)
This adds support for Marvell's Cryptographic Engines and Security Accelerator (CESA) which can be found on a few SoC. Tested with dm-crypt. Acked-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
606 lines
14 KiB
C
606 lines
14 KiB
C
/*
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* Support for Marvell's crypto engine which can be found on some Orion5X
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* boards.
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*
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* Author: Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
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* License: GPLv2
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*
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*/
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#include <crypto/aes.h>
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#include <crypto/algapi.h>
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#include <linux/crypto.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kthread.h>
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#include <linux/platform_device.h>
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#include <linux/scatterlist.h>
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#include "mv_cesa.h"
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/*
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* STM:
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* /---------------------------------------\
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* | | request complete
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* \./ |
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* IDLE -> new request -> BUSY -> done -> DEQUEUE
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* /°\ |
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* | | more scatter entries
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* \________________/
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*/
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enum engine_status {
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ENGINE_IDLE,
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ENGINE_BUSY,
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ENGINE_W_DEQUEUE,
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};
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/**
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* struct req_progress - used for every crypt request
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* @src_sg_it: sg iterator for src
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* @dst_sg_it: sg iterator for dst
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* @sg_src_left: bytes left in src to process (scatter list)
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* @src_start: offset to add to src start position (scatter list)
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* @crypt_len: length of current crypt process
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* @sg_dst_left: bytes left dst to process in this scatter list
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* @dst_start: offset to add to dst start position (scatter list)
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* @total_req_bytes: total number of bytes processed (request).
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*
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* sg helper are used to iterate over the scatterlist. Since the size of the
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* SRAM may be less than the scatter size, this struct struct is used to keep
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* track of progress within current scatterlist.
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*/
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struct req_progress {
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struct sg_mapping_iter src_sg_it;
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struct sg_mapping_iter dst_sg_it;
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/* src mostly */
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int sg_src_left;
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int src_start;
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int crypt_len;
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/* dst mostly */
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int sg_dst_left;
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int dst_start;
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int total_req_bytes;
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};
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struct crypto_priv {
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void __iomem *reg;
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void __iomem *sram;
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int irq;
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struct task_struct *queue_th;
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/* the lock protects queue and eng_st */
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spinlock_t lock;
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struct crypto_queue queue;
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enum engine_status eng_st;
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struct ablkcipher_request *cur_req;
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struct req_progress p;
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int max_req_size;
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int sram_size;
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};
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static struct crypto_priv *cpg;
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struct mv_ctx {
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u8 aes_enc_key[AES_KEY_LEN];
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u32 aes_dec_key[8];
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int key_len;
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u32 need_calc_aes_dkey;
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};
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enum crypto_op {
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COP_AES_ECB,
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COP_AES_CBC,
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};
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struct mv_req_ctx {
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enum crypto_op op;
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int decrypt;
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};
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static void compute_aes_dec_key(struct mv_ctx *ctx)
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{
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struct crypto_aes_ctx gen_aes_key;
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int key_pos;
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if (!ctx->need_calc_aes_dkey)
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return;
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crypto_aes_expand_key(&gen_aes_key, ctx->aes_enc_key, ctx->key_len);
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key_pos = ctx->key_len + 24;
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memcpy(ctx->aes_dec_key, &gen_aes_key.key_enc[key_pos], 4 * 4);
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switch (ctx->key_len) {
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case AES_KEYSIZE_256:
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key_pos -= 2;
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/* fall */
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case AES_KEYSIZE_192:
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key_pos -= 2;
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memcpy(&ctx->aes_dec_key[4], &gen_aes_key.key_enc[key_pos],
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4 * 4);
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break;
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}
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ctx->need_calc_aes_dkey = 0;
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}
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static int mv_setkey_aes(struct crypto_ablkcipher *cipher, const u8 *key,
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unsigned int len)
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{
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struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
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struct mv_ctx *ctx = crypto_tfm_ctx(tfm);
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switch (len) {
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case AES_KEYSIZE_128:
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case AES_KEYSIZE_192:
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case AES_KEYSIZE_256:
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break;
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default:
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crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
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return -EINVAL;
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}
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ctx->key_len = len;
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ctx->need_calc_aes_dkey = 1;
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memcpy(ctx->aes_enc_key, key, AES_KEY_LEN);
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return 0;
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}
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static void setup_data_in(struct ablkcipher_request *req)
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{
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int ret;
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void *buf;
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if (!cpg->p.sg_src_left) {
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ret = sg_miter_next(&cpg->p.src_sg_it);
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BUG_ON(!ret);
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cpg->p.sg_src_left = cpg->p.src_sg_it.length;
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cpg->p.src_start = 0;
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}
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cpg->p.crypt_len = min(cpg->p.sg_src_left, cpg->max_req_size);
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buf = cpg->p.src_sg_it.addr;
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buf += cpg->p.src_start;
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memcpy(cpg->sram + SRAM_DATA_IN_START, buf, cpg->p.crypt_len);
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cpg->p.sg_src_left -= cpg->p.crypt_len;
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cpg->p.src_start += cpg->p.crypt_len;
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}
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static void mv_process_current_q(int first_block)
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{
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struct ablkcipher_request *req = cpg->cur_req;
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struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
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struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
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struct sec_accel_config op;
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switch (req_ctx->op) {
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case COP_AES_ECB:
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op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_ECB;
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break;
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case COP_AES_CBC:
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op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_CBC;
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op.enc_iv = ENC_IV_POINT(SRAM_DATA_IV) |
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ENC_IV_BUF_POINT(SRAM_DATA_IV_BUF);
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if (first_block)
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memcpy(cpg->sram + SRAM_DATA_IV, req->info, 16);
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break;
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}
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if (req_ctx->decrypt) {
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op.config |= CFG_DIR_DEC;
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memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_dec_key,
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AES_KEY_LEN);
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} else {
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op.config |= CFG_DIR_ENC;
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memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_enc_key,
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AES_KEY_LEN);
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}
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switch (ctx->key_len) {
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case AES_KEYSIZE_128:
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op.config |= CFG_AES_LEN_128;
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break;
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case AES_KEYSIZE_192:
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op.config |= CFG_AES_LEN_192;
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break;
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case AES_KEYSIZE_256:
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op.config |= CFG_AES_LEN_256;
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break;
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}
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op.enc_p = ENC_P_SRC(SRAM_DATA_IN_START) |
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ENC_P_DST(SRAM_DATA_OUT_START);
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op.enc_key_p = SRAM_DATA_KEY_P;
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setup_data_in(req);
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op.enc_len = cpg->p.crypt_len;
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memcpy(cpg->sram + SRAM_CONFIG, &op,
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sizeof(struct sec_accel_config));
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writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
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/* GO */
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writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
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/*
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* XXX: add timer if the interrupt does not occur for some mystery
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* reason
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*/
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}
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static void mv_crypto_algo_completion(void)
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{
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struct ablkcipher_request *req = cpg->cur_req;
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struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
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if (req_ctx->op != COP_AES_CBC)
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return ;
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memcpy(req->info, cpg->sram + SRAM_DATA_IV_BUF, 16);
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}
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static void dequeue_complete_req(void)
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{
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struct ablkcipher_request *req = cpg->cur_req;
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void *buf;
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int ret;
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cpg->p.total_req_bytes += cpg->p.crypt_len;
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do {
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int dst_copy;
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if (!cpg->p.sg_dst_left) {
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ret = sg_miter_next(&cpg->p.dst_sg_it);
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BUG_ON(!ret);
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cpg->p.sg_dst_left = cpg->p.dst_sg_it.length;
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cpg->p.dst_start = 0;
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}
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buf = cpg->p.dst_sg_it.addr;
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buf += cpg->p.dst_start;
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dst_copy = min(cpg->p.crypt_len, cpg->p.sg_dst_left);
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memcpy(buf, cpg->sram + SRAM_DATA_OUT_START, dst_copy);
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cpg->p.sg_dst_left -= dst_copy;
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cpg->p.crypt_len -= dst_copy;
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cpg->p.dst_start += dst_copy;
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} while (cpg->p.crypt_len > 0);
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BUG_ON(cpg->eng_st != ENGINE_W_DEQUEUE);
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if (cpg->p.total_req_bytes < req->nbytes) {
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/* process next scatter list entry */
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cpg->eng_st = ENGINE_BUSY;
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mv_process_current_q(0);
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} else {
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sg_miter_stop(&cpg->p.src_sg_it);
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sg_miter_stop(&cpg->p.dst_sg_it);
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mv_crypto_algo_completion();
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cpg->eng_st = ENGINE_IDLE;
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req->base.complete(&req->base, 0);
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}
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}
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static int count_sgs(struct scatterlist *sl, unsigned int total_bytes)
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{
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int i = 0;
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do {
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total_bytes -= sl[i].length;
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i++;
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} while (total_bytes > 0);
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return i;
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}
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static void mv_enqueue_new_req(struct ablkcipher_request *req)
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{
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int num_sgs;
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cpg->cur_req = req;
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memset(&cpg->p, 0, sizeof(struct req_progress));
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num_sgs = count_sgs(req->src, req->nbytes);
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sg_miter_start(&cpg->p.src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
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num_sgs = count_sgs(req->dst, req->nbytes);
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sg_miter_start(&cpg->p.dst_sg_it, req->dst, num_sgs, SG_MITER_TO_SG);
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mv_process_current_q(1);
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}
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static int queue_manag(void *data)
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{
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cpg->eng_st = ENGINE_IDLE;
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do {
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struct ablkcipher_request *req;
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struct crypto_async_request *async_req = NULL;
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struct crypto_async_request *backlog;
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__set_current_state(TASK_INTERRUPTIBLE);
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if (cpg->eng_st == ENGINE_W_DEQUEUE)
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dequeue_complete_req();
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spin_lock_irq(&cpg->lock);
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if (cpg->eng_st == ENGINE_IDLE) {
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backlog = crypto_get_backlog(&cpg->queue);
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async_req = crypto_dequeue_request(&cpg->queue);
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if (async_req) {
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BUG_ON(cpg->eng_st != ENGINE_IDLE);
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cpg->eng_st = ENGINE_BUSY;
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}
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}
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spin_unlock_irq(&cpg->lock);
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if (backlog) {
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backlog->complete(backlog, -EINPROGRESS);
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backlog = NULL;
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}
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if (async_req) {
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req = container_of(async_req,
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struct ablkcipher_request, base);
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mv_enqueue_new_req(req);
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async_req = NULL;
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}
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schedule();
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} while (!kthread_should_stop());
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return 0;
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}
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static int mv_handle_req(struct ablkcipher_request *req)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&cpg->lock, flags);
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ret = ablkcipher_enqueue_request(&cpg->queue, req);
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spin_unlock_irqrestore(&cpg->lock, flags);
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wake_up_process(cpg->queue_th);
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return ret;
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}
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static int mv_enc_aes_ecb(struct ablkcipher_request *req)
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{
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struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
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req_ctx->op = COP_AES_ECB;
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req_ctx->decrypt = 0;
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return mv_handle_req(req);
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}
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static int mv_dec_aes_ecb(struct ablkcipher_request *req)
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{
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struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
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struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
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req_ctx->op = COP_AES_ECB;
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req_ctx->decrypt = 1;
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compute_aes_dec_key(ctx);
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return mv_handle_req(req);
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}
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static int mv_enc_aes_cbc(struct ablkcipher_request *req)
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{
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struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
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req_ctx->op = COP_AES_CBC;
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req_ctx->decrypt = 0;
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return mv_handle_req(req);
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}
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static int mv_dec_aes_cbc(struct ablkcipher_request *req)
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{
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struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
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struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
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req_ctx->op = COP_AES_CBC;
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req_ctx->decrypt = 1;
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compute_aes_dec_key(ctx);
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return mv_handle_req(req);
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}
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static int mv_cra_init(struct crypto_tfm *tfm)
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{
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tfm->crt_ablkcipher.reqsize = sizeof(struct mv_req_ctx);
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return 0;
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}
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irqreturn_t crypto_int(int irq, void *priv)
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{
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u32 val;
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val = readl(cpg->reg + SEC_ACCEL_INT_STATUS);
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if (!(val & SEC_INT_ACCEL0_DONE))
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return IRQ_NONE;
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val &= ~SEC_INT_ACCEL0_DONE;
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writel(val, cpg->reg + FPGA_INT_STATUS);
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writel(val, cpg->reg + SEC_ACCEL_INT_STATUS);
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BUG_ON(cpg->eng_st != ENGINE_BUSY);
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cpg->eng_st = ENGINE_W_DEQUEUE;
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wake_up_process(cpg->queue_th);
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return IRQ_HANDLED;
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}
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struct crypto_alg mv_aes_alg_ecb = {
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.cra_name = "ecb(aes)",
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.cra_driver_name = "mv-ecb-aes",
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.cra_priority = 300,
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.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
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.cra_blocksize = 16,
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.cra_ctxsize = sizeof(struct mv_ctx),
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.cra_alignmask = 0,
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.cra_type = &crypto_ablkcipher_type,
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.cra_module = THIS_MODULE,
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.cra_init = mv_cra_init,
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.cra_u = {
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.ablkcipher = {
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.min_keysize = AES_MIN_KEY_SIZE,
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.max_keysize = AES_MAX_KEY_SIZE,
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.setkey = mv_setkey_aes,
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.encrypt = mv_enc_aes_ecb,
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.decrypt = mv_dec_aes_ecb,
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},
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},
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};
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struct crypto_alg mv_aes_alg_cbc = {
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.cra_name = "cbc(aes)",
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.cra_driver_name = "mv-cbc-aes",
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.cra_priority = 300,
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.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_ctxsize = sizeof(struct mv_ctx),
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.cra_alignmask = 0,
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.cra_type = &crypto_ablkcipher_type,
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.cra_module = THIS_MODULE,
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.cra_init = mv_cra_init,
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.cra_u = {
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.ablkcipher = {
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.ivsize = AES_BLOCK_SIZE,
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.min_keysize = AES_MIN_KEY_SIZE,
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.max_keysize = AES_MAX_KEY_SIZE,
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.setkey = mv_setkey_aes,
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.encrypt = mv_enc_aes_cbc,
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.decrypt = mv_dec_aes_cbc,
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},
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},
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};
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static int mv_probe(struct platform_device *pdev)
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{
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struct crypto_priv *cp;
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struct resource *res;
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int irq;
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int ret;
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if (cpg) {
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printk(KERN_ERR "Second crypto dev?\n");
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return -EEXIST;
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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if (!res)
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return -ENXIO;
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cp = kzalloc(sizeof(*cp), GFP_KERNEL);
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if (!cp)
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return -ENOMEM;
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spin_lock_init(&cp->lock);
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|
crypto_init_queue(&cp->queue, 50);
|
|
cp->reg = ioremap(res->start, res->end - res->start + 1);
|
|
if (!cp->reg) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
|
|
if (!res) {
|
|
ret = -ENXIO;
|
|
goto err_unmap_reg;
|
|
}
|
|
cp->sram_size = res->end - res->start + 1;
|
|
cp->max_req_size = cp->sram_size - SRAM_CFG_SPACE;
|
|
cp->sram = ioremap(res->start, cp->sram_size);
|
|
if (!cp->sram) {
|
|
ret = -ENOMEM;
|
|
goto err_unmap_reg;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0 || irq == NO_IRQ) {
|
|
ret = irq;
|
|
goto err_unmap_sram;
|
|
}
|
|
cp->irq = irq;
|
|
|
|
platform_set_drvdata(pdev, cp);
|
|
cpg = cp;
|
|
|
|
cp->queue_th = kthread_run(queue_manag, cp, "mv_crypto");
|
|
if (IS_ERR(cp->queue_th)) {
|
|
ret = PTR_ERR(cp->queue_th);
|
|
goto err_thread;
|
|
}
|
|
|
|
ret = request_irq(irq, crypto_int, IRQF_DISABLED, dev_name(&pdev->dev),
|
|
cp);
|
|
if (ret)
|
|
goto err_unmap_sram;
|
|
|
|
writel(SEC_INT_ACCEL0_DONE, cpg->reg + SEC_ACCEL_INT_MASK);
|
|
writel(SEC_CFG_STOP_DIG_ERR, cpg->reg + SEC_ACCEL_CFG);
|
|
|
|
ret = crypto_register_alg(&mv_aes_alg_ecb);
|
|
if (ret)
|
|
goto err_reg;
|
|
|
|
ret = crypto_register_alg(&mv_aes_alg_cbc);
|
|
if (ret)
|
|
goto err_unreg_ecb;
|
|
return 0;
|
|
err_unreg_ecb:
|
|
crypto_unregister_alg(&mv_aes_alg_ecb);
|
|
err_thread:
|
|
free_irq(irq, cp);
|
|
err_reg:
|
|
kthread_stop(cp->queue_th);
|
|
err_unmap_sram:
|
|
iounmap(cp->sram);
|
|
err_unmap_reg:
|
|
iounmap(cp->reg);
|
|
err:
|
|
kfree(cp);
|
|
cpg = NULL;
|
|
platform_set_drvdata(pdev, NULL);
|
|
return ret;
|
|
}
|
|
|
|
static int mv_remove(struct platform_device *pdev)
|
|
{
|
|
struct crypto_priv *cp = platform_get_drvdata(pdev);
|
|
|
|
crypto_unregister_alg(&mv_aes_alg_ecb);
|
|
crypto_unregister_alg(&mv_aes_alg_cbc);
|
|
kthread_stop(cp->queue_th);
|
|
free_irq(cp->irq, cp);
|
|
memset(cp->sram, 0, cp->sram_size);
|
|
iounmap(cp->sram);
|
|
iounmap(cp->reg);
|
|
kfree(cp);
|
|
cpg = NULL;
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver marvell_crypto = {
|
|
.probe = mv_probe,
|
|
.remove = mv_remove,
|
|
.driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = "mv_crypto",
|
|
},
|
|
};
|
|
MODULE_ALIAS("platform:mv_crypto");
|
|
|
|
static int __init mv_crypto_init(void)
|
|
{
|
|
return platform_driver_register(&marvell_crypto);
|
|
}
|
|
module_init(mv_crypto_init);
|
|
|
|
static void __exit mv_crypto_exit(void)
|
|
{
|
|
platform_driver_unregister(&marvell_crypto);
|
|
}
|
|
module_exit(mv_crypto_exit);
|
|
|
|
MODULE_AUTHOR("Sebastian Andrzej Siewior <sebastian@breakpoint.cc>");
|
|
MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");
|
|
MODULE_LICENSE("GPL");
|