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876 lines
21 KiB
C
876 lines
21 KiB
C
/*
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* Renesas SuperH DMA Engine support
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*
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* base is drivers/dma/flsdma.c
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*
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* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
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* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* - DMA of SuperH does not have Hardware DMA chain mode.
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* - MAX DMA size is 16MB.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <cpu/dma.h>
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#include <asm/dma-sh.h>
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#include "shdma.h"
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/* DMA descriptor control */
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enum sh_dmae_desc_status {
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DESC_IDLE,
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DESC_PREPARED,
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DESC_SUBMITTED,
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DESC_COMPLETED, /* completed, have to call callback */
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DESC_WAITING, /* callback called, waiting for ack / re-submit */
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};
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#define NR_DESCS_PER_CHANNEL 32
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/*
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* Define the default configuration for dual address memory-memory transfer.
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* The 0x400 value represents auto-request, external->external.
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*
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* And this driver set 4byte burst mode.
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* If you want to change mode, you need to change RS_DEFAULT of value.
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* (ex 1byte burst mode -> (RS_DUAL & ~TS_32)
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*/
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#define RS_DEFAULT (RS_DUAL)
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static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
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#define SH_DMAC_CHAN_BASE(id) (dma_base_addr[id])
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static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
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{
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ctrl_outl(data, (SH_DMAC_CHAN_BASE(sh_dc->id) + reg));
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}
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static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
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{
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return ctrl_inl((SH_DMAC_CHAN_BASE(sh_dc->id) + reg));
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}
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static void dmae_init(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = RS_DEFAULT; /* default is DUAL mode */
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sh_dmae_writel(sh_chan, chcr, CHCR);
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}
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/*
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* Reset DMA controller
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*
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* SH7780 has two DMAOR register
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*/
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static void sh_dmae_ctl_stop(int id)
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{
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unsigned short dmaor = dmaor_read_reg(id);
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dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
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dmaor_write_reg(id, dmaor);
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}
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static int sh_dmae_rst(int id)
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{
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unsigned short dmaor;
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sh_dmae_ctl_stop(id);
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dmaor = dmaor_read_reg(id) | DMAOR_INIT;
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dmaor_write_reg(id, dmaor);
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if (dmaor_read_reg(id) & (DMAOR_AE | DMAOR_NMIF)) {
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pr_warning(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
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return -EINVAL;
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}
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return 0;
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}
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static int dmae_is_busy(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = sh_dmae_readl(sh_chan, CHCR);
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if (chcr & CHCR_DE) {
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if (!(chcr & CHCR_TE))
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return -EBUSY; /* working */
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}
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return 0; /* waiting */
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}
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static inline unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = sh_dmae_readl(sh_chan, CHCR);
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return ts_shift[(chcr & CHCR_TS_MASK) >> CHCR_TS_SHIFT];
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}
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static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
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{
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sh_dmae_writel(sh_chan, hw->sar, SAR);
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sh_dmae_writel(sh_chan, hw->dar, DAR);
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sh_dmae_writel(sh_chan, hw->tcr >> calc_xmit_shift(sh_chan), TCR);
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}
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static void dmae_start(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = sh_dmae_readl(sh_chan, CHCR);
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chcr |= CHCR_DE | CHCR_IE;
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sh_dmae_writel(sh_chan, chcr, CHCR);
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}
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static void dmae_halt(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = sh_dmae_readl(sh_chan, CHCR);
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chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
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sh_dmae_writel(sh_chan, chcr, CHCR);
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}
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static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
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{
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int ret = dmae_is_busy(sh_chan);
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/* When DMA was working, can not set data to CHCR */
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if (ret)
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return ret;
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sh_dmae_writel(sh_chan, val, CHCR);
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return 0;
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}
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#define DMARS1_ADDR 0x04
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#define DMARS2_ADDR 0x08
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#define DMARS_SHIFT 8
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#define DMARS_CHAN_MSK 0x01
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static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
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{
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u32 addr;
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int shift = 0;
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int ret = dmae_is_busy(sh_chan);
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if (ret)
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return ret;
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if (sh_chan->id & DMARS_CHAN_MSK)
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shift = DMARS_SHIFT;
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switch (sh_chan->id) {
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/* DMARS0 */
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case 0:
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case 1:
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addr = SH_DMARS_BASE;
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break;
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/* DMARS1 */
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case 2:
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case 3:
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addr = (SH_DMARS_BASE + DMARS1_ADDR);
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break;
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/* DMARS2 */
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case 4:
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case 5:
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addr = (SH_DMARS_BASE + DMARS2_ADDR);
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break;
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default:
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return -EINVAL;
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}
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ctrl_outw((val << shift) |
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(ctrl_inw(addr) & (shift ? 0xFF00 : 0x00FF)),
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addr);
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return 0;
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}
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static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c;
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struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan);
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dma_async_tx_callback callback = tx->callback;
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dma_cookie_t cookie;
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spin_lock_bh(&sh_chan->desc_lock);
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cookie = sh_chan->common.cookie;
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cookie++;
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if (cookie < 0)
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cookie = 1;
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sh_chan->common.cookie = cookie;
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tx->cookie = cookie;
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/* Mark all chunks of this descriptor as submitted, move to the queue */
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list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
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/*
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* All chunks are on the global ld_free, so, we have to find
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* the end of the chain ourselves
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*/
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if (chunk != desc && (chunk->mark == DESC_IDLE ||
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chunk->async_tx.cookie > 0 ||
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chunk->async_tx.cookie == -EBUSY ||
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&chunk->node == &sh_chan->ld_free))
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break;
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chunk->mark = DESC_SUBMITTED;
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/* Callback goes to the last chunk */
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chunk->async_tx.callback = NULL;
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chunk->cookie = cookie;
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list_move_tail(&chunk->node, &sh_chan->ld_queue);
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last = chunk;
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}
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last->async_tx.callback = callback;
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last->async_tx.callback_param = tx->callback_param;
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dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n",
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tx->cookie, &last->async_tx, sh_chan->id,
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desc->hw.sar, desc->hw.tcr, desc->hw.dar);
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spin_unlock_bh(&sh_chan->desc_lock);
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return cookie;
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}
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/* Called with desc_lock held */
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static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan)
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{
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struct sh_desc *desc;
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list_for_each_entry(desc, &sh_chan->ld_free, node)
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if (desc->mark != DESC_PREPARED) {
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BUG_ON(desc->mark != DESC_IDLE);
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list_del(&desc->node);
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return desc;
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}
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return NULL;
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}
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static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
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{
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struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
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struct sh_desc *desc;
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spin_lock_bh(&sh_chan->desc_lock);
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while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) {
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spin_unlock_bh(&sh_chan->desc_lock);
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desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL);
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if (!desc) {
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spin_lock_bh(&sh_chan->desc_lock);
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break;
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}
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dma_async_tx_descriptor_init(&desc->async_tx,
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&sh_chan->common);
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desc->async_tx.tx_submit = sh_dmae_tx_submit;
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desc->mark = DESC_IDLE;
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spin_lock_bh(&sh_chan->desc_lock);
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list_add(&desc->node, &sh_chan->ld_free);
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sh_chan->descs_allocated++;
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}
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spin_unlock_bh(&sh_chan->desc_lock);
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return sh_chan->descs_allocated;
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}
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/*
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* sh_dma_free_chan_resources - Free all resources of the channel.
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*/
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static void sh_dmae_free_chan_resources(struct dma_chan *chan)
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{
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struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
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struct sh_desc *desc, *_desc;
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LIST_HEAD(list);
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/* Prepared and not submitted descriptors can still be on the queue */
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if (!list_empty(&sh_chan->ld_queue))
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sh_dmae_chan_ld_cleanup(sh_chan, true);
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spin_lock_bh(&sh_chan->desc_lock);
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list_splice_init(&sh_chan->ld_free, &list);
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sh_chan->descs_allocated = 0;
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spin_unlock_bh(&sh_chan->desc_lock);
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list_for_each_entry_safe(desc, _desc, &list, node)
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kfree(desc);
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}
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static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
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struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
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size_t len, unsigned long flags)
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{
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struct sh_dmae_chan *sh_chan;
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struct sh_desc *first = NULL, *prev = NULL, *new;
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size_t copy_size;
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LIST_HEAD(tx_list);
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int chunks = (len + SH_DMA_TCR_MAX) / (SH_DMA_TCR_MAX + 1);
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if (!chan)
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return NULL;
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if (!len)
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return NULL;
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sh_chan = to_sh_chan(chan);
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/* Have to lock the whole loop to protect against concurrent release */
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spin_lock_bh(&sh_chan->desc_lock);
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/*
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* Chaining:
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* first descriptor is what user is dealing with in all API calls, its
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* cookie is at first set to -EBUSY, at tx-submit to a positive
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* number
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* if more than one chunk is needed further chunks have cookie = -EINVAL
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* the last chunk, if not equal to the first, has cookie = -ENOSPC
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* all chunks are linked onto the tx_list head with their .node heads
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* only during this function, then they are immediately spliced
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* back onto the free list in form of a chain
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*/
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do {
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/* Allocate the link descriptor from the free list */
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new = sh_dmae_get_desc(sh_chan);
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if (!new) {
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dev_err(sh_chan->dev,
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"No free memory for link descriptor\n");
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list_for_each_entry(new, &tx_list, node)
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new->mark = DESC_IDLE;
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list_splice(&tx_list, &sh_chan->ld_free);
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spin_unlock_bh(&sh_chan->desc_lock);
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return NULL;
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}
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copy_size = min(len, (size_t)SH_DMA_TCR_MAX + 1);
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new->hw.sar = dma_src;
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new->hw.dar = dma_dest;
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new->hw.tcr = copy_size;
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if (!first) {
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/* First desc */
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new->async_tx.cookie = -EBUSY;
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first = new;
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} else {
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/* Other desc - invisible to the user */
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new->async_tx.cookie = -EINVAL;
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}
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dev_dbg(sh_chan->dev,
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"chaining %u of %u with %p, dst %x, cookie %d\n",
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copy_size, len, &new->async_tx, dma_dest,
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new->async_tx.cookie);
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new->mark = DESC_PREPARED;
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new->async_tx.flags = flags;
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new->chunks = chunks--;
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prev = new;
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len -= copy_size;
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dma_src += copy_size;
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dma_dest += copy_size;
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/* Insert the link descriptor to the LD ring */
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list_add_tail(&new->node, &tx_list);
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} while (len);
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if (new != first)
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new->async_tx.cookie = -ENOSPC;
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/* Put them back on the free list, so, they don't get lost */
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list_splice_tail(&tx_list, &sh_chan->ld_free);
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spin_unlock_bh(&sh_chan->desc_lock);
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return &first->async_tx;
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}
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static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
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{
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struct sh_desc *desc, *_desc;
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/* Is the "exposed" head of a chain acked? */
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bool head_acked = false;
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dma_cookie_t cookie = 0;
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dma_async_tx_callback callback = NULL;
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void *param = NULL;
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spin_lock_bh(&sh_chan->desc_lock);
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list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) {
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struct dma_async_tx_descriptor *tx = &desc->async_tx;
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BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
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BUG_ON(desc->mark != DESC_SUBMITTED &&
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desc->mark != DESC_COMPLETED &&
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desc->mark != DESC_WAITING);
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/*
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* queue is ordered, and we use this loop to (1) clean up all
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* completed descriptors, and to (2) update descriptor flags of
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* any chunks in a (partially) completed chain
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*/
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if (!all && desc->mark == DESC_SUBMITTED &&
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desc->cookie != cookie)
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break;
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if (tx->cookie > 0)
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cookie = tx->cookie;
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if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
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BUG_ON(sh_chan->completed_cookie != desc->cookie - 1);
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sh_chan->completed_cookie = desc->cookie;
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}
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/* Call callback on the last chunk */
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if (desc->mark == DESC_COMPLETED && tx->callback) {
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desc->mark = DESC_WAITING;
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callback = tx->callback;
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param = tx->callback_param;
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dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n",
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tx->cookie, tx, sh_chan->id);
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BUG_ON(desc->chunks != 1);
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break;
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}
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if (tx->cookie > 0 || tx->cookie == -EBUSY) {
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if (desc->mark == DESC_COMPLETED) {
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BUG_ON(tx->cookie < 0);
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desc->mark = DESC_WAITING;
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}
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head_acked = async_tx_test_ack(tx);
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} else {
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switch (desc->mark) {
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case DESC_COMPLETED:
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desc->mark = DESC_WAITING;
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/* Fall through */
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case DESC_WAITING:
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if (head_acked)
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async_tx_ack(&desc->async_tx);
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}
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}
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dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n",
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tx, tx->cookie);
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if (((desc->mark == DESC_COMPLETED ||
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desc->mark == DESC_WAITING) &&
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async_tx_test_ack(&desc->async_tx)) || all) {
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/* Remove from ld_queue list */
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desc->mark = DESC_IDLE;
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list_move(&desc->node, &sh_chan->ld_free);
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}
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}
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spin_unlock_bh(&sh_chan->desc_lock);
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if (callback)
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callback(param);
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return callback;
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}
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/*
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* sh_chan_ld_cleanup - Clean up link descriptors
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*
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* This function cleans up the ld_queue of DMA channel.
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*/
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static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
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{
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while (__ld_cleanup(sh_chan, all))
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;
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}
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static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
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{
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struct sh_desc *sd;
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spin_lock_bh(&sh_chan->desc_lock);
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/* DMA work check */
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if (dmae_is_busy(sh_chan)) {
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spin_unlock_bh(&sh_chan->desc_lock);
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return;
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}
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/* Find the first un-transfer desciptor */
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list_for_each_entry(sd, &sh_chan->ld_queue, node)
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if (sd->mark == DESC_SUBMITTED) {
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/* Get the ld start address from ld_queue */
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dmae_set_reg(sh_chan, &sd->hw);
|
|
dmae_start(sh_chan);
|
|
break;
|
|
}
|
|
|
|
spin_unlock_bh(&sh_chan->desc_lock);
|
|
}
|
|
|
|
static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan)
|
|
{
|
|
struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
|
|
sh_chan_xfer_ld_queue(sh_chan);
|
|
}
|
|
|
|
static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
|
|
dma_cookie_t cookie,
|
|
dma_cookie_t *done,
|
|
dma_cookie_t *used)
|
|
{
|
|
struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
|
|
dma_cookie_t last_used;
|
|
dma_cookie_t last_complete;
|
|
|
|
sh_dmae_chan_ld_cleanup(sh_chan, false);
|
|
|
|
last_used = chan->cookie;
|
|
last_complete = sh_chan->completed_cookie;
|
|
BUG_ON(last_complete < 0);
|
|
|
|
if (done)
|
|
*done = last_complete;
|
|
|
|
if (used)
|
|
*used = last_used;
|
|
|
|
return dma_async_is_complete(cookie, last_complete, last_used);
|
|
}
|
|
|
|
static irqreturn_t sh_dmae_interrupt(int irq, void *data)
|
|
{
|
|
irqreturn_t ret = IRQ_NONE;
|
|
struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
|
|
u32 chcr = sh_dmae_readl(sh_chan, CHCR);
|
|
|
|
if (chcr & CHCR_TE) {
|
|
/* DMA stop */
|
|
dmae_halt(sh_chan);
|
|
|
|
ret = IRQ_HANDLED;
|
|
tasklet_schedule(&sh_chan->tasklet);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
#if defined(CONFIG_CPU_SH4)
|
|
static irqreturn_t sh_dmae_err(int irq, void *data)
|
|
{
|
|
int err = 0;
|
|
struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
|
|
|
|
/* IRQ Multi */
|
|
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
|
int cnt = 0;
|
|
switch (irq) {
|
|
#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
|
|
case DMTE6_IRQ:
|
|
cnt++;
|
|
#endif
|
|
case DMTE0_IRQ:
|
|
if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) {
|
|
disable_irq(irq);
|
|
return IRQ_HANDLED;
|
|
}
|
|
default:
|
|
return IRQ_NONE;
|
|
}
|
|
} else {
|
|
/* reset dma controller */
|
|
err = sh_dmae_rst(0);
|
|
if (err)
|
|
return err;
|
|
#ifdef SH_DMAC_BASE1
|
|
if (shdev->pdata.mode & SHDMA_DMAOR1) {
|
|
err = sh_dmae_rst(1);
|
|
if (err)
|
|
return err;
|
|
}
|
|
#endif
|
|
disable_irq(irq);
|
|
return IRQ_HANDLED;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static void dmae_do_tasklet(unsigned long data)
|
|
{
|
|
struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
|
|
struct sh_desc *desc;
|
|
u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
|
|
|
|
spin_lock(&sh_chan->desc_lock);
|
|
list_for_each_entry(desc, &sh_chan->ld_queue, node) {
|
|
if ((desc->hw.sar + desc->hw.tcr) == sar_buf &&
|
|
desc->mark == DESC_SUBMITTED) {
|
|
dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
|
|
desc->async_tx.cookie, &desc->async_tx,
|
|
desc->hw.dar);
|
|
desc->mark = DESC_COMPLETED;
|
|
break;
|
|
}
|
|
}
|
|
spin_unlock(&sh_chan->desc_lock);
|
|
|
|
/* Next desc */
|
|
sh_chan_xfer_ld_queue(sh_chan);
|
|
sh_dmae_chan_ld_cleanup(sh_chan, false);
|
|
}
|
|
|
|
static unsigned int get_dmae_irq(unsigned int id)
|
|
{
|
|
unsigned int irq = 0;
|
|
if (id < ARRAY_SIZE(dmte_irq_map))
|
|
irq = dmte_irq_map[id];
|
|
return irq;
|
|
}
|
|
|
|
static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id)
|
|
{
|
|
int err;
|
|
unsigned int irq = get_dmae_irq(id);
|
|
unsigned long irqflags = IRQF_DISABLED;
|
|
struct sh_dmae_chan *new_sh_chan;
|
|
|
|
/* alloc channel */
|
|
new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL);
|
|
if (!new_sh_chan) {
|
|
dev_err(shdev->common.dev,
|
|
"No free memory for allocating dma channels!\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
new_sh_chan->dev = shdev->common.dev;
|
|
new_sh_chan->id = id;
|
|
|
|
/* Init DMA tasklet */
|
|
tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
|
|
(unsigned long)new_sh_chan);
|
|
|
|
/* Init the channel */
|
|
dmae_init(new_sh_chan);
|
|
|
|
spin_lock_init(&new_sh_chan->desc_lock);
|
|
|
|
/* Init descripter manage list */
|
|
INIT_LIST_HEAD(&new_sh_chan->ld_queue);
|
|
INIT_LIST_HEAD(&new_sh_chan->ld_free);
|
|
|
|
/* copy struct dma_device */
|
|
new_sh_chan->common.device = &shdev->common;
|
|
|
|
/* Add the channel to DMA device channel list */
|
|
list_add_tail(&new_sh_chan->common.device_node,
|
|
&shdev->common.channels);
|
|
shdev->common.chancnt++;
|
|
|
|
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
|
irqflags = IRQF_SHARED;
|
|
#if defined(DMTE6_IRQ)
|
|
if (irq >= DMTE6_IRQ)
|
|
irq = DMTE6_IRQ;
|
|
else
|
|
#endif
|
|
irq = DMTE0_IRQ;
|
|
}
|
|
|
|
snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
|
|
"sh-dmae%d", new_sh_chan->id);
|
|
|
|
/* set up channel irq */
|
|
err = request_irq(irq, &sh_dmae_interrupt, irqflags,
|
|
new_sh_chan->dev_id, new_sh_chan);
|
|
if (err) {
|
|
dev_err(shdev->common.dev, "DMA channel %d request_irq error "
|
|
"with return %d\n", id, err);
|
|
goto err_no_irq;
|
|
}
|
|
|
|
/* CHCR register control function */
|
|
new_sh_chan->set_chcr = dmae_set_chcr;
|
|
/* DMARS register control function */
|
|
new_sh_chan->set_dmars = dmae_set_dmars;
|
|
|
|
shdev->chan[id] = new_sh_chan;
|
|
return 0;
|
|
|
|
err_no_irq:
|
|
/* remove from dmaengine device node */
|
|
list_del(&new_sh_chan->common.device_node);
|
|
kfree(new_sh_chan);
|
|
return err;
|
|
}
|
|
|
|
static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
|
|
{
|
|
int i;
|
|
|
|
for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
|
|
if (shdev->chan[i]) {
|
|
struct sh_dmae_chan *shchan = shdev->chan[i];
|
|
if (!(shdev->pdata.mode & SHDMA_MIX_IRQ))
|
|
free_irq(dmte_irq_map[i], shchan);
|
|
|
|
list_del(&shchan->common.device_node);
|
|
kfree(shchan);
|
|
shdev->chan[i] = NULL;
|
|
}
|
|
}
|
|
shdev->common.chancnt = 0;
|
|
}
|
|
|
|
static int __init sh_dmae_probe(struct platform_device *pdev)
|
|
{
|
|
int err = 0, cnt, ecnt;
|
|
unsigned long irqflags = IRQF_DISABLED;
|
|
#if defined(CONFIG_CPU_SH4)
|
|
int eirq[] = { DMAE0_IRQ,
|
|
#if defined(DMAE1_IRQ)
|
|
DMAE1_IRQ
|
|
#endif
|
|
};
|
|
#endif
|
|
struct sh_dmae_device *shdev;
|
|
|
|
/* get platform data */
|
|
if (!pdev->dev.platform_data)
|
|
return -ENODEV;
|
|
|
|
shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
|
|
if (!shdev) {
|
|
dev_err(&pdev->dev, "No enough memory\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* platform data */
|
|
memcpy(&shdev->pdata, pdev->dev.platform_data,
|
|
sizeof(struct sh_dmae_pdata));
|
|
|
|
/* reset dma controller */
|
|
err = sh_dmae_rst(0);
|
|
if (err)
|
|
goto rst_err;
|
|
|
|
/* SH7780/85/23 has DMAOR1 */
|
|
if (shdev->pdata.mode & SHDMA_DMAOR1) {
|
|
err = sh_dmae_rst(1);
|
|
if (err)
|
|
goto rst_err;
|
|
}
|
|
|
|
INIT_LIST_HEAD(&shdev->common.channels);
|
|
|
|
dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
|
|
shdev->common.device_alloc_chan_resources
|
|
= sh_dmae_alloc_chan_resources;
|
|
shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources;
|
|
shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy;
|
|
shdev->common.device_is_tx_complete = sh_dmae_is_complete;
|
|
shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending;
|
|
shdev->common.dev = &pdev->dev;
|
|
/* Default transfer size of 32 bytes requires 32-byte alignment */
|
|
shdev->common.copy_align = 5;
|
|
|
|
#if defined(CONFIG_CPU_SH4)
|
|
/* Non Mix IRQ mode SH7722/SH7730 etc... */
|
|
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
|
irqflags = IRQF_SHARED;
|
|
eirq[0] = DMTE0_IRQ;
|
|
#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
|
|
eirq[1] = DMTE6_IRQ;
|
|
#endif
|
|
}
|
|
|
|
for (ecnt = 0 ; ecnt < ARRAY_SIZE(eirq); ecnt++) {
|
|
err = request_irq(eirq[ecnt], sh_dmae_err, irqflags,
|
|
"DMAC Address Error", shdev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "DMA device request_irq"
|
|
"error (irq %d) with return %d\n",
|
|
eirq[ecnt], err);
|
|
goto eirq_err;
|
|
}
|
|
}
|
|
#endif /* CONFIG_CPU_SH4 */
|
|
|
|
/* Create DMA Channel */
|
|
for (cnt = 0 ; cnt < MAX_DMA_CHANNELS ; cnt++) {
|
|
err = sh_dmae_chan_probe(shdev, cnt);
|
|
if (err)
|
|
goto chan_probe_err;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, shdev);
|
|
dma_async_device_register(&shdev->common);
|
|
|
|
return err;
|
|
|
|
chan_probe_err:
|
|
sh_dmae_chan_remove(shdev);
|
|
|
|
eirq_err:
|
|
for (ecnt-- ; ecnt >= 0; ecnt--)
|
|
free_irq(eirq[ecnt], shdev);
|
|
|
|
rst_err:
|
|
kfree(shdev);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int __exit sh_dmae_remove(struct platform_device *pdev)
|
|
{
|
|
struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
|
|
|
|
dma_async_device_unregister(&shdev->common);
|
|
|
|
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
|
free_irq(DMTE0_IRQ, shdev);
|
|
#if defined(DMTE6_IRQ)
|
|
free_irq(DMTE6_IRQ, shdev);
|
|
#endif
|
|
}
|
|
|
|
/* channel data remove */
|
|
sh_dmae_chan_remove(shdev);
|
|
|
|
if (!(shdev->pdata.mode & SHDMA_MIX_IRQ)) {
|
|
free_irq(DMAE0_IRQ, shdev);
|
|
#if defined(DMAE1_IRQ)
|
|
free_irq(DMAE1_IRQ, shdev);
|
|
#endif
|
|
}
|
|
kfree(shdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sh_dmae_shutdown(struct platform_device *pdev)
|
|
{
|
|
struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
|
|
sh_dmae_ctl_stop(0);
|
|
if (shdev->pdata.mode & SHDMA_DMAOR1)
|
|
sh_dmae_ctl_stop(1);
|
|
}
|
|
|
|
static struct platform_driver sh_dmae_driver = {
|
|
.remove = __exit_p(sh_dmae_remove),
|
|
.shutdown = sh_dmae_shutdown,
|
|
.driver = {
|
|
.name = "sh-dma-engine",
|
|
},
|
|
};
|
|
|
|
static int __init sh_dmae_init(void)
|
|
{
|
|
return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
|
|
}
|
|
module_init(sh_dmae_init);
|
|
|
|
static void __exit sh_dmae_exit(void)
|
|
{
|
|
platform_driver_unregister(&sh_dmae_driver);
|
|
}
|
|
module_exit(sh_dmae_exit);
|
|
|
|
MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
|
|
MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
|
|
MODULE_LICENSE("GPL");
|