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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-29 05:44:11 +00:00
85c823ac9a
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_i915_private struct pointer is readily
available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
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-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule2@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
command: spatch --sp-file <script> --dir drivers/gpu/drm/i915/gem \
--linux-spacing --in-place
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200115034455.17658-6-pankaj.laxminarayan.bharadiya@intel.com
111 lines
3.1 KiB
C
111 lines
3.1 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#include "gem/i915_gem_pm.h"
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#include "gt/intel_gt.h"
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#include "gt/intel_gt_pm.h"
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#include "gt/intel_gt_requests.h"
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#include "i915_drv.h"
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void i915_gem_suspend(struct drm_i915_private *i915)
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{
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GEM_TRACE("%s\n", dev_name(i915->drm.dev));
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intel_wakeref_auto(&i915->ggtt.userfault_wakeref, 0);
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flush_workqueue(i915->wq);
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/*
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* We have to flush all the executing contexts to main memory so
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* that they can saved in the hibernation image. To ensure the last
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* context image is coherent, we have to switch away from it. That
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* leaves the i915->kernel_context still active when
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* we actually suspend, and its image in memory may not match the GPU
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* state. Fortunately, the kernel_context is disposable and we do
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* not rely on its state.
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*/
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intel_gt_suspend_prepare(&i915->gt);
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i915_gem_drain_freed_objects(i915);
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}
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static struct drm_i915_gem_object *first_mm_object(struct list_head *list)
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{
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return list_first_entry_or_null(list,
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struct drm_i915_gem_object,
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mm.link);
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}
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void i915_gem_suspend_late(struct drm_i915_private *i915)
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{
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struct drm_i915_gem_object *obj;
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struct list_head *phases[] = {
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&i915->mm.shrink_list,
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&i915->mm.purge_list,
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NULL
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}, **phase;
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unsigned long flags;
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/*
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* Neither the BIOS, ourselves or any other kernel
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* expects the system to be in execlists mode on startup,
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* so we need to reset the GPU back to legacy mode. And the only
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* known way to disable logical contexts is through a GPU reset.
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*
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* So in order to leave the system in a known default configuration,
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* always reset the GPU upon unload and suspend. Afterwards we then
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* clean up the GEM state tracking, flushing off the requests and
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* leaving the system in a known idle state.
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*
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* Note that is of the upmost importance that the GPU is idle and
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* all stray writes are flushed *before* we dismantle the backing
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* storage for the pinned objects.
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*
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* However, since we are uncertain that resetting the GPU on older
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* machines is a good idea, we don't - just in case it leaves the
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* machine in an unusable condition.
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*/
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intel_gt_suspend_late(&i915->gt);
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spin_lock_irqsave(&i915->mm.obj_lock, flags);
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for (phase = phases; *phase; phase++) {
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LIST_HEAD(keep);
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while ((obj = first_mm_object(*phase))) {
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list_move_tail(&obj->mm.link, &keep);
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/* Beware the background _i915_gem_free_objects */
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if (!kref_get_unless_zero(&obj->base.refcount))
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continue;
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spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
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i915_gem_object_lock(obj);
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drm_WARN_ON(&i915->drm,
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i915_gem_object_set_to_gtt_domain(obj, false));
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i915_gem_object_unlock(obj);
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i915_gem_object_put(obj);
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spin_lock_irqsave(&i915->mm.obj_lock, flags);
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}
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list_splice_tail(&keep, *phase);
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}
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spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
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}
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void i915_gem_resume(struct drm_i915_private *i915)
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{
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GEM_TRACE("%s\n", dev_name(i915->drm.dev));
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/*
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* As we didn't flush the kernel context before suspend, we cannot
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* guarantee that the context image is complete. So let's just reset
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* it and start again.
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*/
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intel_gt_resume(&i915->gt);
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}
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