mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-29 23:53:32 +00:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
361 lines
11 KiB
C
361 lines
11 KiB
C
#ifndef __ALPHA_LCA__H__
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#define __ALPHA_LCA__H__
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#include <asm/system.h>
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#include <asm/compiler.h>
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/*
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* Low Cost Alpha (LCA) definitions (these apply to 21066 and 21068,
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* for example).
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*
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* This file is based on:
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*
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* DECchip 21066 and DECchip 21068 Alpha AXP Microprocessors
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* Hardware Reference Manual; Digital Equipment Corp.; May 1994;
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* Maynard, MA; Order Number: EC-N2681-71.
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*/
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/*
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* NOTE: The LCA uses a Host Address Extension (HAE) register to access
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* PCI addresses that are beyond the first 27 bits of address
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* space. Updating the HAE requires an external cycle (and
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* a memory barrier), which tends to be slow. Instead of updating
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* it on each sparse memory access, we keep the current HAE value
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* cached in variable cache_hae. Only if the cached HAE differs
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* from the desired HAE value do we actually updated HAE register.
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* The HAE register is preserved by the interrupt handler entry/exit
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* code, so this scheme works even in the presence of interrupts.
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*
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* Dense memory space doesn't require the HAE, but is restricted to
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* aligned 32 and 64 bit accesses. Special Cycle and Interrupt
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* Acknowledge cycles may also require the use of the HAE. The LCA
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* limits I/O address space to the bottom 24 bits of address space,
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* but this easily covers the 16 bit ISA I/O address space.
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*/
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/*
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* NOTE 2! The memory operations do not set any memory barriers, as
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* it's not needed for cases like a frame buffer that is essentially
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* memory-like. You need to do them by hand if the operations depend
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* on ordering.
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*
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* Similarly, the port I/O operations do a "mb" only after a write
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* operation: if an mb is needed before (as in the case of doing
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* memory mapped I/O first, and then a port I/O operation to the same
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* device), it needs to be done by hand.
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*
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* After the above has bitten me 100 times, I'll give up and just do
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* the mb all the time, but right now I'm hoping this will work out.
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* Avoiding mb's may potentially be a noticeable speed improvement,
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* but I can't honestly say I've tested it.
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*
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* Handling interrupts that need to do mb's to synchronize to
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* non-interrupts is another fun race area. Don't do it (because if
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* you do, I'll have to do *everything* with interrupts disabled,
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* ugh).
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*/
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/*
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* Memory Controller registers:
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*/
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#define LCA_MEM_BCR0 (IDENT_ADDR + 0x120000000UL)
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#define LCA_MEM_BCR1 (IDENT_ADDR + 0x120000008UL)
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#define LCA_MEM_BCR2 (IDENT_ADDR + 0x120000010UL)
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#define LCA_MEM_BCR3 (IDENT_ADDR + 0x120000018UL)
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#define LCA_MEM_BMR0 (IDENT_ADDR + 0x120000020UL)
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#define LCA_MEM_BMR1 (IDENT_ADDR + 0x120000028UL)
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#define LCA_MEM_BMR2 (IDENT_ADDR + 0x120000030UL)
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#define LCA_MEM_BMR3 (IDENT_ADDR + 0x120000038UL)
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#define LCA_MEM_BTR0 (IDENT_ADDR + 0x120000040UL)
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#define LCA_MEM_BTR1 (IDENT_ADDR + 0x120000048UL)
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#define LCA_MEM_BTR2 (IDENT_ADDR + 0x120000050UL)
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#define LCA_MEM_BTR3 (IDENT_ADDR + 0x120000058UL)
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#define LCA_MEM_GTR (IDENT_ADDR + 0x120000060UL)
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#define LCA_MEM_ESR (IDENT_ADDR + 0x120000068UL)
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#define LCA_MEM_EAR (IDENT_ADDR + 0x120000070UL)
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#define LCA_MEM_CAR (IDENT_ADDR + 0x120000078UL)
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#define LCA_MEM_VGR (IDENT_ADDR + 0x120000080UL)
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#define LCA_MEM_PLM (IDENT_ADDR + 0x120000088UL)
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#define LCA_MEM_FOR (IDENT_ADDR + 0x120000090UL)
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/*
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* I/O Controller registers:
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*/
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#define LCA_IOC_HAE (IDENT_ADDR + 0x180000000UL)
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#define LCA_IOC_CONF (IDENT_ADDR + 0x180000020UL)
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#define LCA_IOC_STAT0 (IDENT_ADDR + 0x180000040UL)
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#define LCA_IOC_STAT1 (IDENT_ADDR + 0x180000060UL)
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#define LCA_IOC_TBIA (IDENT_ADDR + 0x180000080UL)
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#define LCA_IOC_TB_ENA (IDENT_ADDR + 0x1800000a0UL)
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#define LCA_IOC_SFT_RST (IDENT_ADDR + 0x1800000c0UL)
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#define LCA_IOC_PAR_DIS (IDENT_ADDR + 0x1800000e0UL)
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#define LCA_IOC_W_BASE0 (IDENT_ADDR + 0x180000100UL)
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#define LCA_IOC_W_BASE1 (IDENT_ADDR + 0x180000120UL)
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#define LCA_IOC_W_MASK0 (IDENT_ADDR + 0x180000140UL)
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#define LCA_IOC_W_MASK1 (IDENT_ADDR + 0x180000160UL)
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#define LCA_IOC_T_BASE0 (IDENT_ADDR + 0x180000180UL)
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#define LCA_IOC_T_BASE1 (IDENT_ADDR + 0x1800001a0UL)
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#define LCA_IOC_TB_TAG0 (IDENT_ADDR + 0x188000000UL)
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#define LCA_IOC_TB_TAG1 (IDENT_ADDR + 0x188000020UL)
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#define LCA_IOC_TB_TAG2 (IDENT_ADDR + 0x188000040UL)
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#define LCA_IOC_TB_TAG3 (IDENT_ADDR + 0x188000060UL)
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#define LCA_IOC_TB_TAG4 (IDENT_ADDR + 0x188000070UL)
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#define LCA_IOC_TB_TAG5 (IDENT_ADDR + 0x1880000a0UL)
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#define LCA_IOC_TB_TAG6 (IDENT_ADDR + 0x1880000c0UL)
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#define LCA_IOC_TB_TAG7 (IDENT_ADDR + 0x1880000e0UL)
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/*
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* Memory spaces:
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*/
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#define LCA_IACK_SC (IDENT_ADDR + 0x1a0000000UL)
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#define LCA_CONF (IDENT_ADDR + 0x1e0000000UL)
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#define LCA_IO (IDENT_ADDR + 0x1c0000000UL)
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#define LCA_SPARSE_MEM (IDENT_ADDR + 0x200000000UL)
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#define LCA_DENSE_MEM (IDENT_ADDR + 0x300000000UL)
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/*
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* Bit definitions for I/O Controller status register 0:
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*/
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#define LCA_IOC_STAT0_CMD 0xf
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#define LCA_IOC_STAT0_ERR (1<<4)
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#define LCA_IOC_STAT0_LOST (1<<5)
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#define LCA_IOC_STAT0_THIT (1<<6)
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#define LCA_IOC_STAT0_TREF (1<<7)
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#define LCA_IOC_STAT0_CODE_SHIFT 8
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#define LCA_IOC_STAT0_CODE_MASK 0x7
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#define LCA_IOC_STAT0_P_NBR_SHIFT 13
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#define LCA_IOC_STAT0_P_NBR_MASK 0x7ffff
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#define LCA_HAE_ADDRESS LCA_IOC_HAE
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/* LCA PMR Power Management register defines */
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#define LCA_PMR_ADDR (IDENT_ADDR + 0x120000098UL)
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#define LCA_PMR_PDIV 0x7 /* Primary clock divisor */
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#define LCA_PMR_ODIV 0x38 /* Override clock divisor */
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#define LCA_PMR_INTO 0x40 /* Interrupt override */
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#define LCA_PMR_DMAO 0x80 /* DMA override */
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#define LCA_PMR_OCCEB 0xffff0000L /* Override cycle counter - even bits */
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#define LCA_PMR_OCCOB 0xffff000000000000L /* Override cycle counter - even bits */
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#define LCA_PMR_PRIMARY_MASK 0xfffffffffffffff8L
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/* LCA PMR Macros */
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#define LCA_READ_PMR (*(volatile unsigned long *)LCA_PMR_ADDR)
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#define LCA_WRITE_PMR(d) (*((volatile unsigned long *)LCA_PMR_ADDR) = (d))
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#define LCA_GET_PRIMARY(r) ((r) & LCA_PMR_PDIV)
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#define LCA_GET_OVERRIDE(r) (((r) >> 3) & LCA_PMR_PDIV)
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#define LCA_SET_PRIMARY_CLOCK(r, c) ((r) = (((r) & LCA_PMR_PRIMARY_MASK)|(c)))
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/* LCA PMR Divisor values */
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#define LCA_PMR_DIV_1 0x0
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#define LCA_PMR_DIV_1_5 0x1
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#define LCA_PMR_DIV_2 0x2
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#define LCA_PMR_DIV_4 0x3
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#define LCA_PMR_DIV_8 0x4
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#define LCA_PMR_DIV_16 0x5
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#define LCA_PMR_DIV_MIN DIV_1
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#define LCA_PMR_DIV_MAX DIV_16
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/*
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* Data structure for handling LCA machine checks. Correctable errors
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* result in a short logout frame, uncorrectable ones in a long one.
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*/
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struct el_lca_mcheck_short {
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struct el_common h; /* common logout header */
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unsigned long esr; /* error-status register */
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unsigned long ear; /* error-address register */
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unsigned long dc_stat; /* dcache status register */
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unsigned long ioc_stat0; /* I/O controller status register 0 */
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unsigned long ioc_stat1; /* I/O controller status register 1 */
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};
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struct el_lca_mcheck_long {
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struct el_common h; /* common logout header */
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unsigned long pt[31]; /* PAL temps */
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unsigned long exc_addr; /* exception address */
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unsigned long pad1[3];
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unsigned long pal_base; /* PALcode base address */
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unsigned long hier; /* hw interrupt enable */
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unsigned long hirr; /* hw interrupt request */
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unsigned long mm_csr; /* MMU control & status */
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unsigned long dc_stat; /* data cache status */
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unsigned long dc_addr; /* data cache addr register */
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unsigned long abox_ctl; /* address box control register */
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unsigned long esr; /* error status register */
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unsigned long ear; /* error address register */
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unsigned long car; /* cache control register */
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unsigned long ioc_stat0; /* I/O controller status register 0 */
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unsigned long ioc_stat1; /* I/O controller status register 1 */
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unsigned long va; /* virtual address register */
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};
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union el_lca {
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struct el_common * c;
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struct el_lca_mcheck_long * l;
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struct el_lca_mcheck_short * s;
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};
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#ifdef __KERNEL__
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#ifndef __EXTERN_INLINE
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#define __EXTERN_INLINE extern inline
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#define __IO_EXTERN_INLINE
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#endif
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/*
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* I/O functions:
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*
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* Unlike Jensen, the Noname machines have no concept of local
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* I/O---everything goes over the PCI bus.
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*
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* There is plenty room for optimization here. In particular,
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* the Alpha's insb/insw/extb/extw should be useful in moving
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* data to/from the right byte-lanes.
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*/
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#define vip volatile int __force *
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#define vuip volatile unsigned int __force *
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#define vulp volatile unsigned long __force *
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#define LCA_SET_HAE \
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do { \
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if (addr >= (1UL << 24)) { \
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unsigned long msb = addr & 0xf8000000; \
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addr -= msb; \
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set_hae(msb); \
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} \
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} while (0)
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__EXTERN_INLINE unsigned int lca_ioread8(void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long) xaddr;
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unsigned long result, base_and_type;
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if (addr >= LCA_DENSE_MEM) {
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addr -= LCA_DENSE_MEM;
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LCA_SET_HAE;
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base_and_type = LCA_SPARSE_MEM + 0x00;
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} else {
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addr -= LCA_IO;
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base_and_type = LCA_IO + 0x00;
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}
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result = *(vip) ((addr << 5) + base_and_type);
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return __kernel_extbl(result, addr & 3);
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}
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__EXTERN_INLINE void lca_iowrite8(u8 b, void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long) xaddr;
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unsigned long w, base_and_type;
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if (addr >= LCA_DENSE_MEM) {
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addr -= LCA_DENSE_MEM;
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LCA_SET_HAE;
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base_and_type = LCA_SPARSE_MEM + 0x00;
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} else {
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addr -= LCA_IO;
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base_and_type = LCA_IO + 0x00;
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}
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w = __kernel_insbl(b, addr & 3);
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*(vuip) ((addr << 5) + base_and_type) = w;
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}
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__EXTERN_INLINE unsigned int lca_ioread16(void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long) xaddr;
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unsigned long result, base_and_type;
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if (addr >= LCA_DENSE_MEM) {
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addr -= LCA_DENSE_MEM;
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LCA_SET_HAE;
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base_and_type = LCA_SPARSE_MEM + 0x08;
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} else {
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addr -= LCA_IO;
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base_and_type = LCA_IO + 0x08;
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}
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result = *(vip) ((addr << 5) + base_and_type);
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return __kernel_extwl(result, addr & 3);
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}
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__EXTERN_INLINE void lca_iowrite16(u16 b, void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long) xaddr;
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unsigned long w, base_and_type;
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if (addr >= LCA_DENSE_MEM) {
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addr -= LCA_DENSE_MEM;
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LCA_SET_HAE;
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base_and_type = LCA_SPARSE_MEM + 0x08;
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} else {
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addr -= LCA_IO;
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base_and_type = LCA_IO + 0x08;
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}
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w = __kernel_inswl(b, addr & 3);
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*(vuip) ((addr << 5) + base_and_type) = w;
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}
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__EXTERN_INLINE unsigned int lca_ioread32(void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long) xaddr;
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if (addr < LCA_DENSE_MEM)
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addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18;
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return *(vuip)addr;
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}
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__EXTERN_INLINE void lca_iowrite32(u32 b, void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long) xaddr;
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if (addr < LCA_DENSE_MEM)
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addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18;
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*(vuip)addr = b;
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}
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__EXTERN_INLINE void __iomem *lca_ioportmap(unsigned long addr)
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{
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return (void __iomem *)(addr + LCA_IO);
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}
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__EXTERN_INLINE void __iomem *lca_ioremap(unsigned long addr,
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unsigned long size)
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{
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return (void __iomem *)(addr + LCA_DENSE_MEM);
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}
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__EXTERN_INLINE int lca_is_ioaddr(unsigned long addr)
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{
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return addr >= IDENT_ADDR + 0x120000000UL;
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}
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__EXTERN_INLINE int lca_is_mmio(const volatile void __iomem *addr)
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{
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return (unsigned long)addr >= LCA_DENSE_MEM;
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}
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#undef vip
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#undef vuip
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#undef vulp
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#undef __IO_PREFIX
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#define __IO_PREFIX lca
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#define lca_trivial_rw_bw 2
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#define lca_trivial_rw_lq 1
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#define lca_trivial_io_bw 0
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#define lca_trivial_io_lq 0
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#define lca_trivial_iounmap 1
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#include <asm/io_trivial.h>
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#ifdef __IO_EXTERN_INLINE
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#undef __EXTERN_INLINE
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#undef __IO_EXTERN_INLINE
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#endif
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#endif /* __KERNEL__ */
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#endif /* __ALPHA_LCA__H__ */
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