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![Ira Weiny](/assets/img/avatar_default.png)
CXL _OSC Error Reporting Control is used by the OS to determine if Firmware has control of various CXL error reporting capabilities including the event logs. Expose the result of negotiating CXL Error Reporting Control in struct pci_host_bridge for consumption by the CXL drivers. Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Lukas Wunner <lukas@wunner.de> Cc: linux-pci@vger.kernel.org Cc: linux-acpi@vger.kernel.org Signed-off-by: Ira Weiny <ira.weiny@intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/20221212070627.1372402-2-ira.weiny@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
1085 lines
30 KiB
C
1085 lines
30 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $)
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*
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* Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
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* Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
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*/
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#define pr_fmt(fmt) "ACPI: " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/mutex.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/pci.h>
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#include <linux/pci-acpi.h>
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#include <linux/dmar.h>
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#include <linux/acpi.h>
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#include <linux/slab.h>
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#include <linux/dmi.h>
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#include <linux/platform_data/x86/apple.h>
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#include "internal.h"
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#define ACPI_PCI_ROOT_CLASS "pci_bridge"
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#define ACPI_PCI_ROOT_DEVICE_NAME "PCI Root Bridge"
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static int acpi_pci_root_add(struct acpi_device *device,
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const struct acpi_device_id *not_used);
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static void acpi_pci_root_remove(struct acpi_device *device);
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static int acpi_pci_root_scan_dependent(struct acpi_device *adev)
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{
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acpiphp_check_host_bridge(adev);
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return 0;
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}
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#define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \
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| OSC_PCI_ASPM_SUPPORT \
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| OSC_PCI_CLOCK_PM_SUPPORT \
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| OSC_PCI_MSI_SUPPORT)
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static const struct acpi_device_id root_device_ids[] = {
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{"PNP0A03", 0},
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{"", 0},
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};
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static struct acpi_scan_handler pci_root_handler = {
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.ids = root_device_ids,
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.attach = acpi_pci_root_add,
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.detach = acpi_pci_root_remove,
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.hotplug = {
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.enabled = true,
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.scan_dependent = acpi_pci_root_scan_dependent,
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},
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};
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/**
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* acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge
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* @handle: the ACPI CA node in question.
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*
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* Note: we could make this API take a struct acpi_device * instead, but
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* for now, it's more convenient to operate on an acpi_handle.
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*/
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int acpi_is_root_bridge(acpi_handle handle)
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{
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struct acpi_device *device = acpi_fetch_acpi_dev(handle);
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int ret;
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if (!device)
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return 0;
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ret = acpi_match_device_ids(device, root_device_ids);
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if (ret)
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return 0;
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else
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return 1;
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}
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EXPORT_SYMBOL_GPL(acpi_is_root_bridge);
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static acpi_status
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get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data)
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{
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struct resource *res = data;
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struct acpi_resource_address64 address;
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acpi_status status;
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status = acpi_resource_to_address64(resource, &address);
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if (ACPI_FAILURE(status))
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return AE_OK;
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if ((address.address.address_length > 0) &&
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(address.resource_type == ACPI_BUS_NUMBER_RANGE)) {
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res->start = address.address.minimum;
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res->end = address.address.minimum + address.address.address_length - 1;
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}
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return AE_OK;
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}
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static acpi_status try_get_root_bridge_busnr(acpi_handle handle,
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struct resource *res)
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{
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acpi_status status;
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res->start = -1;
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status =
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acpi_walk_resources(handle, METHOD_NAME__CRS,
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get_root_bridge_busnr_callback, res);
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if (ACPI_FAILURE(status))
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return status;
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if (res->start == -1)
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return AE_ERROR;
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return AE_OK;
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}
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struct pci_osc_bit_struct {
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u32 bit;
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char *desc;
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};
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static struct pci_osc_bit_struct pci_osc_support_bit[] = {
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{ OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" },
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{ OSC_PCI_ASPM_SUPPORT, "ASPM" },
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{ OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" },
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{ OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" },
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{ OSC_PCI_MSI_SUPPORT, "MSI" },
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{ OSC_PCI_EDR_SUPPORT, "EDR" },
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{ OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" },
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};
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static struct pci_osc_bit_struct pci_osc_control_bit[] = {
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{ OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" },
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{ OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" },
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{ OSC_PCI_EXPRESS_PME_CONTROL, "PME" },
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{ OSC_PCI_EXPRESS_AER_CONTROL, "AER" },
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{ OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" },
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{ OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" },
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{ OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" },
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};
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static struct pci_osc_bit_struct cxl_osc_support_bit[] = {
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{ OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT, "CXL11PortRegAccess" },
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{ OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT, "CXL20PortDevRegAccess" },
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{ OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT, "CXLProtocolErrorReporting" },
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{ OSC_CXL_NATIVE_HP_SUPPORT, "CXLNativeHotPlug" },
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};
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static struct pci_osc_bit_struct cxl_osc_control_bit[] = {
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{ OSC_CXL_ERROR_REPORTING_CONTROL, "CXLMemErrorReporting" },
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};
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static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,
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struct pci_osc_bit_struct *table, int size)
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{
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char buf[80];
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int i, len = 0;
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struct pci_osc_bit_struct *entry;
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buf[0] = '\0';
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for (i = 0, entry = table; i < size; i++, entry++)
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if (word & entry->bit)
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len += scnprintf(buf + len, sizeof(buf) - len, "%s%s",
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len ? " " : "", entry->desc);
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dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf);
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}
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static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
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{
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decode_osc_bits(root, msg, word, pci_osc_support_bit,
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ARRAY_SIZE(pci_osc_support_bit));
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}
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static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
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{
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decode_osc_bits(root, msg, word, pci_osc_control_bit,
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ARRAY_SIZE(pci_osc_control_bit));
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}
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static void decode_cxl_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
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{
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decode_osc_bits(root, msg, word, cxl_osc_support_bit,
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ARRAY_SIZE(cxl_osc_support_bit));
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}
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static void decode_cxl_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
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{
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decode_osc_bits(root, msg, word, cxl_osc_control_bit,
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ARRAY_SIZE(cxl_osc_control_bit));
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}
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static inline bool is_pcie(struct acpi_pci_root *root)
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{
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return root->bridge_type == ACPI_BRIDGE_TYPE_PCIE;
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}
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static inline bool is_cxl(struct acpi_pci_root *root)
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{
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return root->bridge_type == ACPI_BRIDGE_TYPE_CXL;
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}
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static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766";
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static u8 cxl_osc_uuid_str[] = "68F2D50B-C469-4d8A-BD3D-941A103FD3FC";
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static char *to_uuid(struct acpi_pci_root *root)
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{
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if (is_cxl(root))
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return cxl_osc_uuid_str;
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return pci_osc_uuid_str;
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}
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static int cap_length(struct acpi_pci_root *root)
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{
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if (is_cxl(root))
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return sizeof(u32) * OSC_CXL_CAPABILITY_DWORDS;
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return sizeof(u32) * OSC_PCI_CAPABILITY_DWORDS;
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}
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static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
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const u32 *capbuf, u32 *pci_control,
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u32 *cxl_control)
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{
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struct acpi_osc_context context = {
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.uuid_str = to_uuid(root),
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.rev = 1,
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.cap.length = cap_length(root),
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.cap.pointer = (void *)capbuf,
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};
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acpi_status status;
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status = acpi_run_osc(root->device->handle, &context);
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if (ACPI_SUCCESS(status)) {
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*pci_control = acpi_osc_ctx_get_pci_control(&context);
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if (is_cxl(root))
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*cxl_control = acpi_osc_ctx_get_cxl_control(&context);
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kfree(context.ret.pointer);
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}
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return status;
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}
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static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, u32 support,
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u32 *control, u32 cxl_support,
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u32 *cxl_control)
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{
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acpi_status status;
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u32 pci_result, cxl_result, capbuf[OSC_CXL_CAPABILITY_DWORDS];
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support |= root->osc_support_set;
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capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE;
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capbuf[OSC_SUPPORT_DWORD] = support;
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capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
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if (is_cxl(root)) {
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cxl_support |= root->osc_ext_support_set;
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capbuf[OSC_EXT_SUPPORT_DWORD] = cxl_support;
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capbuf[OSC_EXT_CONTROL_DWORD] = *cxl_control | root->osc_ext_control_set;
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}
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retry:
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status = acpi_pci_run_osc(root, capbuf, &pci_result, &cxl_result);
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if (ACPI_SUCCESS(status)) {
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root->osc_support_set = support;
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*control = pci_result;
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if (is_cxl(root)) {
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root->osc_ext_support_set = cxl_support;
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*cxl_control = cxl_result;
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}
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} else if (is_cxl(root)) {
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/*
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* CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC
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* upon any failure using CXL _OSC.
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*/
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root->bridge_type = ACPI_BRIDGE_TYPE_PCIE;
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goto retry;
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}
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return status;
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}
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struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle)
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{
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struct acpi_device *device = acpi_fetch_acpi_dev(handle);
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struct acpi_pci_root *root;
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if (!device || acpi_match_device_ids(device, root_device_ids))
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return NULL;
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root = acpi_driver_data(device);
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return root;
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}
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EXPORT_SYMBOL_GPL(acpi_pci_find_root);
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struct acpi_handle_node {
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struct list_head node;
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acpi_handle handle;
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};
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/**
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* acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev
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* @handle: the handle in question
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*
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* Given an ACPI CA handle, the desired PCI device is located in the
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* list of PCI devices.
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*
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* If the device is found, its reference count is increased and this
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* function returns a pointer to its data structure. The caller must
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* decrement the reference count by calling pci_dev_put().
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* If no device is found, %NULL is returned.
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*/
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struct pci_dev *acpi_get_pci_dev(acpi_handle handle)
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{
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struct acpi_device *adev = acpi_fetch_acpi_dev(handle);
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struct acpi_device_physical_node *pn;
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struct pci_dev *pci_dev = NULL;
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if (!adev)
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return NULL;
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mutex_lock(&adev->physical_node_lock);
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list_for_each_entry(pn, &adev->physical_node_list, node) {
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if (dev_is_pci(pn->dev)) {
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get_device(pn->dev);
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pci_dev = to_pci_dev(pn->dev);
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break;
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}
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}
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mutex_unlock(&adev->physical_node_lock);
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return pci_dev;
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}
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EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
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/**
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* acpi_pci_osc_control_set - Request control of PCI root _OSC features.
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* @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex).
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* @mask: Mask of _OSC bits to request control of, place to store control mask.
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* @support: _OSC supported capability.
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* @cxl_mask: Mask of CXL _OSC control bits, place to store control mask.
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* @cxl_support: CXL _OSC supported capability.
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*
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* Run _OSC query for @mask and if that is successful, compare the returned
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* mask of control bits with @req. If all of the @req bits are set in the
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* returned mask, run _OSC request for it.
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*
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* The variable at the @mask address may be modified regardless of whether or
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* not the function returns success. On success it will contain the mask of
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* _OSC bits the BIOS has granted control of, but its contents are meaningless
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* on failure.
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**/
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static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask,
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u32 support, u32 *cxl_mask,
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u32 cxl_support)
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{
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u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL;
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struct acpi_pci_root *root;
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acpi_status status;
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u32 ctrl, cxl_ctrl = 0, capbuf[OSC_CXL_CAPABILITY_DWORDS];
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if (!mask)
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return AE_BAD_PARAMETER;
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root = acpi_pci_find_root(handle);
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if (!root)
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return AE_NOT_EXIST;
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ctrl = *mask;
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*mask |= root->osc_control_set;
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if (is_cxl(root)) {
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cxl_ctrl = *cxl_mask;
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*cxl_mask |= root->osc_ext_control_set;
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}
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/* Need to check the available controls bits before requesting them. */
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do {
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u32 pci_missing = 0, cxl_missing = 0;
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status = acpi_pci_query_osc(root, support, mask, cxl_support,
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cxl_mask);
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if (ACPI_FAILURE(status))
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return status;
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if (is_cxl(root)) {
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if (ctrl == *mask && cxl_ctrl == *cxl_mask)
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break;
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pci_missing = ctrl & ~(*mask);
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cxl_missing = cxl_ctrl & ~(*cxl_mask);
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} else {
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if (ctrl == *mask)
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break;
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pci_missing = ctrl & ~(*mask);
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}
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if (pci_missing)
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decode_osc_control(root, "platform does not support",
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pci_missing);
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if (cxl_missing)
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decode_cxl_osc_control(root, "CXL platform does not support",
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cxl_missing);
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ctrl = *mask;
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cxl_ctrl = *cxl_mask;
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} while (*mask || *cxl_mask);
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/* No need to request _OSC if the control was already granted. */
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if ((root->osc_control_set & ctrl) == ctrl &&
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(root->osc_ext_control_set & cxl_ctrl) == cxl_ctrl)
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return AE_OK;
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if ((ctrl & req) != req) {
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decode_osc_control(root, "not requesting control; platform does not support",
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req & ~(ctrl));
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return AE_SUPPORT;
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}
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capbuf[OSC_QUERY_DWORD] = 0;
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capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set;
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capbuf[OSC_CONTROL_DWORD] = ctrl;
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if (is_cxl(root)) {
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capbuf[OSC_EXT_SUPPORT_DWORD] = root->osc_ext_support_set;
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capbuf[OSC_EXT_CONTROL_DWORD] = cxl_ctrl;
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}
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status = acpi_pci_run_osc(root, capbuf, mask, cxl_mask);
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if (ACPI_FAILURE(status))
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return status;
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root->osc_control_set = *mask;
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root->osc_ext_control_set = *cxl_mask;
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return AE_OK;
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}
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static u32 calculate_support(void)
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{
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u32 support;
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/*
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* All supported architectures that use ACPI have support for
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* PCI domains, so we indicate this in _OSC support capabilities.
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*/
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support = OSC_PCI_SEGMENT_GROUPS_SUPPORT;
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support |= OSC_PCI_HPX_TYPE_3_SUPPORT;
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if (pci_ext_cfg_avail())
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support |= OSC_PCI_EXT_CONFIG_SUPPORT;
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if (pcie_aspm_support_enabled())
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support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT;
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if (pci_msi_enabled())
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support |= OSC_PCI_MSI_SUPPORT;
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if (IS_ENABLED(CONFIG_PCIE_EDR))
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support |= OSC_PCI_EDR_SUPPORT;
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return support;
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}
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/*
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* Background on hotplug support, and making it depend on only
|
|
* CONFIG_HOTPLUG_PCI_PCIE vs. also considering CONFIG_MEMORY_HOTPLUG:
|
|
*
|
|
* CONFIG_ACPI_HOTPLUG_MEMORY does depend on CONFIG_MEMORY_HOTPLUG, but
|
|
* there is no existing _OSC for memory hotplug support. The reason is that
|
|
* ACPI memory hotplug requires the OS to acknowledge / coordinate with
|
|
* memory plug events via a scan handler. On the CXL side the equivalent
|
|
* would be if Linux supported the Mechanical Retention Lock [1], or
|
|
* otherwise had some coordination for the driver of a PCI device
|
|
* undergoing hotplug to be consulted on whether the hotplug should
|
|
* proceed or not.
|
|
*
|
|
* The concern is that if Linux says no to supporting CXL hotplug then
|
|
* the BIOS may say no to giving the OS hotplug control of any other PCIe
|
|
* device. So the question here is not whether hotplug is enabled, it's
|
|
* whether it is handled natively by the at all OS, and if
|
|
* CONFIG_HOTPLUG_PCI_PCIE is enabled then the answer is "yes".
|
|
*
|
|
* Otherwise, the plan for CXL coordinated remove, since the kernel does
|
|
* not support blocking hotplug, is to require the memory device to be
|
|
* disabled before hotplug is attempted. When CONFIG_MEMORY_HOTPLUG is
|
|
* disabled that step will fail and the remove attempt cancelled by the
|
|
* user. If that is not honored and the card is removed anyway then it
|
|
* does not matter if CONFIG_MEMORY_HOTPLUG is enabled or not, it will
|
|
* cause a crash and other badness.
|
|
*
|
|
* Therefore, just say yes to CXL hotplug and require removal to
|
|
* be coordinated by userspace unless and until the kernel grows better
|
|
* mechanisms for doing "managed" removal of devices in consultation with
|
|
* the driver.
|
|
*
|
|
* [1]: https://lore.kernel.org/all/20201122014203.4706-1-ashok.raj@intel.com/
|
|
*/
|
|
static u32 calculate_cxl_support(void)
|
|
{
|
|
u32 support;
|
|
|
|
support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
|
|
support |= OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT;
|
|
if (pci_aer_available())
|
|
support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT;
|
|
if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
|
|
support |= OSC_CXL_NATIVE_HP_SUPPORT;
|
|
|
|
return support;
|
|
}
|
|
|
|
static u32 calculate_control(void)
|
|
{
|
|
u32 control;
|
|
|
|
control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL
|
|
| OSC_PCI_EXPRESS_PME_CONTROL;
|
|
|
|
if (IS_ENABLED(CONFIG_PCIEASPM))
|
|
control |= OSC_PCI_EXPRESS_LTR_CONTROL;
|
|
|
|
if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
|
|
control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL;
|
|
|
|
if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC))
|
|
control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL;
|
|
|
|
if (pci_aer_available())
|
|
control |= OSC_PCI_EXPRESS_AER_CONTROL;
|
|
|
|
/*
|
|
* Per the Downstream Port Containment Related Enhancements ECN to
|
|
* the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5,
|
|
* OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC
|
|
* and EDR.
|
|
*/
|
|
if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR))
|
|
control |= OSC_PCI_EXPRESS_DPC_CONTROL;
|
|
|
|
return control;
|
|
}
|
|
|
|
static u32 calculate_cxl_control(void)
|
|
{
|
|
u32 control = 0;
|
|
|
|
if (IS_ENABLED(CONFIG_MEMORY_FAILURE))
|
|
control |= OSC_CXL_ERROR_REPORTING_CONTROL;
|
|
|
|
return control;
|
|
}
|
|
|
|
static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
|
|
{
|
|
struct acpi_device *device = root->device;
|
|
|
|
if (pcie_ports_disabled) {
|
|
dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n");
|
|
return false;
|
|
}
|
|
|
|
if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) {
|
|
decode_osc_support(root, "not requesting OS control; OS requires",
|
|
ACPI_PCIE_REQ_SUPPORT);
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
|
|
{
|
|
u32 support, control = 0, requested = 0;
|
|
u32 cxl_support = 0, cxl_control = 0, cxl_requested = 0;
|
|
acpi_status status;
|
|
struct acpi_device *device = root->device;
|
|
acpi_handle handle = device->handle;
|
|
|
|
/*
|
|
* Apple always return failure on _OSC calls when _OSI("Darwin") has
|
|
* been called successfully. We know the feature set supported by the
|
|
* platform, so avoid calling _OSC at all
|
|
*/
|
|
if (x86_apple_machine) {
|
|
root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL;
|
|
decode_osc_control(root, "OS assumes control of",
|
|
root->osc_control_set);
|
|
return;
|
|
}
|
|
|
|
support = calculate_support();
|
|
|
|
decode_osc_support(root, "OS supports", support);
|
|
|
|
if (os_control_query_checks(root, support))
|
|
requested = control = calculate_control();
|
|
|
|
if (is_cxl(root)) {
|
|
cxl_support = calculate_cxl_support();
|
|
decode_cxl_osc_support(root, "OS supports", cxl_support);
|
|
cxl_requested = cxl_control = calculate_cxl_control();
|
|
}
|
|
|
|
status = acpi_pci_osc_control_set(handle, &control, support,
|
|
&cxl_control, cxl_support);
|
|
if (ACPI_SUCCESS(status)) {
|
|
if (control)
|
|
decode_osc_control(root, "OS now controls", control);
|
|
if (cxl_control)
|
|
decode_cxl_osc_control(root, "OS now controls",
|
|
cxl_control);
|
|
|
|
if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
|
|
/*
|
|
* We have ASPM control, but the FADT indicates that
|
|
* it's unsupported. Leave existing configuration
|
|
* intact and prevent the OS from touching it.
|
|
*/
|
|
dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n");
|
|
*no_aspm = 1;
|
|
}
|
|
} else {
|
|
/*
|
|
* We want to disable ASPM here, but aspm_disabled
|
|
* needs to remain in its state from boot so that we
|
|
* properly handle PCIe 1.1 devices. So we set this
|
|
* flag here, to defer the action until after the ACPI
|
|
* root scan.
|
|
*/
|
|
*no_aspm = 1;
|
|
|
|
/* _OSC is optional for PCI host bridges */
|
|
if (status == AE_NOT_FOUND && !is_pcie(root))
|
|
return;
|
|
|
|
if (control) {
|
|
decode_osc_control(root, "OS requested", requested);
|
|
decode_osc_control(root, "platform willing to grant", control);
|
|
}
|
|
if (cxl_control) {
|
|
decode_cxl_osc_control(root, "OS requested", cxl_requested);
|
|
decode_cxl_osc_control(root, "platform willing to grant",
|
|
cxl_control);
|
|
}
|
|
|
|
dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n",
|
|
acpi_format_exception(status));
|
|
}
|
|
}
|
|
|
|
static int acpi_pci_root_add(struct acpi_device *device,
|
|
const struct acpi_device_id *not_used)
|
|
{
|
|
unsigned long long segment, bus;
|
|
acpi_status status;
|
|
int result;
|
|
struct acpi_pci_root *root;
|
|
acpi_handle handle = device->handle;
|
|
int no_aspm = 0;
|
|
bool hotadd = system_state == SYSTEM_RUNNING;
|
|
const char *acpi_hid;
|
|
|
|
root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
|
|
if (!root)
|
|
return -ENOMEM;
|
|
|
|
segment = 0;
|
|
status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL,
|
|
&segment);
|
|
if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
|
|
dev_err(&device->dev, "can't evaluate _SEG\n");
|
|
result = -ENODEV;
|
|
goto end;
|
|
}
|
|
|
|
/* Check _CRS first, then _BBN. If no _BBN, default to zero. */
|
|
root->secondary.flags = IORESOURCE_BUS;
|
|
status = try_get_root_bridge_busnr(handle, &root->secondary);
|
|
if (ACPI_FAILURE(status)) {
|
|
/*
|
|
* We need both the start and end of the downstream bus range
|
|
* to interpret _CBA (MMCONFIG base address), so it really is
|
|
* supposed to be in _CRS. If we don't find it there, all we
|
|
* can do is assume [_BBN-0xFF] or [0-0xFF].
|
|
*/
|
|
root->secondary.end = 0xFF;
|
|
dev_warn(&device->dev,
|
|
FW_BUG "no secondary bus range in _CRS\n");
|
|
status = acpi_evaluate_integer(handle, METHOD_NAME__BBN,
|
|
NULL, &bus);
|
|
if (ACPI_SUCCESS(status))
|
|
root->secondary.start = bus;
|
|
else if (status == AE_NOT_FOUND)
|
|
root->secondary.start = 0;
|
|
else {
|
|
dev_err(&device->dev, "can't evaluate _BBN\n");
|
|
result = -ENODEV;
|
|
goto end;
|
|
}
|
|
}
|
|
|
|
root->device = device;
|
|
root->segment = segment & 0xFFFF;
|
|
strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME);
|
|
strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS);
|
|
device->driver_data = root;
|
|
|
|
if (hotadd && dmar_device_add(handle)) {
|
|
result = -ENXIO;
|
|
goto end;
|
|
}
|
|
|
|
pr_info("%s [%s] (domain %04x %pR)\n",
|
|
acpi_device_name(device), acpi_device_bid(device),
|
|
root->segment, &root->secondary);
|
|
|
|
root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle);
|
|
|
|
acpi_hid = acpi_device_hid(root->device);
|
|
if (strcmp(acpi_hid, "PNP0A08") == 0)
|
|
root->bridge_type = ACPI_BRIDGE_TYPE_PCIE;
|
|
else if (strcmp(acpi_hid, "ACPI0016") == 0)
|
|
root->bridge_type = ACPI_BRIDGE_TYPE_CXL;
|
|
else
|
|
dev_dbg(&device->dev, "Assuming non-PCIe host bridge\n");
|
|
|
|
negotiate_os_control(root, &no_aspm);
|
|
|
|
/*
|
|
* TBD: Need PCI interface for enumeration/configuration of roots.
|
|
*/
|
|
|
|
/*
|
|
* Scan the Root Bridge
|
|
* --------------------
|
|
* Must do this prior to any attempt to bind the root device, as the
|
|
* PCI namespace does not get created until this call is made (and
|
|
* thus the root bridge's pci_dev does not exist).
|
|
*/
|
|
root->bus = pci_acpi_scan_root(root);
|
|
if (!root->bus) {
|
|
dev_err(&device->dev,
|
|
"Bus %04x:%02x not present in PCI namespace\n",
|
|
root->segment, (unsigned int)root->secondary.start);
|
|
device->driver_data = NULL;
|
|
result = -ENODEV;
|
|
goto remove_dmar;
|
|
}
|
|
|
|
if (no_aspm)
|
|
pcie_no_aspm();
|
|
|
|
pci_acpi_add_bus_pm_notifier(device);
|
|
device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid);
|
|
|
|
if (hotadd) {
|
|
pcibios_resource_survey_bus(root->bus);
|
|
pci_assign_unassigned_root_bus_resources(root->bus);
|
|
/*
|
|
* This is only called for the hotadd case. For the boot-time
|
|
* case, we need to wait until after PCI initialization in
|
|
* order to deal with IOAPICs mapped in on a PCI BAR.
|
|
*
|
|
* This is currently x86-specific, because acpi_ioapic_add()
|
|
* is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC.
|
|
* And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC
|
|
* (see drivers/acpi/Kconfig).
|
|
*/
|
|
acpi_ioapic_add(root->device->handle);
|
|
}
|
|
|
|
pci_lock_rescan_remove();
|
|
pci_bus_add_devices(root->bus);
|
|
pci_unlock_rescan_remove();
|
|
return 1;
|
|
|
|
remove_dmar:
|
|
if (hotadd)
|
|
dmar_device_remove(handle);
|
|
end:
|
|
kfree(root);
|
|
return result;
|
|
}
|
|
|
|
static void acpi_pci_root_remove(struct acpi_device *device)
|
|
{
|
|
struct acpi_pci_root *root = acpi_driver_data(device);
|
|
|
|
pci_lock_rescan_remove();
|
|
|
|
pci_stop_root_bus(root->bus);
|
|
|
|
pci_ioapic_remove(root);
|
|
device_set_wakeup_capable(root->bus->bridge, false);
|
|
pci_acpi_remove_bus_pm_notifier(device);
|
|
|
|
pci_remove_root_bus(root->bus);
|
|
WARN_ON(acpi_ioapic_remove(root));
|
|
|
|
dmar_device_remove(device->handle);
|
|
|
|
pci_unlock_rescan_remove();
|
|
|
|
kfree(root);
|
|
}
|
|
|
|
/*
|
|
* Following code to support acpi_pci_root_create() is copied from
|
|
* arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64
|
|
* and ARM64.
|
|
*/
|
|
static void acpi_pci_root_validate_resources(struct device *dev,
|
|
struct list_head *resources,
|
|
unsigned long type)
|
|
{
|
|
LIST_HEAD(list);
|
|
struct resource *res1, *res2, *root = NULL;
|
|
struct resource_entry *tmp, *entry, *entry2;
|
|
|
|
BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0);
|
|
root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource;
|
|
|
|
list_splice_init(resources, &list);
|
|
resource_list_for_each_entry_safe(entry, tmp, &list) {
|
|
bool free = false;
|
|
resource_size_t end;
|
|
|
|
res1 = entry->res;
|
|
if (!(res1->flags & type))
|
|
goto next;
|
|
|
|
/* Exclude non-addressable range or non-addressable portion */
|
|
end = min(res1->end, root->end);
|
|
if (end <= res1->start) {
|
|
dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n",
|
|
res1);
|
|
free = true;
|
|
goto next;
|
|
} else if (res1->end != end) {
|
|
dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n",
|
|
res1, (unsigned long long)end + 1,
|
|
(unsigned long long)res1->end);
|
|
res1->end = end;
|
|
}
|
|
|
|
resource_list_for_each_entry(entry2, resources) {
|
|
res2 = entry2->res;
|
|
if (!(res2->flags & type))
|
|
continue;
|
|
|
|
/*
|
|
* I don't like throwing away windows because then
|
|
* our resources no longer match the ACPI _CRS, but
|
|
* the kernel resource tree doesn't allow overlaps.
|
|
*/
|
|
if (resource_union(res1, res2, res2)) {
|
|
dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n",
|
|
res2, res1);
|
|
free = true;
|
|
goto next;
|
|
}
|
|
}
|
|
|
|
next:
|
|
resource_list_del(entry);
|
|
if (free)
|
|
resource_list_free_entry(entry);
|
|
else
|
|
resource_list_add_tail(entry, resources);
|
|
}
|
|
}
|
|
|
|
static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode,
|
|
struct resource_entry *entry)
|
|
{
|
|
#ifdef PCI_IOBASE
|
|
struct resource *res = entry->res;
|
|
resource_size_t cpu_addr = res->start;
|
|
resource_size_t pci_addr = cpu_addr - entry->offset;
|
|
resource_size_t length = resource_size(res);
|
|
unsigned long port;
|
|
|
|
if (pci_register_io_range(fwnode, cpu_addr, length))
|
|
goto err;
|
|
|
|
port = pci_address_to_pio(cpu_addr);
|
|
if (port == (unsigned long)-1)
|
|
goto err;
|
|
|
|
res->start = port;
|
|
res->end = port + length - 1;
|
|
entry->offset = port - pci_addr;
|
|
|
|
if (pci_remap_iospace(res, cpu_addr) < 0)
|
|
goto err;
|
|
|
|
pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res);
|
|
return;
|
|
err:
|
|
res->flags |= IORESOURCE_DISABLED;
|
|
#endif
|
|
}
|
|
|
|
int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info)
|
|
{
|
|
int ret;
|
|
struct list_head *list = &info->resources;
|
|
struct acpi_device *device = info->bridge;
|
|
struct resource_entry *entry, *tmp;
|
|
unsigned long flags;
|
|
|
|
flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT;
|
|
ret = acpi_dev_get_resources(device, list,
|
|
acpi_dev_filter_resource_type_cb,
|
|
(void *)flags);
|
|
if (ret < 0)
|
|
dev_warn(&device->dev,
|
|
"failed to parse _CRS method, error code %d\n", ret);
|
|
else if (ret == 0)
|
|
dev_dbg(&device->dev,
|
|
"no IO and memory resources present in _CRS\n");
|
|
else {
|
|
resource_list_for_each_entry_safe(entry, tmp, list) {
|
|
if (entry->res->flags & IORESOURCE_IO)
|
|
acpi_pci_root_remap_iospace(&device->fwnode,
|
|
entry);
|
|
|
|
if (entry->res->flags & IORESOURCE_DISABLED)
|
|
resource_list_destroy_entry(entry);
|
|
else
|
|
entry->res->name = info->name;
|
|
}
|
|
acpi_pci_root_validate_resources(&device->dev, list,
|
|
IORESOURCE_MEM);
|
|
acpi_pci_root_validate_resources(&device->dev, list,
|
|
IORESOURCE_IO);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info)
|
|
{
|
|
struct resource_entry *entry, *tmp;
|
|
struct resource *res, *conflict, *root = NULL;
|
|
|
|
resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
|
|
res = entry->res;
|
|
if (res->flags & IORESOURCE_MEM)
|
|
root = &iomem_resource;
|
|
else if (res->flags & IORESOURCE_IO)
|
|
root = &ioport_resource;
|
|
else
|
|
continue;
|
|
|
|
/*
|
|
* Some legacy x86 host bridge drivers use iomem_resource and
|
|
* ioport_resource as default resource pool, skip it.
|
|
*/
|
|
if (res == root)
|
|
continue;
|
|
|
|
conflict = insert_resource_conflict(root, res);
|
|
if (conflict) {
|
|
dev_info(&info->bridge->dev,
|
|
"ignoring host bridge window %pR (conflicts with %s %pR)\n",
|
|
res, conflict->name, conflict);
|
|
resource_list_destroy_entry(entry);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info)
|
|
{
|
|
struct resource *res;
|
|
struct resource_entry *entry, *tmp;
|
|
|
|
if (!info)
|
|
return;
|
|
|
|
resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
|
|
res = entry->res;
|
|
if (res->parent &&
|
|
(res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
|
|
release_resource(res);
|
|
resource_list_destroy_entry(entry);
|
|
}
|
|
|
|
info->ops->release_info(info);
|
|
}
|
|
|
|
static void acpi_pci_root_release_info(struct pci_host_bridge *bridge)
|
|
{
|
|
struct resource *res;
|
|
struct resource_entry *entry;
|
|
|
|
resource_list_for_each_entry(entry, &bridge->windows) {
|
|
res = entry->res;
|
|
if (res->flags & IORESOURCE_IO)
|
|
pci_unmap_iospace(res);
|
|
if (res->parent &&
|
|
(res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
|
|
release_resource(res);
|
|
}
|
|
__acpi_pci_root_release_info(bridge->release_data);
|
|
}
|
|
|
|
struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
|
|
struct acpi_pci_root_ops *ops,
|
|
struct acpi_pci_root_info *info,
|
|
void *sysdata)
|
|
{
|
|
int ret, busnum = root->secondary.start;
|
|
struct acpi_device *device = root->device;
|
|
int node = acpi_get_node(device->handle);
|
|
struct pci_bus *bus;
|
|
struct pci_host_bridge *host_bridge;
|
|
union acpi_object *obj;
|
|
|
|
info->root = root;
|
|
info->bridge = device;
|
|
info->ops = ops;
|
|
INIT_LIST_HEAD(&info->resources);
|
|
snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x",
|
|
root->segment, busnum);
|
|
|
|
if (ops->init_info && ops->init_info(info))
|
|
goto out_release_info;
|
|
if (ops->prepare_resources)
|
|
ret = ops->prepare_resources(info);
|
|
else
|
|
ret = acpi_pci_probe_root_resources(info);
|
|
if (ret < 0)
|
|
goto out_release_info;
|
|
|
|
pci_acpi_root_add_resources(info);
|
|
pci_add_resource(&info->resources, &root->secondary);
|
|
bus = pci_create_root_bus(NULL, busnum, ops->pci_ops,
|
|
sysdata, &info->resources);
|
|
if (!bus)
|
|
goto out_release_info;
|
|
|
|
host_bridge = to_pci_host_bridge(bus->bridge);
|
|
if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL))
|
|
host_bridge->native_pcie_hotplug = 0;
|
|
if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL))
|
|
host_bridge->native_shpc_hotplug = 0;
|
|
if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL))
|
|
host_bridge->native_aer = 0;
|
|
if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL))
|
|
host_bridge->native_pme = 0;
|
|
if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL))
|
|
host_bridge->native_ltr = 0;
|
|
if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
|
|
host_bridge->native_dpc = 0;
|
|
|
|
if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL))
|
|
host_bridge->native_cxl_error = 0;
|
|
|
|
/*
|
|
* Evaluate the "PCI Boot Configuration" _DSM Function. If it
|
|
* exists and returns 0, we must preserve any PCI resource
|
|
* assignments made by firmware for this host bridge.
|
|
*/
|
|
obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1,
|
|
DSM_PCI_PRESERVE_BOOT_CONFIG, NULL);
|
|
if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0)
|
|
host_bridge->preserve_config = 1;
|
|
ACPI_FREE(obj);
|
|
|
|
acpi_dev_power_up_children_with_adr(device);
|
|
|
|
pci_scan_child_bus(bus);
|
|
pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info,
|
|
info);
|
|
if (node != NUMA_NO_NODE)
|
|
dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node);
|
|
return bus;
|
|
|
|
out_release_info:
|
|
__acpi_pci_root_release_info(info);
|
|
return NULL;
|
|
}
|
|
|
|
void __init acpi_pci_root_init(void)
|
|
{
|
|
if (acpi_pci_disabled)
|
|
return;
|
|
|
|
pci_acpi_crs_quirks();
|
|
acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root");
|
|
}
|