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![Robin Murphy](/assets/img/avatar_default.png)
Coretemp's platform driver is unconventional. All the real work is done globally by the initcall and CPU hotplug notifiers, while the "driver" effectively just wraps an allocation and the registration of the hwmon interface in a long-winded round-trip through the driver core. The whole logic of dynamically creating and destroying platform devices to bring the interfaces up and down is error prone, since it assumes platform_device_add() will synchronously bind the driver and set drvdata before it returns, thus results in a NULL dereference if drivers_autoprobe is turned off for the platform bus. Furthermore, the unusual approach of doing that from within a CPU hotplug notifier, already commented in the code that it deadlocks suspend, also causes lockdep issues for other drivers or subsystems which may want to legitimately register a CPU hotplug notifier from a platform bus notifier. All of these issues can be solved by ripping this unusual behaviour out completely, simply tying the platform devices to the lifetime of the module itself, and directly managing the hwmon interfaces from the hotplug notifiers. There is a slight user-visible change in that /sys/bus/platform/drivers/coretemp will no longer appear, and /sys/devices/platform/coretemp.n will remain present if package n is hotplugged off, but hwmon users should really only be looking for the presence of the hwmon interfaces, whose behaviour remains unchanged. Link: https://lore.kernel.org/lkml/20220922101036.87457-1-janusz.krzysztofik@linux.intel.com/ Link: https://gitlab.freedesktop.org/drm/intel/issues/6641 Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com> Link: https://lore.kernel.org/r/20230103114620.15319-1-janusz.krzysztofik@linux.intel.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
829 lines
21 KiB
C
829 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* coretemp.c - Linux kernel module for hardware monitoring
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* Inspired from many hwmon drivers
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/jiffies.h>
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#include <linux/hwmon.h>
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#include <linux/sysfs.h>
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#include <linux/hwmon-sysfs.h>
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#include <linux/err.h>
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#include <linux/mutex.h>
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#include <linux/list.h>
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#include <linux/platform_device.h>
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#include <linux/cpu.h>
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#include <linux/smp.h>
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#include <linux/moduleparam.h>
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#include <linux/pci.h>
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#include <asm/msr.h>
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#include <asm/processor.h>
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#include <asm/cpu_device_id.h>
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#include <linux/sched/isolation.h>
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#define DRVNAME "coretemp"
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/*
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* force_tjmax only matters when TjMax can't be read from the CPU itself.
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* When set, it replaces the driver's suboptimal heuristic.
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*/
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static int force_tjmax;
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module_param_named(tjmax, force_tjmax, int, 0444);
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MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius");
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#define PKG_SYSFS_ATTR_NO 1 /* Sysfs attribute for package temp */
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#define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */
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#define NUM_REAL_CORES 128 /* Number of Real cores per cpu */
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#define CORETEMP_NAME_LENGTH 19 /* String Length of attrs */
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#define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */
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#define TOTAL_ATTRS (MAX_CORE_ATTRS + 1)
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#define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO)
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#ifdef CONFIG_SMP
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#define for_each_sibling(i, cpu) \
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for_each_cpu(i, topology_sibling_cpumask(cpu))
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#else
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#define for_each_sibling(i, cpu) for (i = 0; false; )
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#endif
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/*
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* Per-Core Temperature Data
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* @tjmax: The static tjmax value when tjmax cannot be retrieved from
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* IA32_TEMPERATURE_TARGET MSR.
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* @last_updated: The time when the current temperature value was updated
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* earlier (in jiffies).
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* @cpu_core_id: The CPU Core from which temperature values should be read
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* This value is passed as "id" field to rdmsr/wrmsr functions.
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* @status_reg: One of IA32_THERM_STATUS or IA32_PACKAGE_THERM_STATUS,
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* from where the temperature values should be read.
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* @attr_size: Total number of pre-core attrs displayed in the sysfs.
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* @is_pkg_data: If this is 1, the temp_data holds pkgtemp data.
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* Otherwise, temp_data holds coretemp data.
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*/
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struct temp_data {
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int temp;
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int tjmax;
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unsigned long last_updated;
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unsigned int cpu;
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u32 cpu_core_id;
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u32 status_reg;
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int attr_size;
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bool is_pkg_data;
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struct sensor_device_attribute sd_attrs[TOTAL_ATTRS];
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char attr_name[TOTAL_ATTRS][CORETEMP_NAME_LENGTH];
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struct attribute *attrs[TOTAL_ATTRS + 1];
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struct attribute_group attr_group;
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struct mutex update_lock;
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};
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/* Platform Data per Physical CPU */
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struct platform_data {
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struct device *hwmon_dev;
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u16 pkg_id;
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u16 cpu_map[NUM_REAL_CORES];
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struct ida ida;
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struct cpumask cpumask;
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struct temp_data *core_data[MAX_CORE_DATA];
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struct device_attribute name_attr;
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};
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struct tjmax_pci {
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unsigned int device;
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int tjmax;
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};
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static const struct tjmax_pci tjmax_pci_table[] = {
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{ 0x0708, 110000 }, /* CE41x0 (Sodaville ) */
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{ 0x0c72, 102000 }, /* Atom S1240 (Centerton) */
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{ 0x0c73, 95000 }, /* Atom S1220 (Centerton) */
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{ 0x0c75, 95000 }, /* Atom S1260 (Centerton) */
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};
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struct tjmax {
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char const *id;
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int tjmax;
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};
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static const struct tjmax tjmax_table[] = {
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{ "CPU 230", 100000 }, /* Model 0x1c, stepping 2 */
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{ "CPU 330", 125000 }, /* Model 0x1c, stepping 2 */
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};
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struct tjmax_model {
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u8 model;
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u8 mask;
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int tjmax;
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};
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#define ANY 0xff
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static const struct tjmax_model tjmax_model_table[] = {
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{ 0x1c, 10, 100000 }, /* D4xx, K4xx, N4xx, D5xx, K5xx, N5xx */
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{ 0x1c, ANY, 90000 }, /* Z5xx, N2xx, possibly others
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* Note: Also matches 230 and 330,
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* which are covered by tjmax_table
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*/
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{ 0x26, ANY, 90000 }, /* Atom Tunnel Creek (Exx), Lincroft (Z6xx)
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* Note: TjMax for E6xxT is 110C, but CPU type
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* is undetectable by software
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*/
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{ 0x27, ANY, 90000 }, /* Atom Medfield (Z2460) */
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{ 0x35, ANY, 90000 }, /* Atom Clover Trail/Cloverview (Z27x0) */
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{ 0x36, ANY, 100000 }, /* Atom Cedar Trail/Cedarview (N2xxx, D2xxx)
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* Also matches S12x0 (stepping 9), covered by
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* PCI table
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*/
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};
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static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
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{
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/* The 100C is default for both mobile and non mobile CPUs */
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int tjmax = 100000;
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int tjmax_ee = 85000;
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int usemsr_ee = 1;
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int err;
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u32 eax, edx;
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int i;
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u16 devfn = PCI_DEVFN(0, 0);
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struct pci_dev *host_bridge = pci_get_domain_bus_and_slot(0, 0, devfn);
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/*
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* Explicit tjmax table entries override heuristics.
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* First try PCI host bridge IDs, followed by model ID strings
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* and model/stepping information.
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*/
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if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL) {
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for (i = 0; i < ARRAY_SIZE(tjmax_pci_table); i++) {
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if (host_bridge->device == tjmax_pci_table[i].device) {
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pci_dev_put(host_bridge);
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return tjmax_pci_table[i].tjmax;
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}
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}
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}
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pci_dev_put(host_bridge);
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for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) {
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if (strstr(c->x86_model_id, tjmax_table[i].id))
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return tjmax_table[i].tjmax;
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}
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for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) {
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const struct tjmax_model *tm = &tjmax_model_table[i];
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if (c->x86_model == tm->model &&
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(tm->mask == ANY || c->x86_stepping == tm->mask))
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return tm->tjmax;
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}
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/* Early chips have no MSR for TjMax */
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if (c->x86_model == 0xf && c->x86_stepping < 4)
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usemsr_ee = 0;
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if (c->x86_model > 0xe && usemsr_ee) {
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u8 platform_id;
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/*
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* Now we can detect the mobile CPU using Intel provided table
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* http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
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* For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
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*/
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err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
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if (err) {
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dev_warn(dev,
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"Unable to access MSR 0x17, assuming desktop"
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" CPU\n");
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usemsr_ee = 0;
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} else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
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/*
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* Trust bit 28 up to Penryn, I could not find any
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* documentation on that; if you happen to know
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* someone at Intel please ask
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*/
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usemsr_ee = 0;
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} else {
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/* Platform ID bits 52:50 (EDX starts at bit 32) */
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platform_id = (edx >> 18) & 0x7;
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/*
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* Mobile Penryn CPU seems to be platform ID 7 or 5
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* (guesswork)
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*/
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if (c->x86_model == 0x17 &&
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(platform_id == 5 || platform_id == 7)) {
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/*
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* If MSR EE bit is set, set it to 90 degrees C,
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* otherwise 105 degrees C
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*/
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tjmax_ee = 90000;
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tjmax = 105000;
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}
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}
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}
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if (usemsr_ee) {
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err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
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if (err) {
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dev_warn(dev,
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"Unable to access MSR 0xEE, for Tjmax, left"
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" at default\n");
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} else if (eax & 0x40000000) {
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tjmax = tjmax_ee;
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}
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} else if (tjmax == 100000) {
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/*
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* If we don't use msr EE it means we are desktop CPU
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* (with exeception of Atom)
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*/
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dev_warn(dev, "Using relative temperature scale!\n");
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}
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return tjmax;
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}
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static bool cpu_has_tjmax(struct cpuinfo_x86 *c)
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{
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u8 model = c->x86_model;
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return model > 0xe &&
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model != 0x1c &&
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model != 0x26 &&
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model != 0x27 &&
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model != 0x35 &&
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model != 0x36;
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}
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static int get_tjmax(struct temp_data *tdata, struct device *dev)
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{
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struct cpuinfo_x86 *c = &cpu_data(tdata->cpu);
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int err;
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u32 eax, edx;
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u32 val;
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/* use static tjmax once it is set */
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if (tdata->tjmax)
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return tdata->tjmax;
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/*
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* A new feature of current Intel(R) processors, the
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* IA32_TEMPERATURE_TARGET contains the TjMax value
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*/
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err = rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
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if (err) {
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if (cpu_has_tjmax(c))
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dev_warn(dev, "Unable to read TjMax from CPU %u\n", tdata->cpu);
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} else {
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val = (eax >> 16) & 0xff;
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/*
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* If the TjMax is not plausible, an assumption
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* will be used
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*/
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if (val) {
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dev_dbg(dev, "TjMax is %d degrees C\n", val);
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return val * 1000;
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}
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}
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if (force_tjmax) {
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dev_notice(dev, "TjMax forced to %d degrees C by user\n",
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force_tjmax);
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tdata->tjmax = force_tjmax * 1000;
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} else {
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/*
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* An assumption is made for early CPUs and unreadable MSR.
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* NOTE: the calculated value may not be correct.
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*/
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tdata->tjmax = adjust_tjmax(c, tdata->cpu, dev);
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}
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return tdata->tjmax;
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}
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static int get_ttarget(struct temp_data *tdata, struct device *dev)
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{
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u32 eax, edx;
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int tjmax, ttarget_offset, ret;
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/*
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* ttarget is valid only if tjmax can be retrieved from
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* MSR_IA32_TEMPERATURE_TARGET
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*/
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if (tdata->tjmax)
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return -ENODEV;
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ret = rdmsr_safe_on_cpu(tdata->cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
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if (ret)
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return ret;
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tjmax = (eax >> 16) & 0xff;
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/* Read the still undocumented bits 8:15 of IA32_TEMPERATURE_TARGET. */
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ttarget_offset = (eax >> 8) & 0xff;
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return (tjmax - ttarget_offset) * 1000;
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}
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/* Keep track of how many zone pointers we allocated in init() */
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static int max_zones __read_mostly;
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/* Array of zone pointers. Serialized by cpu hotplug lock */
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static struct platform_device **zone_devices;
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static ssize_t show_label(struct device *dev,
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struct device_attribute *devattr, char *buf)
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{
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struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
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struct platform_data *pdata = dev_get_drvdata(dev);
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struct temp_data *tdata = pdata->core_data[attr->index];
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if (tdata->is_pkg_data)
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return sprintf(buf, "Package id %u\n", pdata->pkg_id);
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return sprintf(buf, "Core %u\n", tdata->cpu_core_id);
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}
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static ssize_t show_crit_alarm(struct device *dev,
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struct device_attribute *devattr, char *buf)
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{
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u32 eax, edx;
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struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
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struct platform_data *pdata = dev_get_drvdata(dev);
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struct temp_data *tdata = pdata->core_data[attr->index];
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mutex_lock(&tdata->update_lock);
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rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx);
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mutex_unlock(&tdata->update_lock);
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return sprintf(buf, "%d\n", (eax >> 5) & 1);
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}
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static ssize_t show_tjmax(struct device *dev,
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struct device_attribute *devattr, char *buf)
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{
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struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
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struct platform_data *pdata = dev_get_drvdata(dev);
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struct temp_data *tdata = pdata->core_data[attr->index];
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int tjmax;
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mutex_lock(&tdata->update_lock);
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tjmax = get_tjmax(tdata, dev);
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mutex_unlock(&tdata->update_lock);
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return sprintf(buf, "%d\n", tjmax);
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}
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static ssize_t show_ttarget(struct device *dev,
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struct device_attribute *devattr, char *buf)
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{
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struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
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struct platform_data *pdata = dev_get_drvdata(dev);
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struct temp_data *tdata = pdata->core_data[attr->index];
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int ttarget;
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mutex_lock(&tdata->update_lock);
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ttarget = get_ttarget(tdata, dev);
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mutex_unlock(&tdata->update_lock);
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if (ttarget < 0)
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return ttarget;
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return sprintf(buf, "%d\n", ttarget);
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}
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static ssize_t show_temp(struct device *dev,
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struct device_attribute *devattr, char *buf)
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{
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u32 eax, edx;
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struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
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struct platform_data *pdata = dev_get_drvdata(dev);
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struct temp_data *tdata = pdata->core_data[attr->index];
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int tjmax;
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mutex_lock(&tdata->update_lock);
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tjmax = get_tjmax(tdata, dev);
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/* Check whether the time interval has elapsed */
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if (time_after(jiffies, tdata->last_updated + HZ)) {
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rdmsr_on_cpu(tdata->cpu, tdata->status_reg, &eax, &edx);
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/*
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* Ignore the valid bit. In all observed cases the register
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* value is either low or zero if the valid bit is 0.
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* Return it instead of reporting an error which doesn't
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* really help at all.
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*/
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tdata->temp = tjmax - ((eax >> 16) & 0x7f) * 1000;
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tdata->last_updated = jiffies;
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}
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mutex_unlock(&tdata->update_lock);
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return sprintf(buf, "%d\n", tdata->temp);
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}
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static int create_core_attrs(struct temp_data *tdata, struct device *dev,
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int attr_no)
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{
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int i;
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static ssize_t (*const rd_ptr[TOTAL_ATTRS]) (struct device *dev,
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struct device_attribute *devattr, char *buf) = {
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show_label, show_crit_alarm, show_temp, show_tjmax,
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show_ttarget };
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static const char *const suffixes[TOTAL_ATTRS] = {
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"label", "crit_alarm", "input", "crit", "max"
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};
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for (i = 0; i < tdata->attr_size; i++) {
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snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH,
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"temp%d_%s", attr_no, suffixes[i]);
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sysfs_attr_init(&tdata->sd_attrs[i].dev_attr.attr);
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tdata->sd_attrs[i].dev_attr.attr.name = tdata->attr_name[i];
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tdata->sd_attrs[i].dev_attr.attr.mode = 0444;
|
|
tdata->sd_attrs[i].dev_attr.show = rd_ptr[i];
|
|
tdata->sd_attrs[i].index = attr_no;
|
|
tdata->attrs[i] = &tdata->sd_attrs[i].dev_attr.attr;
|
|
}
|
|
tdata->attr_group.attrs = tdata->attrs;
|
|
return sysfs_create_group(&dev->kobj, &tdata->attr_group);
|
|
}
|
|
|
|
|
|
static int chk_ucode_version(unsigned int cpu)
|
|
{
|
|
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
|
|
|
/*
|
|
* Check if we have problem with errata AE18 of Core processors:
|
|
* Readings might stop update when processor visited too deep sleep,
|
|
* fixed for stepping D0 (6EC).
|
|
*/
|
|
if (c->x86_model == 0xe && c->x86_stepping < 0xc && c->microcode < 0x39) {
|
|
pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n");
|
|
return -ENODEV;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_device *coretemp_get_pdev(unsigned int cpu)
|
|
{
|
|
int id = topology_logical_die_id(cpu);
|
|
|
|
if (id >= 0 && id < max_zones)
|
|
return zone_devices[id];
|
|
return NULL;
|
|
}
|
|
|
|
static struct temp_data *init_temp_data(unsigned int cpu, int pkg_flag)
|
|
{
|
|
struct temp_data *tdata;
|
|
|
|
tdata = kzalloc(sizeof(struct temp_data), GFP_KERNEL);
|
|
if (!tdata)
|
|
return NULL;
|
|
|
|
tdata->status_reg = pkg_flag ? MSR_IA32_PACKAGE_THERM_STATUS :
|
|
MSR_IA32_THERM_STATUS;
|
|
tdata->is_pkg_data = pkg_flag;
|
|
tdata->cpu = cpu;
|
|
tdata->cpu_core_id = topology_core_id(cpu);
|
|
tdata->attr_size = MAX_CORE_ATTRS;
|
|
mutex_init(&tdata->update_lock);
|
|
return tdata;
|
|
}
|
|
|
|
static int create_core_data(struct platform_device *pdev, unsigned int cpu,
|
|
int pkg_flag)
|
|
{
|
|
struct temp_data *tdata;
|
|
struct platform_data *pdata = platform_get_drvdata(pdev);
|
|
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
|
u32 eax, edx;
|
|
int err, index, attr_no;
|
|
|
|
if (!housekeeping_cpu(cpu, HK_TYPE_MISC))
|
|
return 0;
|
|
|
|
/*
|
|
* Find attr number for sysfs:
|
|
* We map the attr number to core id of the CPU
|
|
* The attr number is always core id + 2
|
|
* The Pkgtemp will always show up as temp1_*, if available
|
|
*/
|
|
if (pkg_flag) {
|
|
attr_no = PKG_SYSFS_ATTR_NO;
|
|
} else {
|
|
index = ida_alloc(&pdata->ida, GFP_KERNEL);
|
|
if (index < 0)
|
|
return index;
|
|
pdata->cpu_map[index] = topology_core_id(cpu);
|
|
attr_no = index + BASE_SYSFS_ATTR_NO;
|
|
}
|
|
|
|
if (attr_no > MAX_CORE_DATA - 1) {
|
|
err = -ERANGE;
|
|
goto ida_free;
|
|
}
|
|
|
|
tdata = init_temp_data(cpu, pkg_flag);
|
|
if (!tdata) {
|
|
err = -ENOMEM;
|
|
goto ida_free;
|
|
}
|
|
|
|
/* Test if we can access the status register */
|
|
err = rdmsr_safe_on_cpu(cpu, tdata->status_reg, &eax, &edx);
|
|
if (err)
|
|
goto exit_free;
|
|
|
|
/* Make sure tdata->tjmax is a valid indicator for dynamic/static tjmax */
|
|
get_tjmax(tdata, &pdev->dev);
|
|
|
|
/*
|
|
* The target temperature is available on older CPUs but not in the
|
|
* MSR_IA32_TEMPERATURE_TARGET register. Atoms don't have the register
|
|
* at all.
|
|
*/
|
|
if (c->x86_model > 0xe && c->x86_model != 0x1c)
|
|
if (get_ttarget(tdata, &pdev->dev) >= 0)
|
|
tdata->attr_size++;
|
|
|
|
pdata->core_data[attr_no] = tdata;
|
|
|
|
/* Create sysfs interfaces */
|
|
err = create_core_attrs(tdata, pdata->hwmon_dev, attr_no);
|
|
if (err)
|
|
goto exit_free;
|
|
|
|
return 0;
|
|
exit_free:
|
|
pdata->core_data[attr_no] = NULL;
|
|
kfree(tdata);
|
|
ida_free:
|
|
if (!pkg_flag)
|
|
ida_free(&pdata->ida, index);
|
|
return err;
|
|
}
|
|
|
|
static void
|
|
coretemp_add_core(struct platform_device *pdev, unsigned int cpu, int pkg_flag)
|
|
{
|
|
if (create_core_data(pdev, cpu, pkg_flag))
|
|
dev_err(&pdev->dev, "Adding Core %u failed\n", cpu);
|
|
}
|
|
|
|
static void coretemp_remove_core(struct platform_data *pdata, int indx)
|
|
{
|
|
struct temp_data *tdata = pdata->core_data[indx];
|
|
|
|
/* if we errored on add then this is already gone */
|
|
if (!tdata)
|
|
return;
|
|
|
|
/* Remove the sysfs attributes */
|
|
sysfs_remove_group(&pdata->hwmon_dev->kobj, &tdata->attr_group);
|
|
|
|
kfree(pdata->core_data[indx]);
|
|
pdata->core_data[indx] = NULL;
|
|
|
|
if (indx >= BASE_SYSFS_ATTR_NO)
|
|
ida_free(&pdata->ida, indx - BASE_SYSFS_ATTR_NO);
|
|
}
|
|
|
|
static int coretemp_device_add(int zoneid)
|
|
{
|
|
struct platform_device *pdev;
|
|
struct platform_data *pdata;
|
|
int err;
|
|
|
|
/* Initialize the per-zone data structures */
|
|
pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
|
|
if (!pdata)
|
|
return -ENOMEM;
|
|
|
|
pdata->pkg_id = zoneid;
|
|
ida_init(&pdata->ida);
|
|
|
|
pdev = platform_device_alloc(DRVNAME, zoneid);
|
|
if (!pdev) {
|
|
err = -ENOMEM;
|
|
goto err_free_pdata;
|
|
}
|
|
|
|
err = platform_device_add(pdev);
|
|
if (err)
|
|
goto err_put_dev;
|
|
|
|
platform_set_drvdata(pdev, pdata);
|
|
zone_devices[zoneid] = pdev;
|
|
return 0;
|
|
|
|
err_put_dev:
|
|
platform_device_put(pdev);
|
|
err_free_pdata:
|
|
kfree(pdata);
|
|
return err;
|
|
}
|
|
|
|
static void coretemp_device_remove(int zoneid)
|
|
{
|
|
struct platform_device *pdev = zone_devices[zoneid];
|
|
struct platform_data *pdata = platform_get_drvdata(pdev);
|
|
|
|
ida_destroy(&pdata->ida);
|
|
kfree(pdata);
|
|
platform_device_unregister(pdev);
|
|
}
|
|
|
|
static int coretemp_cpu_online(unsigned int cpu)
|
|
{
|
|
struct platform_device *pdev = coretemp_get_pdev(cpu);
|
|
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
|
struct platform_data *pdata;
|
|
|
|
/*
|
|
* Don't execute this on resume as the offline callback did
|
|
* not get executed on suspend.
|
|
*/
|
|
if (cpuhp_tasks_frozen)
|
|
return 0;
|
|
|
|
/*
|
|
* CPUID.06H.EAX[0] indicates whether the CPU has thermal
|
|
* sensors. We check this bit only, all the early CPUs
|
|
* without thermal sensors will be filtered out.
|
|
*/
|
|
if (!cpu_has(c, X86_FEATURE_DTHERM))
|
|
return -ENODEV;
|
|
|
|
pdata = platform_get_drvdata(pdev);
|
|
if (!pdata->hwmon_dev) {
|
|
struct device *hwmon;
|
|
|
|
/* Check the microcode version of the CPU */
|
|
if (chk_ucode_version(cpu))
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* Alright, we have DTS support.
|
|
* We are bringing the _first_ core in this pkg
|
|
* online. So, initialize per-pkg data structures and
|
|
* then bring this core online.
|
|
*/
|
|
hwmon = hwmon_device_register_with_groups(&pdev->dev, DRVNAME,
|
|
pdata, NULL);
|
|
if (IS_ERR(hwmon))
|
|
return PTR_ERR(hwmon);
|
|
pdata->hwmon_dev = hwmon;
|
|
|
|
/*
|
|
* Check whether pkgtemp support is available.
|
|
* If so, add interfaces for pkgtemp.
|
|
*/
|
|
if (cpu_has(c, X86_FEATURE_PTS))
|
|
coretemp_add_core(pdev, cpu, 1);
|
|
}
|
|
|
|
/*
|
|
* Check whether a thread sibling is already online. If not add the
|
|
* interface for this CPU core.
|
|
*/
|
|
if (!cpumask_intersects(&pdata->cpumask, topology_sibling_cpumask(cpu)))
|
|
coretemp_add_core(pdev, cpu, 0);
|
|
|
|
cpumask_set_cpu(cpu, &pdata->cpumask);
|
|
return 0;
|
|
}
|
|
|
|
static int coretemp_cpu_offline(unsigned int cpu)
|
|
{
|
|
struct platform_device *pdev = coretemp_get_pdev(cpu);
|
|
struct platform_data *pd;
|
|
struct temp_data *tdata;
|
|
int i, indx = -1, target;
|
|
|
|
/* No need to tear down any interfaces for suspend */
|
|
if (cpuhp_tasks_frozen)
|
|
return 0;
|
|
|
|
/* If the physical CPU device does not exist, just return */
|
|
pd = platform_get_drvdata(pdev);
|
|
if (!pd->hwmon_dev)
|
|
return 0;
|
|
|
|
for (i = 0; i < NUM_REAL_CORES; i++) {
|
|
if (pd->cpu_map[i] == topology_core_id(cpu)) {
|
|
indx = i + BASE_SYSFS_ATTR_NO;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Too many cores and this core is not populated, just return */
|
|
if (indx < 0)
|
|
return 0;
|
|
|
|
tdata = pd->core_data[indx];
|
|
|
|
cpumask_clear_cpu(cpu, &pd->cpumask);
|
|
|
|
/*
|
|
* If this is the last thread sibling, remove the CPU core
|
|
* interface, If there is still a sibling online, transfer the
|
|
* target cpu of that core interface to it.
|
|
*/
|
|
target = cpumask_any_and(&pd->cpumask, topology_sibling_cpumask(cpu));
|
|
if (target >= nr_cpu_ids) {
|
|
coretemp_remove_core(pd, indx);
|
|
} else if (tdata && tdata->cpu == cpu) {
|
|
mutex_lock(&tdata->update_lock);
|
|
tdata->cpu = target;
|
|
mutex_unlock(&tdata->update_lock);
|
|
}
|
|
|
|
/*
|
|
* If all cores in this pkg are offline, remove the interface.
|
|
*/
|
|
tdata = pd->core_data[PKG_SYSFS_ATTR_NO];
|
|
if (cpumask_empty(&pd->cpumask)) {
|
|
if (tdata)
|
|
coretemp_remove_core(pd, PKG_SYSFS_ATTR_NO);
|
|
hwmon_device_unregister(pd->hwmon_dev);
|
|
pd->hwmon_dev = NULL;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Check whether this core is the target for the package
|
|
* interface. We need to assign it to some other cpu.
|
|
*/
|
|
if (tdata && tdata->cpu == cpu) {
|
|
target = cpumask_first(&pd->cpumask);
|
|
mutex_lock(&tdata->update_lock);
|
|
tdata->cpu = target;
|
|
mutex_unlock(&tdata->update_lock);
|
|
}
|
|
return 0;
|
|
}
|
|
static const struct x86_cpu_id __initconst coretemp_ids[] = {
|
|
X86_MATCH_VENDOR_FEATURE(INTEL, X86_FEATURE_DTHERM, NULL),
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(x86cpu, coretemp_ids);
|
|
|
|
static enum cpuhp_state coretemp_hp_online;
|
|
|
|
static int __init coretemp_init(void)
|
|
{
|
|
int i, err;
|
|
|
|
/*
|
|
* CPUID.06H.EAX[0] indicates whether the CPU has thermal
|
|
* sensors. We check this bit only, all the early CPUs
|
|
* without thermal sensors will be filtered out.
|
|
*/
|
|
if (!x86_match_cpu(coretemp_ids))
|
|
return -ENODEV;
|
|
|
|
max_zones = topology_max_packages() * topology_max_die_per_package();
|
|
zone_devices = kcalloc(max_zones, sizeof(struct platform_device *),
|
|
GFP_KERNEL);
|
|
if (!zone_devices)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < max_zones; i++) {
|
|
err = coretemp_device_add(i);
|
|
if (err)
|
|
goto outzone;
|
|
}
|
|
|
|
err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "hwmon/coretemp:online",
|
|
coretemp_cpu_online, coretemp_cpu_offline);
|
|
if (err < 0)
|
|
goto outzone;
|
|
coretemp_hp_online = err;
|
|
return 0;
|
|
|
|
outzone:
|
|
while (i--)
|
|
coretemp_device_remove(i);
|
|
kfree(zone_devices);
|
|
return err;
|
|
}
|
|
module_init(coretemp_init)
|
|
|
|
static void __exit coretemp_exit(void)
|
|
{
|
|
int i;
|
|
|
|
cpuhp_remove_state(coretemp_hp_online);
|
|
for (i = 0; i < max_zones; i++)
|
|
coretemp_device_remove(i);
|
|
kfree(zone_devices);
|
|
}
|
|
module_exit(coretemp_exit)
|
|
|
|
MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
|
|
MODULE_DESCRIPTION("Intel Core temperature monitor");
|
|
MODULE_LICENSE("GPL");
|