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![Krzysztof Kozlowski](/assets/img/avatar_default.png)
syscon regmap is not used since commitaddebf1588
("mfd: exynos-lpass: Remove pad retention control"). Fixes:addebf1588
("mfd: exynos-lpass: Remove pad retention control") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20220202151310.285561-3-krzysztof.kozlowski@canonical.com
197 lines
5.2 KiB
C
197 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd.
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*
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* Authors: Inha Song <ideal.song@samsung.com>
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* Sylwester Nawrocki <s.nawrocki@samsung.com>
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*
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* Samsung Exynos SoC series Low Power Audio Subsystem driver.
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*
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* This module provides regmap for the Top SFR region and instantiates
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* devices for IP blocks like DMAC, I2S, UART.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/soc/samsung/exynos-regs-pmu.h>
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#include <linux/types.h>
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/* LPASS Top register definitions */
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#define SFR_LPASS_CORE_SW_RESET 0x08
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#define LPASS_SB_SW_RESET BIT(11)
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#define LPASS_UART_SW_RESET BIT(10)
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#define LPASS_PCM_SW_RESET BIT(9)
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#define LPASS_I2S_SW_RESET BIT(8)
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#define LPASS_WDT1_SW_RESET BIT(4)
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#define LPASS_WDT0_SW_RESET BIT(3)
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#define LPASS_TIMER_SW_RESET BIT(2)
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#define LPASS_MEM_SW_RESET BIT(1)
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#define LPASS_DMA_SW_RESET BIT(0)
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#define SFR_LPASS_INTR_CA5_MASK 0x48
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#define SFR_LPASS_INTR_CPU_MASK 0x58
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#define LPASS_INTR_APM BIT(9)
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#define LPASS_INTR_MIF BIT(8)
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#define LPASS_INTR_TIMER BIT(7)
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#define LPASS_INTR_DMA BIT(6)
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#define LPASS_INTR_GPIO BIT(5)
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#define LPASS_INTR_I2S BIT(4)
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#define LPASS_INTR_PCM BIT(3)
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#define LPASS_INTR_SLIMBUS BIT(2)
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#define LPASS_INTR_UART BIT(1)
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#define LPASS_INTR_SFR BIT(0)
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struct exynos_lpass {
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/* pointer to the LPASS TOP regmap */
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struct regmap *top;
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struct clk *sfr0_clk;
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};
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static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
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{
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unsigned int val = 0;
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regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val);
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val &= ~mask;
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regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
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usleep_range(100, 150);
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val |= mask;
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regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val);
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}
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static void exynos_lpass_enable(struct exynos_lpass *lpass)
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{
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clk_prepare_enable(lpass->sfr0_clk);
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/* Unmask SFR, DMA and I2S interrupt */
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regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
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LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
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regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
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LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S |
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LPASS_INTR_UART);
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exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
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exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
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exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
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exynos_lpass_core_sw_reset(lpass, LPASS_UART_SW_RESET);
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}
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static void exynos_lpass_disable(struct exynos_lpass *lpass)
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{
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/* Mask any unmasked IP interrupt sources */
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regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
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regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
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clk_disable_unprepare(lpass->sfr0_clk);
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}
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static const struct regmap_config exynos_lpass_reg_conf = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0xfc,
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.fast_io = true,
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};
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static int exynos_lpass_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct exynos_lpass *lpass;
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void __iomem *base_top;
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struct resource *res;
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lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL);
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if (!lpass)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base_top = devm_ioremap_resource(dev, res);
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if (IS_ERR(base_top))
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return PTR_ERR(base_top);
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lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl");
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if (IS_ERR(lpass->sfr0_clk))
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return PTR_ERR(lpass->sfr0_clk);
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lpass->top = regmap_init_mmio(dev, base_top,
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&exynos_lpass_reg_conf);
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if (IS_ERR(lpass->top)) {
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dev_err(dev, "LPASS top regmap initialization failed\n");
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return PTR_ERR(lpass->top);
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}
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platform_set_drvdata(pdev, lpass);
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
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exynos_lpass_enable(lpass);
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return devm_of_platform_populate(dev);
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}
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static int exynos_lpass_remove(struct platform_device *pdev)
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{
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struct exynos_lpass *lpass = platform_get_drvdata(pdev);
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exynos_lpass_disable(lpass);
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pm_runtime_disable(&pdev->dev);
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if (!pm_runtime_status_suspended(&pdev->dev))
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exynos_lpass_disable(lpass);
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regmap_exit(lpass->top);
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return 0;
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}
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static int __maybe_unused exynos_lpass_suspend(struct device *dev)
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{
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struct exynos_lpass *lpass = dev_get_drvdata(dev);
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exynos_lpass_disable(lpass);
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return 0;
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}
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static int __maybe_unused exynos_lpass_resume(struct device *dev)
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{
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struct exynos_lpass *lpass = dev_get_drvdata(dev);
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exynos_lpass_enable(lpass);
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return 0;
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}
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static const struct dev_pm_ops lpass_pm_ops = {
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SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
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SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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};
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static const struct of_device_id exynos_lpass_of_match[] = {
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{ .compatible = "samsung,exynos5433-lpass" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, exynos_lpass_of_match);
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static struct platform_driver exynos_lpass_driver = {
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.driver = {
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.name = "exynos-lpass",
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.pm = &lpass_pm_ops,
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.of_match_table = exynos_lpass_of_match,
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},
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.probe = exynos_lpass_probe,
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.remove = exynos_lpass_remove,
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};
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module_platform_driver(exynos_lpass_driver);
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MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver");
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MODULE_LICENSE("GPL v2");
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