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![Andy Shevchenko](/assets/img/avatar_default.png)
With compile testing on non-OMAP platforms compiler might be not happy: In function ‘twl4030_sih_setup’: error: implicit declaration of function ‘dev_err’ [-Werror=implicit-function-declaration] error: implicit declaration of function ‘dev_info’ [-Werror=implicit-function-declaration] In function ‘twl4030_init_irq’: error: invalid use of undefined type ‘struct device’ Add missed header. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20220923175401.8723-1-andriy.shevchenko@linux.intel.com
775 lines
19 KiB
C
775 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* twl4030-irq.c - TWL4030/TPS659x0 irq support
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*
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* Copyright (C) 2005-2006 Texas Instruments, Inc.
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*
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* Modifications to defer interrupt handling to a kernel thread:
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* Copyright (C) 2006 MontaVista Software, Inc.
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*
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* Based on tlv320aic23.c:
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* Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
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*
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* Code cleanup and modifications to IRQ handler.
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* by syed khasim <x0khasim@ti.com>
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*/
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#include <linux/device.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/irqdomain.h>
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#include <linux/mfd/twl.h>
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#include "twl-core.h"
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/*
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* TWL4030 IRQ handling has two stages in hardware, and thus in software.
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* The Primary Interrupt Handler (PIH) stage exposes status bits saying
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* which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
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* SIH modules are more traditional IRQ components, which support per-IRQ
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* enable/disable and trigger controls; they do most of the work.
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*
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* These chips are designed to support IRQ handling from two different
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* I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
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* and mask registers in the PIH and SIH modules.
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*
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* We set up IRQs starting at a platform-specified base, always starting
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* with PIH and the SIH for PWR_INT and then usually adding GPIO:
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* base + 0 .. base + 7 PIH
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* base + 8 .. base + 15 SIH for PWR_INT
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* base + 16 .. base + 33 SIH for GPIO
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*/
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#define TWL4030_CORE_NR_IRQS 8
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#define TWL4030_PWR_NR_IRQS 8
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/* PIH register offsets */
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#define REG_PIH_ISR_P1 0x01
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#define REG_PIH_ISR_P2 0x02
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#define REG_PIH_SIR 0x03 /* for testing */
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/* Linux could (eventually) use either IRQ line */
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static int irq_line;
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struct sih {
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char name[8];
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u8 module; /* module id */
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u8 control_offset; /* for SIH_CTRL */
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bool set_cor;
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u8 bits; /* valid in isr/imr */
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u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
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u8 edr_offset;
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u8 bytes_edr; /* bytelen of EDR */
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u8 irq_lines; /* number of supported irq lines */
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/* SIR ignored -- set interrupt, for testing only */
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struct sih_irq_data {
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u8 isr_offset;
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u8 imr_offset;
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} mask[2];
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/* + 2 bytes padding */
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};
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static const struct sih *sih_modules;
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static int nr_sih_modules;
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#define SIH_INITIALIZER(modname, nbits) \
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.module = TWL4030_MODULE_ ## modname, \
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.control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
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.bits = nbits, \
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.bytes_ixr = DIV_ROUND_UP(nbits, 8), \
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.edr_offset = TWL4030_ ## modname ## _EDR, \
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.bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
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.irq_lines = 2, \
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.mask = { { \
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.isr_offset = TWL4030_ ## modname ## _ISR1, \
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.imr_offset = TWL4030_ ## modname ## _IMR1, \
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}, \
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{ \
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.isr_offset = TWL4030_ ## modname ## _ISR2, \
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.imr_offset = TWL4030_ ## modname ## _IMR2, \
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}, },
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/* register naming policies are inconsistent ... */
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#define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
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#define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
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#define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
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/*
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* Order in this table matches order in PIH_ISR. That is,
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* BIT(n) in PIH_ISR is sih_modules[n].
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*/
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/* sih_modules_twl4030 is used both in twl4030 and twl5030 */
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static const struct sih sih_modules_twl4030[6] = {
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[0] = {
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.name = "gpio",
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.module = TWL4030_MODULE_GPIO,
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.control_offset = REG_GPIO_SIH_CTRL,
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.set_cor = true,
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.bits = TWL4030_GPIO_MAX,
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.bytes_ixr = 3,
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/* Note: *all* of these IRQs default to no-trigger */
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.edr_offset = REG_GPIO_EDR1,
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.bytes_edr = 5,
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.irq_lines = 2,
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.mask = { {
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.isr_offset = REG_GPIO_ISR1A,
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.imr_offset = REG_GPIO_IMR1A,
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}, {
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.isr_offset = REG_GPIO_ISR1B,
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.imr_offset = REG_GPIO_IMR1B,
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}, },
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},
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[1] = {
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.name = "keypad",
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.set_cor = true,
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SIH_INITIALIZER(KEYPAD_KEYP, 4)
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},
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[2] = {
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.name = "bci",
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.module = TWL4030_MODULE_INTERRUPTS,
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.control_offset = TWL4030_INTERRUPTS_BCISIHCTRL,
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.set_cor = true,
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.bits = 12,
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.bytes_ixr = 2,
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.edr_offset = TWL4030_INTERRUPTS_BCIEDR1,
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/* Note: most of these IRQs default to no-trigger */
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.bytes_edr = 3,
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.irq_lines = 2,
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.mask = { {
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.isr_offset = TWL4030_INTERRUPTS_BCIISR1A,
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.imr_offset = TWL4030_INTERRUPTS_BCIIMR1A,
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}, {
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.isr_offset = TWL4030_INTERRUPTS_BCIISR1B,
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.imr_offset = TWL4030_INTERRUPTS_BCIIMR1B,
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}, },
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},
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[3] = {
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.name = "madc",
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SIH_INITIALIZER(MADC, 4)
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},
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[4] = {
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/* USB doesn't use the same SIH organization */
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.name = "usb",
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},
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[5] = {
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.name = "power",
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.set_cor = true,
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SIH_INITIALIZER(INT_PWR, 8)
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},
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/* there are no SIH modules #6 or #7 ... */
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};
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static const struct sih sih_modules_twl5031[8] = {
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[0] = {
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.name = "gpio",
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.module = TWL4030_MODULE_GPIO,
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.control_offset = REG_GPIO_SIH_CTRL,
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.set_cor = true,
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.bits = TWL4030_GPIO_MAX,
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.bytes_ixr = 3,
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/* Note: *all* of these IRQs default to no-trigger */
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.edr_offset = REG_GPIO_EDR1,
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.bytes_edr = 5,
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.irq_lines = 2,
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.mask = { {
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.isr_offset = REG_GPIO_ISR1A,
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.imr_offset = REG_GPIO_IMR1A,
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}, {
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.isr_offset = REG_GPIO_ISR1B,
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.imr_offset = REG_GPIO_IMR1B,
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}, },
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},
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[1] = {
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.name = "keypad",
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.set_cor = true,
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SIH_INITIALIZER(KEYPAD_KEYP, 4)
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},
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[2] = {
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.name = "bci",
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.module = TWL5031_MODULE_INTERRUPTS,
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.control_offset = TWL5031_INTERRUPTS_BCISIHCTRL,
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.bits = 7,
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.bytes_ixr = 1,
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.edr_offset = TWL5031_INTERRUPTS_BCIEDR1,
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/* Note: most of these IRQs default to no-trigger */
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.bytes_edr = 2,
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.irq_lines = 2,
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.mask = { {
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.isr_offset = TWL5031_INTERRUPTS_BCIISR1,
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.imr_offset = TWL5031_INTERRUPTS_BCIIMR1,
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}, {
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.isr_offset = TWL5031_INTERRUPTS_BCIISR2,
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.imr_offset = TWL5031_INTERRUPTS_BCIIMR2,
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}, },
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},
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[3] = {
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.name = "madc",
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SIH_INITIALIZER(MADC, 4)
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},
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[4] = {
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/* USB doesn't use the same SIH organization */
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.name = "usb",
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},
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[5] = {
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.name = "power",
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.set_cor = true,
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SIH_INITIALIZER(INT_PWR, 8)
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},
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[6] = {
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/*
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* ECI/DBI doesn't use the same SIH organization.
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* For example, it supports only one interrupt output line.
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* That is, the interrupts are seen on both INT1 and INT2 lines.
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*/
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.name = "eci_dbi",
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.module = TWL5031_MODULE_ACCESSORY,
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.bits = 9,
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.bytes_ixr = 2,
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.irq_lines = 1,
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.mask = { {
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.isr_offset = TWL5031_ACIIDR_LSB,
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.imr_offset = TWL5031_ACIIMR_LSB,
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}, },
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},
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[7] = {
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/* Audio accessory */
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.name = "audio",
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.module = TWL5031_MODULE_ACCESSORY,
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.control_offset = TWL5031_ACCSIHCTRL,
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.bits = 2,
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.bytes_ixr = 1,
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.edr_offset = TWL5031_ACCEDR1,
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/* Note: most of these IRQs default to no-trigger */
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.bytes_edr = 1,
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.irq_lines = 2,
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.mask = { {
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.isr_offset = TWL5031_ACCISR1,
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.imr_offset = TWL5031_ACCIMR1,
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}, {
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.isr_offset = TWL5031_ACCISR2,
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.imr_offset = TWL5031_ACCIMR2,
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}, },
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},
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};
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#undef TWL4030_MODULE_KEYPAD_KEYP
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#undef TWL4030_MODULE_INT_PWR
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#undef TWL4030_INT_PWR_EDR
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/*----------------------------------------------------------------------*/
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static unsigned twl4030_irq_base;
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/*
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* handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
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* This is a chained interrupt, so there is no desc->action method for it.
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* Now we need to query the interrupt controller in the twl4030 to determine
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* which module is generating the interrupt request. However, we can't do i2c
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* transactions in interrupt context, so we must defer that work to a kernel
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* thread. All we do here is acknowledge and mask the interrupt and wakeup
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* the kernel thread.
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*/
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static irqreturn_t handle_twl4030_pih(int irq, void *devid)
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{
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irqreturn_t ret;
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u8 pih_isr;
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ret = twl_i2c_read_u8(TWL_MODULE_PIH, &pih_isr,
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REG_PIH_ISR_P1);
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if (ret) {
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pr_warn("twl4030: I2C error %d reading PIH ISR\n", ret);
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return IRQ_NONE;
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}
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while (pih_isr) {
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unsigned long pending = __ffs(pih_isr);
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unsigned int irq;
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pih_isr &= ~BIT(pending);
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irq = pending + twl4030_irq_base;
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handle_nested_irq(irq);
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}
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return IRQ_HANDLED;
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}
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/*----------------------------------------------------------------------*/
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/*
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* twl4030_init_sih_modules() ... start from a known state where no
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* IRQs will be coming in, and where we can quickly enable them then
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* handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
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*
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* NOTE: we don't touch EDR registers here; they stay with hardware
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* defaults or whatever the last value was. Note that when both EDR
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* bits for an IRQ are clear, that's as if its IMR bit is set...
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*/
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static int twl4030_init_sih_modules(unsigned line)
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{
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const struct sih *sih;
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u8 buf[4];
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int i;
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int status;
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/* line 0 == int1_n signal; line 1 == int2_n signal */
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if (line > 1)
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return -EINVAL;
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irq_line = line;
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/* disable all interrupts on our line */
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memset(buf, 0xff, sizeof(buf));
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sih = sih_modules;
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for (i = 0; i < nr_sih_modules; i++, sih++) {
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/* skip USB -- it's funky */
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if (!sih->bytes_ixr)
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continue;
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/* Not all the SIH modules support multiple interrupt lines */
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if (sih->irq_lines <= line)
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continue;
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status = twl_i2c_write(sih->module, buf,
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sih->mask[line].imr_offset, sih->bytes_ixr);
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if (status < 0)
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pr_err("twl4030: err %d initializing %s %s\n",
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status, sih->name, "IMR");
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/*
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* Maybe disable "exclusive" mode; buffer second pending irq;
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* set Clear-On-Read (COR) bit.
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*
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* NOTE that sometimes COR polarity is documented as being
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* inverted: for MADC, COR=1 means "clear on write".
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* And for PWR_INT it's not documented...
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*/
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if (sih->set_cor) {
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status = twl_i2c_write_u8(sih->module,
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TWL4030_SIH_CTRL_COR_MASK,
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sih->control_offset);
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if (status < 0)
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pr_err("twl4030: err %d initializing %s %s\n",
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status, sih->name, "SIH_CTRL");
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}
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}
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sih = sih_modules;
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for (i = 0; i < nr_sih_modules; i++, sih++) {
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u8 rxbuf[4];
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int j;
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/* skip USB */
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if (!sih->bytes_ixr)
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continue;
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/* Not all the SIH modules support multiple interrupt lines */
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if (sih->irq_lines <= line)
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continue;
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/*
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* Clear pending interrupt status. Either the read was
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* enough, or we need to write those bits. Repeat, in
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* case an IRQ is pending (PENDDIS=0) ... that's not
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* uncommon with PWR_INT.PWRON.
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*/
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for (j = 0; j < 2; j++) {
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status = twl_i2c_read(sih->module, rxbuf,
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sih->mask[line].isr_offset, sih->bytes_ixr);
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if (status < 0)
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pr_warn("twl4030: err %d initializing %s %s\n",
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status, sih->name, "ISR");
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if (!sih->set_cor) {
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status = twl_i2c_write(sih->module, buf,
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sih->mask[line].isr_offset,
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sih->bytes_ixr);
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if (status < 0)
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pr_warn("twl4030: write failed: %d\n",
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status);
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}
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/*
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* else COR=1 means read sufficed.
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* (for most SIH modules...)
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*/
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}
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}
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return 0;
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}
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static inline void activate_irq(int irq)
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{
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irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
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}
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/*----------------------------------------------------------------------*/
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struct sih_agent {
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int irq_base;
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const struct sih *sih;
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u32 imr;
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bool imr_change_pending;
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u32 edge_change;
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struct mutex irq_lock;
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char *irq_name;
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};
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/*----------------------------------------------------------------------*/
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/*
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* All irq_chip methods get issued from code holding irq_desc[irq].lock,
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* which can't perform the underlying I2C operations (because they sleep).
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* So we must hand them off to a thread (workqueue) and cope with asynch
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* completion, potentially including some re-ordering, of these requests.
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*/
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static void twl4030_sih_mask(struct irq_data *data)
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{
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struct sih_agent *agent = irq_data_get_irq_chip_data(data);
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agent->imr |= BIT(data->irq - agent->irq_base);
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agent->imr_change_pending = true;
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}
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static void twl4030_sih_unmask(struct irq_data *data)
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{
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struct sih_agent *agent = irq_data_get_irq_chip_data(data);
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agent->imr &= ~BIT(data->irq - agent->irq_base);
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agent->imr_change_pending = true;
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}
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static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger)
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{
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struct sih_agent *agent = irq_data_get_irq_chip_data(data);
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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return -EINVAL;
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if (irqd_get_trigger_type(data) != trigger)
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agent->edge_change |= BIT(data->irq - agent->irq_base);
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return 0;
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}
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static void twl4030_sih_bus_lock(struct irq_data *data)
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{
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struct sih_agent *agent = irq_data_get_irq_chip_data(data);
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mutex_lock(&agent->irq_lock);
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}
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static void twl4030_sih_bus_sync_unlock(struct irq_data *data)
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{
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struct sih_agent *agent = irq_data_get_irq_chip_data(data);
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const struct sih *sih = agent->sih;
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int status;
|
|
|
|
if (agent->imr_change_pending) {
|
|
union {
|
|
__le32 word;
|
|
u8 bytes[4];
|
|
} imr;
|
|
|
|
/* byte[0] gets overwritten as we write ... */
|
|
imr.word = cpu_to_le32(agent->imr);
|
|
agent->imr_change_pending = false;
|
|
|
|
/* write the whole mask ... simpler than subsetting it */
|
|
status = twl_i2c_write(sih->module, imr.bytes,
|
|
sih->mask[irq_line].imr_offset,
|
|
sih->bytes_ixr);
|
|
if (status)
|
|
pr_err("twl4030: %s, %s --> %d\n", __func__,
|
|
"write", status);
|
|
}
|
|
|
|
if (agent->edge_change) {
|
|
u32 edge_change;
|
|
u8 bytes[6];
|
|
|
|
edge_change = agent->edge_change;
|
|
agent->edge_change = 0;
|
|
|
|
/*
|
|
* Read, reserving first byte for write scratch. Yes, this
|
|
* could be cached for some speedup ... but be careful about
|
|
* any processor on the other IRQ line, EDR registers are
|
|
* shared.
|
|
*/
|
|
status = twl_i2c_read(sih->module, bytes,
|
|
sih->edr_offset, sih->bytes_edr);
|
|
if (status) {
|
|
pr_err("twl4030: %s, %s --> %d\n", __func__,
|
|
"read", status);
|
|
return;
|
|
}
|
|
|
|
/* Modify only the bits we know must change */
|
|
while (edge_change) {
|
|
int i = fls(edge_change) - 1;
|
|
int byte = i >> 2;
|
|
int off = (i & 0x3) * 2;
|
|
unsigned int type;
|
|
|
|
bytes[byte] &= ~(0x03 << off);
|
|
|
|
type = irq_get_trigger_type(i + agent->irq_base);
|
|
if (type & IRQ_TYPE_EDGE_RISING)
|
|
bytes[byte] |= BIT(off + 1);
|
|
if (type & IRQ_TYPE_EDGE_FALLING)
|
|
bytes[byte] |= BIT(off + 0);
|
|
|
|
edge_change &= ~BIT(i);
|
|
}
|
|
|
|
/* Write */
|
|
status = twl_i2c_write(sih->module, bytes,
|
|
sih->edr_offset, sih->bytes_edr);
|
|
if (status)
|
|
pr_err("twl4030: %s, %s --> %d\n", __func__,
|
|
"write", status);
|
|
}
|
|
|
|
mutex_unlock(&agent->irq_lock);
|
|
}
|
|
|
|
static struct irq_chip twl4030_sih_irq_chip = {
|
|
.name = "twl4030",
|
|
.irq_mask = twl4030_sih_mask,
|
|
.irq_unmask = twl4030_sih_unmask,
|
|
.irq_set_type = twl4030_sih_set_type,
|
|
.irq_bus_lock = twl4030_sih_bus_lock,
|
|
.irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock,
|
|
.flags = IRQCHIP_SKIP_SET_WAKE,
|
|
};
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
static inline int sih_read_isr(const struct sih *sih)
|
|
{
|
|
int status;
|
|
union {
|
|
u8 bytes[4];
|
|
__le32 word;
|
|
} isr;
|
|
|
|
/* FIXME need retry-on-error ... */
|
|
|
|
isr.word = 0;
|
|
status = twl_i2c_read(sih->module, isr.bytes,
|
|
sih->mask[irq_line].isr_offset, sih->bytes_ixr);
|
|
|
|
return (status < 0) ? status : le32_to_cpu(isr.word);
|
|
}
|
|
|
|
/*
|
|
* Generic handler for SIH interrupts ... we "know" this is called
|
|
* in task context, with IRQs enabled.
|
|
*/
|
|
static irqreturn_t handle_twl4030_sih(int irq, void *data)
|
|
{
|
|
struct sih_agent *agent = irq_get_handler_data(irq);
|
|
const struct sih *sih = agent->sih;
|
|
int isr;
|
|
|
|
/* reading ISR acks the IRQs, using clear-on-read mode */
|
|
isr = sih_read_isr(sih);
|
|
|
|
if (isr < 0) {
|
|
pr_err("twl4030: %s SIH, read ISR error %d\n",
|
|
sih->name, isr);
|
|
/* REVISIT: recover; eventually mask it all, etc */
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
while (isr) {
|
|
irq = fls(isr);
|
|
irq--;
|
|
isr &= ~BIT(irq);
|
|
|
|
if (irq < sih->bits)
|
|
handle_nested_irq(agent->irq_base + irq);
|
|
else
|
|
pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
|
|
sih->name, irq);
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/* returns the first IRQ used by this SIH bank, or negative errno */
|
|
int twl4030_sih_setup(struct device *dev, int module, int irq_base)
|
|
{
|
|
int sih_mod;
|
|
const struct sih *sih = NULL;
|
|
struct sih_agent *agent;
|
|
int i, irq;
|
|
int status = -EINVAL;
|
|
|
|
/* only support modules with standard clear-on-read for now */
|
|
for (sih_mod = 0, sih = sih_modules; sih_mod < nr_sih_modules;
|
|
sih_mod++, sih++) {
|
|
if (sih->module == module && sih->set_cor) {
|
|
status = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (status < 0) {
|
|
dev_err(dev, "module to setup SIH for not found\n");
|
|
return status;
|
|
}
|
|
|
|
agent = kzalloc(sizeof(*agent), GFP_KERNEL);
|
|
if (!agent)
|
|
return -ENOMEM;
|
|
|
|
agent->irq_base = irq_base;
|
|
agent->sih = sih;
|
|
agent->imr = ~0;
|
|
mutex_init(&agent->irq_lock);
|
|
|
|
for (i = 0; i < sih->bits; i++) {
|
|
irq = irq_base + i;
|
|
|
|
irq_set_chip_data(irq, agent);
|
|
irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip,
|
|
handle_edge_irq);
|
|
irq_set_nested_thread(irq, 1);
|
|
activate_irq(irq);
|
|
}
|
|
|
|
/* replace generic PIH handler (handle_simple_irq) */
|
|
irq = sih_mod + twl4030_irq_base;
|
|
irq_set_handler_data(irq, agent);
|
|
agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name);
|
|
status = request_threaded_irq(irq, NULL, handle_twl4030_sih,
|
|
IRQF_EARLY_RESUME | IRQF_ONESHOT,
|
|
agent->irq_name ?: sih->name, NULL);
|
|
|
|
dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", sih->name,
|
|
irq, irq_base, irq_base + i - 1);
|
|
|
|
return status < 0 ? status : irq_base;
|
|
}
|
|
|
|
/* FIXME need a call to reverse twl4030_sih_setup() ... */
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
/* FIXME pass in which interrupt line we'll use ... */
|
|
#define twl_irq_line 0
|
|
|
|
int twl4030_init_irq(struct device *dev, int irq_num)
|
|
{
|
|
static struct irq_chip twl4030_irq_chip;
|
|
int status, i;
|
|
int irq_base, irq_end, nr_irqs;
|
|
struct device_node *node = dev->of_node;
|
|
|
|
/*
|
|
* TWL core and pwr interrupts must be contiguous because
|
|
* the hwirqs numbers are defined contiguously from 1 to 15.
|
|
* Create only one domain for both.
|
|
*/
|
|
nr_irqs = TWL4030_PWR_NR_IRQS + TWL4030_CORE_NR_IRQS;
|
|
|
|
irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
|
|
if (irq_base < 0) {
|
|
dev_err(dev, "Fail to allocate IRQ descs\n");
|
|
return irq_base;
|
|
}
|
|
|
|
irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
|
|
&irq_domain_simple_ops, NULL);
|
|
|
|
irq_end = irq_base + TWL4030_CORE_NR_IRQS;
|
|
|
|
/*
|
|
* Mask and clear all TWL4030 interrupts since initially we do
|
|
* not have any TWL4030 module interrupt handlers present
|
|
*/
|
|
status = twl4030_init_sih_modules(twl_irq_line);
|
|
if (status < 0)
|
|
return status;
|
|
|
|
twl4030_irq_base = irq_base;
|
|
|
|
/*
|
|
* Install an irq handler for each of the SIH modules;
|
|
* clone dummy irq_chip since PIH can't *do* anything
|
|
*/
|
|
twl4030_irq_chip = dummy_irq_chip;
|
|
twl4030_irq_chip.name = "twl4030";
|
|
|
|
twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack;
|
|
|
|
for (i = irq_base; i < irq_end; i++) {
|
|
irq_set_chip_and_handler(i, &twl4030_irq_chip,
|
|
handle_simple_irq);
|
|
irq_set_nested_thread(i, 1);
|
|
activate_irq(i);
|
|
}
|
|
|
|
dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", "PIH",
|
|
irq_num, irq_base, irq_end);
|
|
|
|
/* ... and the PWR_INT module ... */
|
|
status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end);
|
|
if (status < 0) {
|
|
dev_err(dev, "sih_setup PWR INT --> %d\n", status);
|
|
goto fail;
|
|
}
|
|
|
|
/* install an irq handler to demultiplex the TWL4030 interrupt */
|
|
status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih,
|
|
IRQF_ONESHOT,
|
|
"TWL4030-PIH", NULL);
|
|
if (status < 0) {
|
|
dev_err(dev, "could not claim irq%d: %d\n", irq_num, status);
|
|
goto fail_rqirq;
|
|
}
|
|
enable_irq_wake(irq_num);
|
|
|
|
return irq_base;
|
|
fail_rqirq:
|
|
/* clean up twl4030_sih_setup */
|
|
fail:
|
|
for (i = irq_base; i < irq_end; i++) {
|
|
irq_set_nested_thread(i, 0);
|
|
irq_set_chip_and_handler(i, NULL, NULL);
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
void twl4030_exit_irq(void)
|
|
{
|
|
/* FIXME undo twl_init_irq() */
|
|
if (twl4030_irq_base)
|
|
pr_err("twl4030: can't yet clean up IRQs?\n");
|
|
}
|
|
|
|
int twl4030_init_chip_irq(const char *chip)
|
|
{
|
|
if (!strcmp(chip, "twl5031")) {
|
|
sih_modules = sih_modules_twl5031;
|
|
nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031);
|
|
} else {
|
|
sih_modules = sih_modules_twl4030;
|
|
nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030);
|
|
}
|
|
|
|
return 0;
|
|
}
|