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053b5579da
Use "hisi_pmu" to simplify the parameter list for the hisi_pmu_init() function. Signed-off-by: Junhao He <hejunhao3@huawei.com> Link: https://lore.kernel.org/r/20230119100307.3660-3-hejunhao3@huawei.com Signed-off-by: Will Deacon <will@kernel.org>
585 lines
16 KiB
C
585 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* HiSilicon SoC HHA uncore Hardware event counters support
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*
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* Copyright (C) 2017 HiSilicon Limited
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* Author: Shaokun Zhang <zhangshaokun@hisilicon.com>
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* Anurup M <anurup.m@huawei.com>
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*
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* This code is based on the uncore PMUs like arm-cci and arm-ccn.
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*/
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#include <linux/acpi.h>
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#include <linux/bug.h>
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#include <linux/cpuhotplug.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/list.h>
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#include <linux/smp.h>
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#include "hisi_uncore_pmu.h"
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/* HHA register definition */
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#define HHA_INT_MASK 0x0804
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#define HHA_INT_STATUS 0x0808
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#define HHA_INT_CLEAR 0x080C
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#define HHA_VERSION 0x1cf0
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#define HHA_PERF_CTRL 0x1E00
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#define HHA_EVENT_CTRL 0x1E04
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#define HHA_SRCID_CTRL 0x1E08
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#define HHA_DATSRC_CTRL 0x1BF0
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#define HHA_EVENT_TYPE0 0x1E80
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/*
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* If the HW version only supports a 48-bit counter, then
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* bits [63:48] are reserved, which are Read-As-Zero and
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* Writes-Ignored.
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*/
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#define HHA_CNT0_LOWER 0x1F00
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/* HHA PMU v1 has 16 counters and v2 only has 8 counters */
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#define HHA_V1_NR_COUNTERS 0x10
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#define HHA_V2_NR_COUNTERS 0x8
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#define HHA_PERF_CTRL_EN 0x1
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#define HHA_TRACETAG_EN BIT(31)
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#define HHA_SRCID_EN BIT(2)
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#define HHA_SRCID_CMD_SHIFT 6
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#define HHA_SRCID_MSK_SHIFT 20
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#define HHA_SRCID_CMD GENMASK(16, 6)
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#define HHA_SRCID_MSK GENMASK(30, 20)
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#define HHA_DATSRC_SKT_EN BIT(23)
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#define HHA_EVTYPE_NONE 0xff
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#define HHA_V1_NR_EVENT 0x65
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#define HHA_V2_NR_EVENT 0xCE
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HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_cmd, config1, 10, 0);
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HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_msk, config1, 21, 11);
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HISI_PMU_EVENT_ATTR_EXTRACTOR(tracetag_en, config1, 22, 22);
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HISI_PMU_EVENT_ATTR_EXTRACTOR(datasrc_skt, config1, 23, 23);
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static void hisi_hha_pmu_enable_tracetag(struct perf_event *event)
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{
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struct hisi_pmu *hha_pmu = to_hisi_pmu(event->pmu);
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u32 tt_en = hisi_get_tracetag_en(event);
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if (tt_en) {
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u32 val;
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val = readl(hha_pmu->base + HHA_SRCID_CTRL);
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val |= HHA_TRACETAG_EN;
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writel(val, hha_pmu->base + HHA_SRCID_CTRL);
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}
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}
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static void hisi_hha_pmu_clear_tracetag(struct perf_event *event)
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{
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struct hisi_pmu *hha_pmu = to_hisi_pmu(event->pmu);
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u32 val;
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val = readl(hha_pmu->base + HHA_SRCID_CTRL);
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val &= ~HHA_TRACETAG_EN;
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writel(val, hha_pmu->base + HHA_SRCID_CTRL);
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}
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static void hisi_hha_pmu_config_ds(struct perf_event *event)
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{
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struct hisi_pmu *hha_pmu = to_hisi_pmu(event->pmu);
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u32 ds_skt = hisi_get_datasrc_skt(event);
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if (ds_skt) {
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u32 val;
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val = readl(hha_pmu->base + HHA_DATSRC_CTRL);
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val |= HHA_DATSRC_SKT_EN;
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writel(val, hha_pmu->base + HHA_DATSRC_CTRL);
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}
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}
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static void hisi_hha_pmu_clear_ds(struct perf_event *event)
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{
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struct hisi_pmu *hha_pmu = to_hisi_pmu(event->pmu);
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u32 ds_skt = hisi_get_datasrc_skt(event);
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if (ds_skt) {
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u32 val;
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val = readl(hha_pmu->base + HHA_DATSRC_CTRL);
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val &= ~HHA_DATSRC_SKT_EN;
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writel(val, hha_pmu->base + HHA_DATSRC_CTRL);
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}
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}
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static void hisi_hha_pmu_config_srcid(struct perf_event *event)
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{
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struct hisi_pmu *hha_pmu = to_hisi_pmu(event->pmu);
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u32 cmd = hisi_get_srcid_cmd(event);
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if (cmd) {
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u32 val, msk;
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msk = hisi_get_srcid_msk(event);
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val = readl(hha_pmu->base + HHA_SRCID_CTRL);
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val |= HHA_SRCID_EN | (cmd << HHA_SRCID_CMD_SHIFT) |
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(msk << HHA_SRCID_MSK_SHIFT);
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writel(val, hha_pmu->base + HHA_SRCID_CTRL);
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}
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}
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static void hisi_hha_pmu_disable_srcid(struct perf_event *event)
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{
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struct hisi_pmu *hha_pmu = to_hisi_pmu(event->pmu);
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u32 cmd = hisi_get_srcid_cmd(event);
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if (cmd) {
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u32 val;
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val = readl(hha_pmu->base + HHA_SRCID_CTRL);
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val &= ~(HHA_SRCID_EN | HHA_SRCID_MSK | HHA_SRCID_CMD);
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writel(val, hha_pmu->base + HHA_SRCID_CTRL);
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}
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}
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static void hisi_hha_pmu_enable_filter(struct perf_event *event)
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{
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if (event->attr.config1 != 0x0) {
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hisi_hha_pmu_enable_tracetag(event);
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hisi_hha_pmu_config_ds(event);
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hisi_hha_pmu_config_srcid(event);
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}
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}
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static void hisi_hha_pmu_disable_filter(struct perf_event *event)
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{
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if (event->attr.config1 != 0x0) {
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hisi_hha_pmu_disable_srcid(event);
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hisi_hha_pmu_clear_ds(event);
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hisi_hha_pmu_clear_tracetag(event);
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}
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}
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/*
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* Select the counter register offset using the counter index
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* each counter is 48-bits.
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*/
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static u32 hisi_hha_pmu_get_counter_offset(int cntr_idx)
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{
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return (HHA_CNT0_LOWER + (cntr_idx * 8));
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}
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static u64 hisi_hha_pmu_read_counter(struct hisi_pmu *hha_pmu,
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struct hw_perf_event *hwc)
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{
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/* Read 64 bits and like L3C, top 16 bits are RAZ */
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return readq(hha_pmu->base + hisi_hha_pmu_get_counter_offset(hwc->idx));
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}
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static void hisi_hha_pmu_write_counter(struct hisi_pmu *hha_pmu,
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struct hw_perf_event *hwc, u64 val)
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{
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/* Write 64 bits and like L3C, top 16 bits are WI */
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writeq(val, hha_pmu->base + hisi_hha_pmu_get_counter_offset(hwc->idx));
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}
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static void hisi_hha_pmu_write_evtype(struct hisi_pmu *hha_pmu, int idx,
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u32 type)
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{
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u32 reg, reg_idx, shift, val;
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/*
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* Select the appropriate event select register(HHA_EVENT_TYPEx).
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* There are 4 event select registers for the 16 hardware counters.
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* Event code is 8-bits and for the first 4 hardware counters,
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* HHA_EVENT_TYPE0 is chosen. For the next 4 hardware counters,
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* HHA_EVENT_TYPE1 is chosen and so on.
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*/
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reg = HHA_EVENT_TYPE0 + 4 * (idx / 4);
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reg_idx = idx % 4;
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shift = 8 * reg_idx;
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/* Write event code to HHA_EVENT_TYPEx register */
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val = readl(hha_pmu->base + reg);
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val &= ~(HHA_EVTYPE_NONE << shift);
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val |= (type << shift);
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writel(val, hha_pmu->base + reg);
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}
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static void hisi_hha_pmu_start_counters(struct hisi_pmu *hha_pmu)
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{
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u32 val;
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/*
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* Set perf_enable bit in HHA_PERF_CTRL to start event
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* counting for all enabled counters.
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*/
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val = readl(hha_pmu->base + HHA_PERF_CTRL);
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val |= HHA_PERF_CTRL_EN;
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writel(val, hha_pmu->base + HHA_PERF_CTRL);
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}
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static void hisi_hha_pmu_stop_counters(struct hisi_pmu *hha_pmu)
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{
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u32 val;
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/*
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* Clear perf_enable bit in HHA_PERF_CTRL to stop event
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* counting for all enabled counters.
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*/
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val = readl(hha_pmu->base + HHA_PERF_CTRL);
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val &= ~(HHA_PERF_CTRL_EN);
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writel(val, hha_pmu->base + HHA_PERF_CTRL);
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}
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static void hisi_hha_pmu_enable_counter(struct hisi_pmu *hha_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Enable counter index in HHA_EVENT_CTRL register */
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val = readl(hha_pmu->base + HHA_EVENT_CTRL);
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val |= (1 << hwc->idx);
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writel(val, hha_pmu->base + HHA_EVENT_CTRL);
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}
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static void hisi_hha_pmu_disable_counter(struct hisi_pmu *hha_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Clear counter index in HHA_EVENT_CTRL register */
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val = readl(hha_pmu->base + HHA_EVENT_CTRL);
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val &= ~(1 << hwc->idx);
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writel(val, hha_pmu->base + HHA_EVENT_CTRL);
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}
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static void hisi_hha_pmu_enable_counter_int(struct hisi_pmu *hha_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Write 0 to enable interrupt */
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val = readl(hha_pmu->base + HHA_INT_MASK);
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val &= ~(1 << hwc->idx);
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writel(val, hha_pmu->base + HHA_INT_MASK);
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}
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static void hisi_hha_pmu_disable_counter_int(struct hisi_pmu *hha_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Write 1 to mask interrupt */
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val = readl(hha_pmu->base + HHA_INT_MASK);
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val |= (1 << hwc->idx);
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writel(val, hha_pmu->base + HHA_INT_MASK);
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}
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static u32 hisi_hha_pmu_get_int_status(struct hisi_pmu *hha_pmu)
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{
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return readl(hha_pmu->base + HHA_INT_STATUS);
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}
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static void hisi_hha_pmu_clear_int_status(struct hisi_pmu *hha_pmu, int idx)
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{
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writel(1 << idx, hha_pmu->base + HHA_INT_CLEAR);
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}
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static const struct acpi_device_id hisi_hha_pmu_acpi_match[] = {
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{ "HISI0243", },
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{ "HISI0244", },
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{}
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};
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MODULE_DEVICE_TABLE(acpi, hisi_hha_pmu_acpi_match);
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static int hisi_hha_pmu_init_data(struct platform_device *pdev,
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struct hisi_pmu *hha_pmu)
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{
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unsigned long long id;
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acpi_status status;
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/*
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* Use SCCL_ID and UID to identify the HHA PMU, while
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* SCCL_ID is in MPIDR[aff2].
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*/
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if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
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&hha_pmu->sccl_id)) {
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dev_err(&pdev->dev, "Can not read hha sccl-id!\n");
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return -EINVAL;
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}
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/*
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* Early versions of BIOS support _UID by mistake, so we support
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* both "hisilicon, idx-id" as preference, if available.
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*/
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if (device_property_read_u32(&pdev->dev, "hisilicon,idx-id",
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&hha_pmu->index_id)) {
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status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
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"_UID", NULL, &id);
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if (ACPI_FAILURE(status)) {
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dev_err(&pdev->dev, "Cannot read idx-id!\n");
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return -EINVAL;
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}
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hha_pmu->index_id = id;
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}
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/* HHA PMUs only share the same SCCL */
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hha_pmu->ccl_id = -1;
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hha_pmu->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(hha_pmu->base)) {
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dev_err(&pdev->dev, "ioremap failed for hha_pmu resource\n");
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return PTR_ERR(hha_pmu->base);
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}
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hha_pmu->identifier = readl(hha_pmu->base + HHA_VERSION);
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return 0;
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}
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static struct attribute *hisi_hha_pmu_v1_format_attr[] = {
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HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
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NULL,
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};
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static const struct attribute_group hisi_hha_pmu_v1_format_group = {
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.name = "format",
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.attrs = hisi_hha_pmu_v1_format_attr,
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};
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static struct attribute *hisi_hha_pmu_v2_format_attr[] = {
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HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
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HISI_PMU_FORMAT_ATTR(srcid_cmd, "config1:0-10"),
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HISI_PMU_FORMAT_ATTR(srcid_msk, "config1:11-21"),
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HISI_PMU_FORMAT_ATTR(tracetag_en, "config1:22"),
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HISI_PMU_FORMAT_ATTR(datasrc_skt, "config1:23"),
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NULL
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};
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static const struct attribute_group hisi_hha_pmu_v2_format_group = {
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.name = "format",
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.attrs = hisi_hha_pmu_v2_format_attr,
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};
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static struct attribute *hisi_hha_pmu_v1_events_attr[] = {
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HISI_PMU_EVENT_ATTR(rx_ops_num, 0x00),
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HISI_PMU_EVENT_ATTR(rx_outer, 0x01),
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HISI_PMU_EVENT_ATTR(rx_sccl, 0x02),
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HISI_PMU_EVENT_ATTR(rx_ccix, 0x03),
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HISI_PMU_EVENT_ATTR(rx_wbi, 0x04),
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HISI_PMU_EVENT_ATTR(rx_wbip, 0x05),
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HISI_PMU_EVENT_ATTR(rx_wtistash, 0x11),
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HISI_PMU_EVENT_ATTR(rd_ddr_64b, 0x1c),
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HISI_PMU_EVENT_ATTR(wr_ddr_64b, 0x1d),
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HISI_PMU_EVENT_ATTR(rd_ddr_128b, 0x1e),
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HISI_PMU_EVENT_ATTR(wr_ddr_128b, 0x1f),
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HISI_PMU_EVENT_ATTR(spill_num, 0x20),
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HISI_PMU_EVENT_ATTR(spill_success, 0x21),
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HISI_PMU_EVENT_ATTR(bi_num, 0x23),
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HISI_PMU_EVENT_ATTR(mediated_num, 0x32),
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HISI_PMU_EVENT_ATTR(tx_snp_num, 0x33),
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HISI_PMU_EVENT_ATTR(tx_snp_outer, 0x34),
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HISI_PMU_EVENT_ATTR(tx_snp_ccix, 0x35),
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HISI_PMU_EVENT_ATTR(rx_snprspdata, 0x38),
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HISI_PMU_EVENT_ATTR(rx_snprsp_outer, 0x3c),
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HISI_PMU_EVENT_ATTR(sdir-lookup, 0x40),
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HISI_PMU_EVENT_ATTR(edir-lookup, 0x41),
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HISI_PMU_EVENT_ATTR(sdir-hit, 0x42),
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HISI_PMU_EVENT_ATTR(edir-hit, 0x43),
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HISI_PMU_EVENT_ATTR(sdir-home-migrate, 0x4c),
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HISI_PMU_EVENT_ATTR(edir-home-migrate, 0x4d),
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NULL,
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};
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static const struct attribute_group hisi_hha_pmu_v1_events_group = {
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.name = "events",
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.attrs = hisi_hha_pmu_v1_events_attr,
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};
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static struct attribute *hisi_hha_pmu_v2_events_attr[] = {
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HISI_PMU_EVENT_ATTR(rx_ops_num, 0x00),
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HISI_PMU_EVENT_ATTR(rx_outer, 0x01),
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HISI_PMU_EVENT_ATTR(rx_sccl, 0x02),
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HISI_PMU_EVENT_ATTR(hha_retry, 0x2e),
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HISI_PMU_EVENT_ATTR(cycles, 0x55),
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NULL
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};
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static const struct attribute_group hisi_hha_pmu_v2_events_group = {
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.name = "events",
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.attrs = hisi_hha_pmu_v2_events_attr,
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};
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static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
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static struct attribute *hisi_hha_pmu_cpumask_attrs[] = {
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&dev_attr_cpumask.attr,
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NULL,
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};
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static const struct attribute_group hisi_hha_pmu_cpumask_attr_group = {
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.attrs = hisi_hha_pmu_cpumask_attrs,
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};
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static struct device_attribute hisi_hha_pmu_identifier_attr =
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__ATTR(identifier, 0444, hisi_uncore_pmu_identifier_attr_show, NULL);
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static struct attribute *hisi_hha_pmu_identifier_attrs[] = {
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&hisi_hha_pmu_identifier_attr.attr,
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NULL
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};
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static const struct attribute_group hisi_hha_pmu_identifier_group = {
|
|
.attrs = hisi_hha_pmu_identifier_attrs,
|
|
};
|
|
|
|
static const struct attribute_group *hisi_hha_pmu_v1_attr_groups[] = {
|
|
&hisi_hha_pmu_v1_format_group,
|
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&hisi_hha_pmu_v1_events_group,
|
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&hisi_hha_pmu_cpumask_attr_group,
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&hisi_hha_pmu_identifier_group,
|
|
NULL,
|
|
};
|
|
|
|
static const struct attribute_group *hisi_hha_pmu_v2_attr_groups[] = {
|
|
&hisi_hha_pmu_v2_format_group,
|
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&hisi_hha_pmu_v2_events_group,
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&hisi_hha_pmu_cpumask_attr_group,
|
|
&hisi_hha_pmu_identifier_group,
|
|
NULL
|
|
};
|
|
|
|
static const struct hisi_uncore_ops hisi_uncore_hha_ops = {
|
|
.write_evtype = hisi_hha_pmu_write_evtype,
|
|
.get_event_idx = hisi_uncore_pmu_get_event_idx,
|
|
.start_counters = hisi_hha_pmu_start_counters,
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|
.stop_counters = hisi_hha_pmu_stop_counters,
|
|
.enable_counter = hisi_hha_pmu_enable_counter,
|
|
.disable_counter = hisi_hha_pmu_disable_counter,
|
|
.enable_counter_int = hisi_hha_pmu_enable_counter_int,
|
|
.disable_counter_int = hisi_hha_pmu_disable_counter_int,
|
|
.write_counter = hisi_hha_pmu_write_counter,
|
|
.read_counter = hisi_hha_pmu_read_counter,
|
|
.get_int_status = hisi_hha_pmu_get_int_status,
|
|
.clear_int_status = hisi_hha_pmu_clear_int_status,
|
|
.enable_filter = hisi_hha_pmu_enable_filter,
|
|
.disable_filter = hisi_hha_pmu_disable_filter,
|
|
};
|
|
|
|
static int hisi_hha_pmu_dev_probe(struct platform_device *pdev,
|
|
struct hisi_pmu *hha_pmu)
|
|
{
|
|
int ret;
|
|
|
|
ret = hisi_hha_pmu_init_data(pdev, hha_pmu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = hisi_uncore_pmu_init_irq(hha_pmu, pdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (hha_pmu->identifier >= HISI_PMU_V2) {
|
|
hha_pmu->counter_bits = 64;
|
|
hha_pmu->check_event = HHA_V2_NR_EVENT;
|
|
hha_pmu->pmu_events.attr_groups = hisi_hha_pmu_v2_attr_groups;
|
|
hha_pmu->num_counters = HHA_V2_NR_COUNTERS;
|
|
} else {
|
|
hha_pmu->counter_bits = 48;
|
|
hha_pmu->check_event = HHA_V1_NR_EVENT;
|
|
hha_pmu->pmu_events.attr_groups = hisi_hha_pmu_v1_attr_groups;
|
|
hha_pmu->num_counters = HHA_V1_NR_COUNTERS;
|
|
}
|
|
hha_pmu->ops = &hisi_uncore_hha_ops;
|
|
hha_pmu->dev = &pdev->dev;
|
|
hha_pmu->on_cpu = -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int hisi_hha_pmu_probe(struct platform_device *pdev)
|
|
{
|
|
struct hisi_pmu *hha_pmu;
|
|
char *name;
|
|
int ret;
|
|
|
|
hha_pmu = devm_kzalloc(&pdev->dev, sizeof(*hha_pmu), GFP_KERNEL);
|
|
if (!hha_pmu)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, hha_pmu);
|
|
|
|
ret = hisi_hha_pmu_dev_probe(pdev, hha_pmu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
|
|
&hha_pmu->node);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%u_hha%u",
|
|
hha_pmu->sccl_id, hha_pmu->index_id);
|
|
hisi_pmu_init(hha_pmu, name, THIS_MODULE);
|
|
|
|
ret = perf_pmu_register(&hha_pmu->pmu, name, -1);
|
|
if (ret) {
|
|
dev_err(hha_pmu->dev, "HHA PMU register failed!\n");
|
|
cpuhp_state_remove_instance_nocalls(
|
|
CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE, &hha_pmu->node);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int hisi_hha_pmu_remove(struct platform_device *pdev)
|
|
{
|
|
struct hisi_pmu *hha_pmu = platform_get_drvdata(pdev);
|
|
|
|
perf_pmu_unregister(&hha_pmu->pmu);
|
|
cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
|
|
&hha_pmu->node);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver hisi_hha_pmu_driver = {
|
|
.driver = {
|
|
.name = "hisi_hha_pmu",
|
|
.acpi_match_table = ACPI_PTR(hisi_hha_pmu_acpi_match),
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = hisi_hha_pmu_probe,
|
|
.remove = hisi_hha_pmu_remove,
|
|
};
|
|
|
|
static int __init hisi_hha_pmu_module_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE,
|
|
"AP_PERF_ARM_HISI_HHA_ONLINE",
|
|
hisi_uncore_pmu_online_cpu,
|
|
hisi_uncore_pmu_offline_cpu);
|
|
if (ret) {
|
|
pr_err("HHA PMU: Error setup hotplug, ret = %d;\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = platform_driver_register(&hisi_hha_pmu_driver);
|
|
if (ret)
|
|
cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE);
|
|
|
|
return ret;
|
|
}
|
|
module_init(hisi_hha_pmu_module_init);
|
|
|
|
static void __exit hisi_hha_pmu_module_exit(void)
|
|
{
|
|
platform_driver_unregister(&hisi_hha_pmu_driver);
|
|
cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_HHA_ONLINE);
|
|
}
|
|
module_exit(hisi_hha_pmu_module_exit);
|
|
|
|
MODULE_DESCRIPTION("HiSilicon SoC HHA uncore PMU driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Shaokun Zhang <zhangshaokun@hisilicon.com>");
|
|
MODULE_AUTHOR("Anurup M <anurup.m@huawei.com>");
|