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![Alexandre Belloni](/assets/img/avatar_default.png)
Allow the IRQ type to be passed from the device tree if available as there may be components changing the trigger type of the interrupt between the RTC and the IRQ controller. Link: https://lore.kernel.org/r/20230123200217.1236011-5-alexandre.belloni@bootlin.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
481 lines
13 KiB
C
481 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* An SPI driver for the Philips PCF2123 RTC
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* Copyright 2009 Cyber Switching, Inc.
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*
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* Author: Chris Verges <chrisv@cyberswitching.com>
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* Maintainers: http://www.cyberswitching.com
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*
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* based on the RS5C348 driver in this same directory.
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*
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* Thanks to Christian Pellegrin <chripell@fsfe.org> for
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* the sysfs contributions to this driver.
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*
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* Please note that the CS is active high, so platform data
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* should look something like:
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*
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* static struct spi_board_info ek_spi_devices[] = {
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* ...
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* {
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* .modalias = "rtc-pcf2123",
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* .chip_select = 1,
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* .controller_data = (void *)AT91_PIN_PA10,
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* .max_speed_hz = 1000 * 1000,
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* .mode = SPI_CS_HIGH,
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* .bus_num = 0,
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* },
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* ...
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*};
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*/
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#include <linux/bcd.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/rtc.h>
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#include <linux/spi/spi.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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/* REGISTERS */
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#define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
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#define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
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#define PCF2123_REG_SC (0x02) /* datetime */
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#define PCF2123_REG_MN (0x03)
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#define PCF2123_REG_HR (0x04)
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#define PCF2123_REG_DM (0x05)
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#define PCF2123_REG_DW (0x06)
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#define PCF2123_REG_MO (0x07)
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#define PCF2123_REG_YR (0x08)
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#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
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#define PCF2123_REG_ALRM_HR (0x0a)
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#define PCF2123_REG_ALRM_DM (0x0b)
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#define PCF2123_REG_ALRM_DW (0x0c)
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#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
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#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
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#define PCF2123_REG_CTDWN_TMR (0x0f)
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/* PCF2123_REG_CTRL1 BITS */
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#define CTRL1_CLEAR (0) /* Clear */
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#define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
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#define CTRL1_12_HOUR BIT(2) /* 12 hour time */
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#define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */
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#define CTRL1_STOP BIT(5) /* Stop the clock */
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#define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
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/* PCF2123_REG_CTRL2 BITS */
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#define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
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#define CTRL2_AIE BIT(1) /* Alarm irq enable */
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#define CTRL2_TF BIT(2) /* Countdown timer flag */
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#define CTRL2_AF BIT(3) /* Alarm flag */
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#define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
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#define CTRL2_MSF BIT(5) /* Minute or second irq flag */
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#define CTRL2_SI BIT(6) /* Second irq enable */
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#define CTRL2_MI BIT(7) /* Minute irq enable */
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/* PCF2123_REG_SC BITS */
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#define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
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/* PCF2123_REG_ALRM_XX BITS */
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#define ALRM_DISABLE BIT(7) /* MN, HR, DM, or DW alarm matching */
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/* PCF2123_REG_TMR_CLKOUT BITS */
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#define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
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#define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
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#define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
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#define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
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#define CD_TMR_TE BIT(3) /* Countdown timer enable */
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/* PCF2123_REG_OFFSET BITS */
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#define OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
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#define OFFSET_COARSE BIT(7) /* Coarse mode offset */
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#define OFFSET_STEP (2170) /* Offset step in parts per billion */
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#define OFFSET_MASK GENMASK(6, 0) /* Offset value */
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/* READ/WRITE ADDRESS BITS */
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#define PCF2123_WRITE BIT(4)
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#define PCF2123_READ (BIT(4) | BIT(7))
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static struct spi_driver pcf2123_driver;
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struct pcf2123_data {
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struct rtc_device *rtc;
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struct regmap *map;
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};
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static const struct regmap_config pcf2123_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.read_flag_mask = PCF2123_READ,
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.write_flag_mask = PCF2123_WRITE,
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.max_register = PCF2123_REG_CTDWN_TMR,
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};
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static int pcf2123_read_offset(struct device *dev, long *offset)
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{
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struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
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int ret, val;
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unsigned int reg;
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ret = regmap_read(pcf2123->map, PCF2123_REG_OFFSET, ®);
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if (ret)
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return ret;
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val = sign_extend32((reg & OFFSET_MASK), OFFSET_SIGN_BIT);
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if (reg & OFFSET_COARSE)
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val *= 2;
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*offset = ((long)val) * OFFSET_STEP;
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return 0;
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}
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/*
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* The offset register is a 7 bit signed value with a coarse bit in bit 7.
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* The main difference between the two is normal offset adjusts the first
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* second of n minutes every other hour, with 61, 62 and 63 being shoved
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* into the 60th minute.
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* The coarse adjustment does the same, but every hour.
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* the two overlap, with every even normal offset value corresponding
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* to a coarse offset. Based on this algorithm, it seems that despite the
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* name, coarse offset is a better fit for overlapping values.
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*/
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static int pcf2123_set_offset(struct device *dev, long offset)
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{
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struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
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s8 reg;
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if (offset > OFFSET_STEP * 127)
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reg = 127;
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else if (offset < OFFSET_STEP * -128)
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reg = -128;
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else
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reg = DIV_ROUND_CLOSEST(offset, OFFSET_STEP);
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/* choose fine offset only for odd values in the normal range */
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if (reg & 1 && reg <= 63 && reg >= -64) {
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/* Normal offset. Clear the coarse bit */
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reg &= ~OFFSET_COARSE;
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} else {
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/* Coarse offset. Divide by 2 and set the coarse bit */
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reg >>= 1;
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reg |= OFFSET_COARSE;
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}
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return regmap_write(pcf2123->map, PCF2123_REG_OFFSET, (unsigned int)reg);
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}
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static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
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u8 rxbuf[7];
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int ret;
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ret = regmap_bulk_read(pcf2123->map, PCF2123_REG_SC, rxbuf,
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sizeof(rxbuf));
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if (ret)
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return ret;
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if (rxbuf[0] & OSC_HAS_STOPPED) {
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dev_info(dev, "clock was stopped. Time is not valid\n");
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return -EINVAL;
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}
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tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
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tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
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tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
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tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
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tm->tm_wday = rxbuf[4] & 0x07;
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tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
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tm->tm_year = bcd2bin(rxbuf[6]) + 100;
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dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
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return 0;
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}
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static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
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u8 txbuf[7];
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int ret;
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dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
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/* Stop the counter first */
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ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_STOP);
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if (ret)
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return ret;
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/* Set the new time */
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txbuf[0] = bin2bcd(tm->tm_sec & 0x7F);
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txbuf[1] = bin2bcd(tm->tm_min & 0x7F);
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txbuf[2] = bin2bcd(tm->tm_hour & 0x3F);
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txbuf[3] = bin2bcd(tm->tm_mday & 0x3F);
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txbuf[4] = tm->tm_wday & 0x07;
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txbuf[5] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
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txbuf[6] = bin2bcd(tm->tm_year - 100);
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ret = regmap_bulk_write(pcf2123->map, PCF2123_REG_SC, txbuf,
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sizeof(txbuf));
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if (ret)
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return ret;
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/* Start the counter */
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ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
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if (ret)
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return ret;
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return 0;
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}
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static int pcf2123_rtc_alarm_irq_enable(struct device *dev, unsigned int en)
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{
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struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
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return regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AIE,
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en ? CTRL2_AIE : 0);
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}
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static int pcf2123_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
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{
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struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
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u8 rxbuf[4];
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int ret;
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unsigned int val = 0;
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ret = regmap_bulk_read(pcf2123->map, PCF2123_REG_ALRM_MN, rxbuf,
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sizeof(rxbuf));
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if (ret)
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return ret;
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alm->time.tm_min = bcd2bin(rxbuf[0] & 0x7F);
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alm->time.tm_hour = bcd2bin(rxbuf[1] & 0x3F);
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alm->time.tm_mday = bcd2bin(rxbuf[2] & 0x3F);
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alm->time.tm_wday = bcd2bin(rxbuf[3] & 0x07);
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dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
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ret = regmap_read(pcf2123->map, PCF2123_REG_CTRL2, &val);
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if (ret)
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return ret;
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alm->enabled = !!(val & CTRL2_AIE);
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return 0;
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}
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static int pcf2123_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
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{
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struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
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u8 txbuf[4];
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int ret;
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dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
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/* Disable alarm interrupt */
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ret = regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AIE, 0);
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if (ret)
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return ret;
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/* Ensure alarm flag is clear */
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ret = regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
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if (ret)
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return ret;
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/* Set new alarm */
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txbuf[0] = bin2bcd(alm->time.tm_min & 0x7F);
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txbuf[1] = bin2bcd(alm->time.tm_hour & 0x3F);
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txbuf[2] = bin2bcd(alm->time.tm_mday & 0x3F);
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txbuf[3] = ALRM_DISABLE;
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ret = regmap_bulk_write(pcf2123->map, PCF2123_REG_ALRM_MN, txbuf,
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sizeof(txbuf));
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if (ret)
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return ret;
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return pcf2123_rtc_alarm_irq_enable(dev, alm->enabled);
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}
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static irqreturn_t pcf2123_rtc_irq(int irq, void *dev)
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{
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struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
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unsigned int val = 0;
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int ret = IRQ_NONE;
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rtc_lock(pcf2123->rtc);
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regmap_read(pcf2123->map, PCF2123_REG_CTRL2, &val);
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/* Alarm? */
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if (val & CTRL2_AF) {
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ret = IRQ_HANDLED;
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/* Clear alarm flag */
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regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
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rtc_update_irq(pcf2123->rtc, 1, RTC_IRQF | RTC_AF);
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}
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rtc_unlock(pcf2123->rtc);
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return ret;
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}
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static int pcf2123_reset(struct device *dev)
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{
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struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
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int ret;
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unsigned int val = 0;
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ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
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if (ret)
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return ret;
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/* Stop the counter */
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dev_dbg(dev, "stopping RTC\n");
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ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_STOP);
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if (ret)
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return ret;
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/* See if the counter was actually stopped */
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dev_dbg(dev, "checking for presence of RTC\n");
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ret = regmap_read(pcf2123->map, PCF2123_REG_CTRL1, &val);
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if (ret)
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return ret;
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dev_dbg(dev, "received data from RTC (0x%08X)\n", val);
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if (!(val & CTRL1_STOP))
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return -ENODEV;
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/* Start the counter */
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ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
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if (ret)
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return ret;
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return 0;
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}
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static const struct rtc_class_ops pcf2123_rtc_ops = {
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.read_time = pcf2123_rtc_read_time,
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.set_time = pcf2123_rtc_set_time,
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.read_offset = pcf2123_read_offset,
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.set_offset = pcf2123_set_offset,
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.read_alarm = pcf2123_rtc_read_alarm,
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.set_alarm = pcf2123_rtc_set_alarm,
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.alarm_irq_enable = pcf2123_rtc_alarm_irq_enable,
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};
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static int pcf2123_probe(struct spi_device *spi)
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{
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struct rtc_device *rtc;
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struct rtc_time tm;
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struct pcf2123_data *pcf2123;
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int ret = 0;
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pcf2123 = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_data),
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GFP_KERNEL);
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if (!pcf2123)
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return -ENOMEM;
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dev_set_drvdata(&spi->dev, pcf2123);
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pcf2123->map = devm_regmap_init_spi(spi, &pcf2123_regmap_config);
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if (IS_ERR(pcf2123->map)) {
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dev_err(&spi->dev, "regmap init failed.\n");
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return PTR_ERR(pcf2123->map);
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}
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ret = pcf2123_rtc_read_time(&spi->dev, &tm);
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if (ret < 0) {
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ret = pcf2123_reset(&spi->dev);
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if (ret < 0) {
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dev_err(&spi->dev, "chip not found\n");
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return ret;
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}
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}
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dev_info(&spi->dev, "spiclk %u KHz.\n",
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(spi->max_speed_hz + 500) / 1000);
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/* Finalize the initialization */
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rtc = devm_rtc_allocate_device(&spi->dev);
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if (IS_ERR(rtc))
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return PTR_ERR(rtc);
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pcf2123->rtc = rtc;
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/* Register alarm irq */
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if (spi->irq > 0) {
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unsigned long irqflags = IRQF_TRIGGER_LOW;
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if (dev_fwnode(&spi->dev))
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irqflags = 0;
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ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
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pcf2123_rtc_irq,
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irqflags | IRQF_ONESHOT,
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pcf2123_driver.driver.name, &spi->dev);
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if (!ret)
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device_init_wakeup(&spi->dev, true);
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else
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dev_err(&spi->dev, "could not request irq.\n");
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}
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/* The PCF2123's alarm only has minute accuracy. Must add timer
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* support to this driver to generate interrupts more than once
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* per minute.
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*/
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set_bit(RTC_FEATURE_ALARM_RES_MINUTE, rtc->features);
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clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->features);
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rtc->ops = &pcf2123_rtc_ops;
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rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
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rtc->range_max = RTC_TIMESTAMP_END_2099;
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rtc->set_start_time = true;
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ret = devm_rtc_register_device(rtc);
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if (ret)
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return ret;
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return 0;
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}
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#ifdef CONFIG_OF
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static const struct of_device_id pcf2123_dt_ids[] = {
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{ .compatible = "nxp,pcf2123", },
|
|
{ .compatible = "microcrystal,rv2123", },
|
|
/* Deprecated, do not use */
|
|
{ .compatible = "nxp,rtc-pcf2123", },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
|
|
#endif
|
|
|
|
static const struct spi_device_id pcf2123_spi_ids[] = {
|
|
{ .name = "pcf2123", },
|
|
{ .name = "rv2123", },
|
|
{ .name = "rtc-pcf2123", },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(spi, pcf2123_spi_ids);
|
|
|
|
static struct spi_driver pcf2123_driver = {
|
|
.driver = {
|
|
.name = "rtc-pcf2123",
|
|
.of_match_table = of_match_ptr(pcf2123_dt_ids),
|
|
},
|
|
.probe = pcf2123_probe,
|
|
.id_table = pcf2123_spi_ids,
|
|
};
|
|
|
|
module_spi_driver(pcf2123_driver);
|
|
|
|
MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
|
|
MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
|
|
MODULE_LICENSE("GPL");
|