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![Christophe JAILLET](/assets/img/avatar_default.png)
The devm_clk_get_enabled() helper: - calls devm_clk_get() - calls clk_prepare_enable() and registers what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This simplifies the code, the error handling paths and avoid the need of a dedicated function used with devm_add_action_or_reset(). Based on my test with allyesconfig, this reduces the .o size from: text data bss dec hex filename 12843 4804 64 17711 452f drivers/rtc/rtc-ti-k3.o down to: 12523 4804 64 17391 43ef drivers/rtc/rtc-ti-k3.o Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/601288834ab71c0fddde7eedd8cdb8001254ed7e.1661329498.git.christophe.jaillet@wanadoo.fr Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
662 lines
18 KiB
C
662 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Texas Instruments K3 RTC driver
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*
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* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/sys_soc.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/rtc.h>
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/* Registers */
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#define REG_K3RTC_S_CNT_LSW 0x08
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#define REG_K3RTC_S_CNT_MSW 0x0c
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#define REG_K3RTC_COMP 0x10
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#define REG_K3RTC_ON_OFF_S_CNT_LSW 0x20
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#define REG_K3RTC_ON_OFF_S_CNT_MSW 0x24
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#define REG_K3RTC_SCRATCH0 0x30
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#define REG_K3RTC_SCRATCH7 0x4c
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#define REG_K3RTC_GENERAL_CTL 0x50
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#define REG_K3RTC_IRQSTATUS_RAW_SYS 0x54
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#define REG_K3RTC_IRQSTATUS_SYS 0x58
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#define REG_K3RTC_IRQENABLE_SET_SYS 0x5c
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#define REG_K3RTC_IRQENABLE_CLR_SYS 0x60
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#define REG_K3RTC_SYNCPEND 0x68
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#define REG_K3RTC_KICK0 0x70
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#define REG_K3RTC_KICK1 0x74
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/* Freeze when lsw is read and unfreeze when msw is read */
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#define K3RTC_CNT_FMODE_S_CNT_VALUE (0x2 << 24)
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/* Magic values for lock/unlock */
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#define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b13
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#define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e0
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/* Multiplier for ppb conversions */
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#define K3RTC_PPB_MULT (1000000000LL)
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/* Min and max values supported with 'offset' interface (swapped sign) */
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#define K3RTC_MIN_OFFSET (-277761)
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#define K3RTC_MAX_OFFSET (277778)
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static const struct regmap_config ti_k3_rtc_regmap_config = {
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.name = "peripheral-registers",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = REG_K3RTC_KICK1,
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};
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enum ti_k3_rtc_fields {
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K3RTC_KICK0,
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K3RTC_KICK1,
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K3RTC_S_CNT_LSW,
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K3RTC_S_CNT_MSW,
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K3RTC_O32K_OSC_DEP_EN,
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K3RTC_UNLOCK,
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K3RTC_CNT_FMODE,
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K3RTC_PEND,
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K3RTC_RELOAD_FROM_BBD,
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K3RTC_COMP,
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K3RTC_ALM_S_CNT_LSW,
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K3RTC_ALM_S_CNT_MSW,
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K3RTC_IRQ_STATUS_RAW,
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K3RTC_IRQ_STATUS,
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K3RTC_IRQ_ENABLE_SET,
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K3RTC_IRQ_ENABLE_CLR,
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K3RTC_IRQ_STATUS_ALT,
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K3RTC_IRQ_ENABLE_CLR_ALT,
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K3_RTC_MAX_FIELDS
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};
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static const struct reg_field ti_rtc_reg_fields[] = {
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[K3RTC_KICK0] = REG_FIELD(REG_K3RTC_KICK0, 0, 31),
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[K3RTC_KICK1] = REG_FIELD(REG_K3RTC_KICK1, 0, 31),
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[K3RTC_S_CNT_LSW] = REG_FIELD(REG_K3RTC_S_CNT_LSW, 0, 31),
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[K3RTC_S_CNT_MSW] = REG_FIELD(REG_K3RTC_S_CNT_MSW, 0, 15),
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[K3RTC_O32K_OSC_DEP_EN] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 21, 21),
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[K3RTC_UNLOCK] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 23, 23),
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[K3RTC_CNT_FMODE] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 24, 25),
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[K3RTC_PEND] = REG_FIELD(REG_K3RTC_SYNCPEND, 0, 1),
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[K3RTC_RELOAD_FROM_BBD] = REG_FIELD(REG_K3RTC_SYNCPEND, 31, 31),
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[K3RTC_COMP] = REG_FIELD(REG_K3RTC_COMP, 0, 31),
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/* We use on to off as alarm trigger */
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[K3RTC_ALM_S_CNT_LSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_LSW, 0, 31),
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[K3RTC_ALM_S_CNT_MSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_MSW, 0, 15),
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[K3RTC_IRQ_STATUS_RAW] = REG_FIELD(REG_K3RTC_IRQSTATUS_RAW_SYS, 0, 0),
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[K3RTC_IRQ_STATUS] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 0, 0),
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[K3RTC_IRQ_ENABLE_SET] = REG_FIELD(REG_K3RTC_IRQENABLE_SET_SYS, 0, 0),
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[K3RTC_IRQ_ENABLE_CLR] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 0, 0),
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/* Off to on is alternate */
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[K3RTC_IRQ_STATUS_ALT] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 1, 1),
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[K3RTC_IRQ_ENABLE_CLR_ALT] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 1, 1),
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};
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/**
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* struct ti_k3_rtc - Private data for ti-k3-rtc
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* @irq: IRQ
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* @sync_timeout_us: data sync timeout period in uSec
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* @rate_32k: 32k clock rate in Hz
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* @rtc_dev: rtc device
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* @regmap: rtc mmio regmap
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* @r_fields: rtc register fields
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*/
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struct ti_k3_rtc {
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unsigned int irq;
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u32 sync_timeout_us;
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unsigned long rate_32k;
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struct rtc_device *rtc_dev;
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struct regmap *regmap;
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struct regmap_field *r_fields[K3_RTC_MAX_FIELDS];
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};
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static int k3rtc_field_read(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f)
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{
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int ret;
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int val;
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ret = regmap_field_read(priv->r_fields[f], &val);
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/*
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* We shouldn't be seeing regmap fail on us for mmio reads
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* This is possible if clock context fails, but that isn't the case for us
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*/
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if (WARN_ON_ONCE(ret))
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return ret;
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return val;
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}
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static void k3rtc_field_write(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f, u32 val)
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{
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regmap_field_write(priv->r_fields[f], val);
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}
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/**
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* k3rtc_fence - Ensure a register sync took place between the two domains
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* @priv: pointer to priv data
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*
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* Return: 0 if the sync took place, else returns -ETIMEDOUT
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*/
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static int k3rtc_fence(struct ti_k3_rtc *priv)
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{
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int ret;
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ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_PEND], ret,
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!ret, 2, priv->sync_timeout_us);
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return ret;
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}
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static inline int k3rtc_check_unlocked(struct ti_k3_rtc *priv)
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{
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int ret;
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ret = k3rtc_field_read(priv, K3RTC_UNLOCK);
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if (ret < 0)
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return ret;
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return (ret) ? 0 : 1;
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}
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static int k3rtc_unlock_rtc(struct ti_k3_rtc *priv)
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{
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int ret;
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ret = k3rtc_check_unlocked(priv);
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if (!ret)
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return ret;
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k3rtc_field_write(priv, K3RTC_KICK0, K3RTC_KICK0_UNLOCK_VALUE);
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k3rtc_field_write(priv, K3RTC_KICK1, K3RTC_KICK1_UNLOCK_VALUE);
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/* Skip fence since we are going to check the unlock bit as fence */
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ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_UNLOCK], ret,
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ret, 2, priv->sync_timeout_us);
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return ret;
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}
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/*
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* This is the list of SoCs affected by TI's i2327 errata causing the RTC
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* state-machine to break if not unlocked fast enough during boot. These
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* SoCs must have the bootloader unlock this device very early in the
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* boot-flow before we (Linux) can use this device.
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*/
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static const struct soc_device_attribute has_erratum_i2327[] = {
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{ .family = "AM62X", .revision = "SR1.0" },
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{ /* sentinel */ }
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};
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static int k3rtc_configure(struct device *dev)
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{
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int ret;
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struct ti_k3_rtc *priv = dev_get_drvdata(dev);
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/*
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* HWBUG: The compare state machine is broken if the RTC module
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* is NOT unlocked in under one second of boot - which is pretty long
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* time from the perspective of Linux driver (module load, u-boot
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* shell all can take much longer than this.
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*
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* In such occurrence, it is assumed that the RTC module is unusable
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*/
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if (soc_device_match(has_erratum_i2327)) {
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ret = k3rtc_check_unlocked(priv);
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/* If there is an error OR if we are locked, return error */
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if (ret) {
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dev_err(dev,
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HW_ERR "Erratum i2327 unlock QUIRK! Cannot operate!!\n");
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return -EFAULT;
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}
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} else {
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/* May need to explicitly unlock first time */
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ret = k3rtc_unlock_rtc(priv);
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if (ret) {
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dev_err(dev, "Failed to unlock(%d)!\n", ret);
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return ret;
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}
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}
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/* Enable Shadow register sync on 32k clock boundary */
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k3rtc_field_write(priv, K3RTC_O32K_OSC_DEP_EN, 0x1);
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/*
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* Wait at least clock sync time before proceeding further programming.
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* This ensures that the 32k based sync is active.
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*/
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usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 5);
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/* We need to ensure fence here to make sure sync here */
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ret = k3rtc_fence(priv);
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if (ret) {
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dev_err(dev,
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"Failed fence osc_dep enable(%d) - is 32k clk working?!\n", ret);
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return ret;
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}
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/*
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* FMODE setting: Reading lower seconds will freeze value on higher
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* seconds. This also implies that we must *ALWAYS* read lower seconds
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* prior to reading higher seconds
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*/
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k3rtc_field_write(priv, K3RTC_CNT_FMODE, K3RTC_CNT_FMODE_S_CNT_VALUE);
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/* Clear any spurious IRQ sources if any */
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k3rtc_field_write(priv, K3RTC_IRQ_STATUS_ALT, 0x1);
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k3rtc_field_write(priv, K3RTC_IRQ_STATUS, 0x1);
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/* Disable all IRQs */
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k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR_ALT, 0x1);
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k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR, 0x1);
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/* And.. Let us Sync the writes in */
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return k3rtc_fence(priv);
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}
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static int ti_k3_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct ti_k3_rtc *priv = dev_get_drvdata(dev);
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u32 seconds_lo, seconds_hi;
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seconds_lo = k3rtc_field_read(priv, K3RTC_S_CNT_LSW);
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seconds_hi = k3rtc_field_read(priv, K3RTC_S_CNT_MSW);
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rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, tm);
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return 0;
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}
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static int ti_k3_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct ti_k3_rtc *priv = dev_get_drvdata(dev);
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time64_t seconds;
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seconds = rtc_tm_to_time64(tm);
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/*
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* Read operation on LSW will freeze the RTC, so to update
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* the time, we cannot use field operations. Just write since the
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* reserved bits are ignored.
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*/
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regmap_write(priv->regmap, REG_K3RTC_S_CNT_LSW, seconds);
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regmap_write(priv->regmap, REG_K3RTC_S_CNT_MSW, seconds >> 32);
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return k3rtc_fence(priv);
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}
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static int ti_k3_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
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{
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struct ti_k3_rtc *priv = dev_get_drvdata(dev);
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u32 reg;
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u32 offset = enabled ? K3RTC_IRQ_ENABLE_SET : K3RTC_IRQ_ENABLE_CLR;
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reg = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET);
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if ((enabled && reg) || (!enabled && !reg))
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return 0;
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k3rtc_field_write(priv, offset, 0x1);
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/*
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* Ensure the write sync is through - NOTE: it should be OK to have
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* ISR to fire as we are checking sync (which should be done in a 32k
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* cycle or so).
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*/
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return k3rtc_fence(priv);
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}
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static int ti_k3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct ti_k3_rtc *priv = dev_get_drvdata(dev);
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u32 seconds_lo, seconds_hi;
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seconds_lo = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_LSW);
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seconds_hi = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_MSW);
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rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, &alarm->time);
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alarm->enabled = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET);
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return 0;
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}
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static int ti_k3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct ti_k3_rtc *priv = dev_get_drvdata(dev);
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time64_t seconds;
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int ret;
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seconds = rtc_tm_to_time64(&alarm->time);
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k3rtc_field_write(priv, K3RTC_ALM_S_CNT_LSW, seconds);
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k3rtc_field_write(priv, K3RTC_ALM_S_CNT_MSW, (seconds >> 32));
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/* Make sure the alarm time is synced in */
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ret = k3rtc_fence(priv);
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if (ret) {
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dev_err(dev, "Failed to fence(%d)! Potential config issue?\n", ret);
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return ret;
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}
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/* Alarm IRQ enable will do a sync */
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return ti_k3_rtc_alarm_irq_enable(dev, alarm->enabled);
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}
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static int ti_k3_rtc_read_offset(struct device *dev, long *offset)
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{
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struct ti_k3_rtc *priv = dev_get_drvdata(dev);
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u32 ticks_per_hr = priv->rate_32k * 3600;
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int comp;
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s64 tmp;
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comp = k3rtc_field_read(priv, K3RTC_COMP);
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/* Convert from RTC calibration register format to ppb format */
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tmp = comp * (s64)K3RTC_PPB_MULT;
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if (tmp < 0)
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tmp -= ticks_per_hr / 2LL;
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else
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tmp += ticks_per_hr / 2LL;
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tmp = div_s64(tmp, ticks_per_hr);
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/* Offset value operates in negative way, so swap sign */
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*offset = (long)-tmp;
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return 0;
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}
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static int ti_k3_rtc_set_offset(struct device *dev, long offset)
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{
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struct ti_k3_rtc *priv = dev_get_drvdata(dev);
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u32 ticks_per_hr = priv->rate_32k * 3600;
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int comp;
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s64 tmp;
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/* Make sure offset value is within supported range */
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if (offset < K3RTC_MIN_OFFSET || offset > K3RTC_MAX_OFFSET)
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return -ERANGE;
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/* Convert from ppb format to RTC calibration register format */
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tmp = offset * (s64)ticks_per_hr;
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if (tmp < 0)
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tmp -= K3RTC_PPB_MULT / 2LL;
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else
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tmp += K3RTC_PPB_MULT / 2LL;
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tmp = div_s64(tmp, K3RTC_PPB_MULT);
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/* Offset value operates in negative way, so swap sign */
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comp = (int)-tmp;
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k3rtc_field_write(priv, K3RTC_COMP, comp);
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return k3rtc_fence(priv);
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}
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static irqreturn_t ti_k3_rtc_interrupt(s32 irq, void *dev_id)
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{
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struct device *dev = dev_id;
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struct ti_k3_rtc *priv = dev_get_drvdata(dev);
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u32 reg;
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int ret;
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/*
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* IRQ assertion can be very fast, however, the IRQ Status clear
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* de-assert depends on 32k clock edge in the 32k domain
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* If we clear the status prior to the first 32k clock edge,
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* the status bit is cleared, but the IRQ stays re-asserted.
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*
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* To prevent this condition, we need to wait for clock sync time.
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* We can either do that by polling the 32k observability signal for
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* a toggle OR we could just sleep and let the processor do other
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* stuff.
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*/
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usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 2);
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/* Lets make sure that this is a valid interrupt */
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reg = k3rtc_field_read(priv, K3RTC_IRQ_STATUS);
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if (!reg) {
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u32 raw = k3rtc_field_read(priv, K3RTC_IRQ_STATUS_RAW);
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dev_err(dev,
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HW_ERR
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"Erratum i2327/IRQ trig: status: 0x%08x / 0x%08x\n", reg, raw);
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return IRQ_NONE;
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}
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/*
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* Write 1 to clear status reg
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* We cannot use a field operation here due to a potential race between
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* 32k domain and vbus domain.
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*/
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regmap_write(priv->regmap, REG_K3RTC_IRQSTATUS_SYS, 0x1);
|
|
|
|
/* Sync the write in */
|
|
ret = k3rtc_fence(priv);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to fence irq status clr(%d)!\n", ret);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
/*
|
|
* Force the 32k status to be reloaded back in to ensure status is
|
|
* reflected back correctly.
|
|
*/
|
|
k3rtc_field_write(priv, K3RTC_RELOAD_FROM_BBD, 0x1);
|
|
|
|
/* Ensure the write sync is through */
|
|
ret = k3rtc_fence(priv);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to fence reload from bbd(%d)!\n", ret);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
/* Now we ensure that the status bit is cleared */
|
|
ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_IRQ_STATUS],
|
|
ret, !ret, 2, priv->sync_timeout_us);
|
|
if (ret) {
|
|
dev_err(dev, "Time out waiting for status clear\n");
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
/* Notify RTC core on event */
|
|
rtc_update_irq(priv->rtc_dev, 1, RTC_IRQF | RTC_AF);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static const struct rtc_class_ops ti_k3_rtc_ops = {
|
|
.read_time = ti_k3_rtc_read_time,
|
|
.set_time = ti_k3_rtc_set_time,
|
|
.read_alarm = ti_k3_rtc_read_alarm,
|
|
.set_alarm = ti_k3_rtc_set_alarm,
|
|
.read_offset = ti_k3_rtc_read_offset,
|
|
.set_offset = ti_k3_rtc_set_offset,
|
|
.alarm_irq_enable = ti_k3_rtc_alarm_irq_enable,
|
|
};
|
|
|
|
static int ti_k3_rtc_scratch_read(void *priv_data, unsigned int offset,
|
|
void *val, size_t bytes)
|
|
{
|
|
struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data;
|
|
|
|
return regmap_bulk_read(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4);
|
|
}
|
|
|
|
static int ti_k3_rtc_scratch_write(void *priv_data, unsigned int offset,
|
|
void *val, size_t bytes)
|
|
{
|
|
struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data;
|
|
int ret;
|
|
|
|
ret = regmap_bulk_write(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return k3rtc_fence(priv);
|
|
}
|
|
|
|
static struct nvmem_config ti_k3_rtc_nvmem_config = {
|
|
.name = "ti_k3_rtc_scratch",
|
|
.word_size = 4,
|
|
.stride = 4,
|
|
.size = REG_K3RTC_SCRATCH7 - REG_K3RTC_SCRATCH0 + 4,
|
|
.reg_read = ti_k3_rtc_scratch_read,
|
|
.reg_write = ti_k3_rtc_scratch_write,
|
|
};
|
|
|
|
static int k3rtc_get_32kclk(struct device *dev, struct ti_k3_rtc *priv)
|
|
{
|
|
struct clk *clk;
|
|
|
|
clk = devm_clk_get_enabled(dev, "osc32k");
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
priv->rate_32k = clk_get_rate(clk);
|
|
|
|
/* Make sure we are exact 32k clock. Else, try to compensate delay */
|
|
if (priv->rate_32k != 32768)
|
|
dev_warn(dev, "Clock rate %ld is not 32768! Could misbehave!\n",
|
|
priv->rate_32k);
|
|
|
|
/*
|
|
* Sync timeout should be two 32k clk sync cycles = ~61uS. We double
|
|
* it to comprehend intermediate bus segment and cpu frequency
|
|
* deltas
|
|
*/
|
|
priv->sync_timeout_us = (u32)(DIV_ROUND_UP_ULL(1000000, priv->rate_32k) * 4);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int k3rtc_get_vbusclk(struct device *dev, struct ti_k3_rtc *priv)
|
|
{
|
|
struct clk *clk;
|
|
|
|
/* Note: VBUS isn't a context clock, it is needed for hardware operation */
|
|
clk = devm_clk_get_enabled(dev, "vbus");
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ti_k3_rtc_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct ti_k3_rtc *priv;
|
|
void __iomem *rtc_base;
|
|
int ret;
|
|
|
|
priv = devm_kzalloc(dev, sizeof(struct ti_k3_rtc), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
rtc_base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(rtc_base))
|
|
return PTR_ERR(rtc_base);
|
|
|
|
priv->regmap = devm_regmap_init_mmio(dev, rtc_base, &ti_k3_rtc_regmap_config);
|
|
if (IS_ERR(priv->regmap))
|
|
return PTR_ERR(priv->regmap);
|
|
|
|
ret = devm_regmap_field_bulk_alloc(dev, priv->regmap, priv->r_fields,
|
|
ti_rtc_reg_fields, K3_RTC_MAX_FIELDS);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = k3rtc_get_32kclk(dev, priv);
|
|
if (ret)
|
|
return ret;
|
|
ret = k3rtc_get_vbusclk(dev, priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = platform_get_irq(pdev, 0);
|
|
if (ret < 0)
|
|
return ret;
|
|
priv->irq = (unsigned int)ret;
|
|
|
|
priv->rtc_dev = devm_rtc_allocate_device(dev);
|
|
if (IS_ERR(priv->rtc_dev))
|
|
return PTR_ERR(priv->rtc_dev);
|
|
|
|
priv->rtc_dev->ops = &ti_k3_rtc_ops;
|
|
priv->rtc_dev->range_max = (1ULL << 48) - 1; /* 48Bit seconds */
|
|
ti_k3_rtc_nvmem_config.priv = priv;
|
|
|
|
ret = devm_request_threaded_irq(dev, priv->irq, NULL,
|
|
ti_k3_rtc_interrupt,
|
|
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
|
|
dev_name(dev), dev);
|
|
if (ret) {
|
|
dev_err(dev, "Could not request IRQ: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
ret = k3rtc_configure(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (device_property_present(dev, "wakeup-source"))
|
|
device_init_wakeup(dev, true);
|
|
else
|
|
device_set_wakeup_capable(dev, true);
|
|
|
|
ret = devm_rtc_register_device(priv->rtc_dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return devm_rtc_nvmem_register(priv->rtc_dev, &ti_k3_rtc_nvmem_config);
|
|
}
|
|
|
|
static const struct of_device_id ti_k3_rtc_of_match_table[] = {
|
|
{.compatible = "ti,am62-rtc" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, ti_k3_rtc_of_match_table);
|
|
|
|
static int __maybe_unused ti_k3_rtc_suspend(struct device *dev)
|
|
{
|
|
struct ti_k3_rtc *priv = dev_get_drvdata(dev);
|
|
|
|
if (device_may_wakeup(dev))
|
|
enable_irq_wake(priv->irq);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused ti_k3_rtc_resume(struct device *dev)
|
|
{
|
|
struct ti_k3_rtc *priv = dev_get_drvdata(dev);
|
|
|
|
if (device_may_wakeup(dev))
|
|
disable_irq_wake(priv->irq);
|
|
return 0;
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(ti_k3_rtc_pm_ops, ti_k3_rtc_suspend, ti_k3_rtc_resume);
|
|
|
|
static struct platform_driver ti_k3_rtc_driver = {
|
|
.probe = ti_k3_rtc_probe,
|
|
.driver = {
|
|
.name = "rtc-ti-k3",
|
|
.of_match_table = ti_k3_rtc_of_match_table,
|
|
.pm = &ti_k3_rtc_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(ti_k3_rtc_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("TI K3 RTC driver");
|
|
MODULE_AUTHOR("Nishanth Menon");
|