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![Mark Brown](/assets/img/avatar_default.png)
-----BEGIN PGP SIGNATURE----- iQFSBAABCAA8FiEEq68RxlopcLEwq+PEeb4+QwBBGIYFAmNoPiAeHHRvcnZhbGRz QGxpbnV4LWZvdW5kYXRpb24ub3JnAAoJEHm+PkMAQRiGPmcH/2dl4Zu+ofzwziH4 MxIHeSdL62tFEtD+643hTArXLR/8YeZkt17q0vaQa0WQFC09vtYepdvAuiQIGrDm 69hXY20BIARz1bwqmGuP+gNhjFeuHVy5B9qIKV7z0HoO3Guf2BoAG14LEEBsc5SO RrZSVDRlGHnstMBx4zplWDNXOxehumwoPInFyKC8SqDg464BCeo/ErJbzwMXPdBw RPUuDh3m9iwN6BhjlbM9UhtNEbakVKw+LaTO5eYtiPValyJ40ws/wQ/SrDc/k9YA 1E1gFlUMgPwNz0uVBEO+NcRRsQHiBqrEyLDpvg5RkE2xnOJwMrm9LDY6RqwJD/w1 4UKcuAs= =ls46 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmOBFIEACgkQJNaLcl1U h9A4zAgAgVnP6727ptBIpTE55chOrOPyeVI0bE1xAZ3jyBEfqCFk9yb7wmr9NZY4 tJkuRlBlDGFVvpYavk18m8ZbwaedGqYfRqxmWSFdq19dmbSXn6DdZglrtf19zN2S eNEFSbp/CAjxZAGAdoErf3VjFOHyEt8sm4K6443BbkvKhObKAR5Np2tlEURV2ezJ UAJZXcc+Muu273nH5aaXpKyagL/kupeUns5kcJ73sK3qozxvjrEh8vHhRHx+CQAH qmEqe8dovBWxZUXr7rYDia3xVxCeZGjIQIRsJX/9oA3YuU9entNZx3QeGlMRvue8 wTlhLVYhO+WlB2AfYtOAPNyJAizttA== =CYxU -----END PGP SIGNATURE----- Merge tag 'v6.1-rc4' into spi-6.2 Linux 6.1-rc4 which should get my CI working on RPi3s again.
1216 lines
32 KiB
C
1216 lines
32 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* ASPEED FMC/SPI Memory Controller Driver
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*
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* Copyright (c) 2015-2022, IBM Corporation.
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* Copyright (c) 2020, ASPEED Corporation.
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*/
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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#define DEVICE_NAME "spi-aspeed-smc"
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/* Type setting Register */
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#define CONFIG_REG 0x0
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#define CONFIG_TYPE_SPI 0x2
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/* CE Control Register */
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#define CE_CTRL_REG 0x4
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/* CEx Control Register */
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#define CE0_CTRL_REG 0x10
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#define CTRL_IO_MODE_MASK GENMASK(30, 28)
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#define CTRL_IO_SINGLE_DATA 0x0
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#define CTRL_IO_DUAL_DATA BIT(29)
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#define CTRL_IO_QUAD_DATA BIT(30)
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#define CTRL_COMMAND_SHIFT 16
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#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
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#define CTRL_IO_DUMMY_SET(dummy) \
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(((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
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#define CTRL_FREQ_SEL_SHIFT 8
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#define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT)
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#define CTRL_CE_STOP_ACTIVE BIT(2)
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#define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
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#define CTRL_IO_MODE_NORMAL 0x0
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#define CTRL_IO_MODE_READ 0x1
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#define CTRL_IO_MODE_WRITE 0x2
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#define CTRL_IO_MODE_USER 0x3
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#define CTRL_IO_CMD_MASK 0xf0ff40c3
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/* CEx Address Decoding Range Register */
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#define CE0_SEGMENT_ADDR_REG 0x30
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/* CEx Read timing compensation register */
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#define CE0_TIMING_COMPENSATION_REG 0x94
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enum aspeed_spi_ctl_reg_value {
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ASPEED_SPI_BASE,
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ASPEED_SPI_READ,
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ASPEED_SPI_WRITE,
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ASPEED_SPI_MAX,
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};
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struct aspeed_spi;
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struct aspeed_spi_chip {
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struct aspeed_spi *aspi;
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u32 cs;
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void __iomem *ctl;
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void __iomem *ahb_base;
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u32 ahb_window_size;
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u32 ctl_val[ASPEED_SPI_MAX];
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u32 clk_freq;
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};
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struct aspeed_spi_data {
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u32 ctl0;
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u32 max_cs;
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bool hastype;
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u32 mode_bits;
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u32 we0;
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u32 timing;
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u32 hclk_mask;
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u32 hdiv_max;
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u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
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u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
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u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
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int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv,
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const u8 *golden_buf, u8 *test_buf);
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};
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#define ASPEED_SPI_MAX_NUM_CS 5
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struct aspeed_spi {
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const struct aspeed_spi_data *data;
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void __iomem *regs;
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void __iomem *ahb_base;
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u32 ahb_base_phy;
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u32 ahb_window_size;
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struct device *dev;
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struct clk *clk;
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u32 clk_freq;
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struct aspeed_spi_chip chips[ASPEED_SPI_MAX_NUM_CS];
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};
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static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op)
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{
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switch (op->data.buswidth) {
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case 1:
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return CTRL_IO_SINGLE_DATA;
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case 2:
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return CTRL_IO_DUAL_DATA;
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case 4:
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return CTRL_IO_QUAD_DATA;
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default:
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return CTRL_IO_SINGLE_DATA;
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}
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}
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static void aspeed_spi_set_io_mode(struct aspeed_spi_chip *chip, u32 io_mode)
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{
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u32 ctl;
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if (io_mode > 0) {
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ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK;
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ctl |= io_mode;
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writel(ctl, chip->ctl);
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}
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}
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static void aspeed_spi_start_user(struct aspeed_spi_chip *chip)
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{
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u32 ctl = chip->ctl_val[ASPEED_SPI_BASE];
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ctl |= CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
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writel(ctl, chip->ctl);
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ctl &= ~CTRL_CE_STOP_ACTIVE;
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writel(ctl, chip->ctl);
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}
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static void aspeed_spi_stop_user(struct aspeed_spi_chip *chip)
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{
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u32 ctl = chip->ctl_val[ASPEED_SPI_READ] |
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CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
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writel(ctl, chip->ctl);
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/* Restore defaults */
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writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
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}
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static int aspeed_spi_read_from_ahb(void *buf, void __iomem *src, size_t len)
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{
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size_t offset = 0;
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if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) &&
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IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
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ioread32_rep(src, buf, len >> 2);
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offset = len & ~0x3;
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len -= offset;
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}
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ioread8_rep(src, (u8 *)buf + offset, len);
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return 0;
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}
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static int aspeed_spi_write_to_ahb(void __iomem *dst, const void *buf, size_t len)
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{
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size_t offset = 0;
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if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) &&
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IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
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iowrite32_rep(dst, buf, len >> 2);
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offset = len & ~0x3;
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len -= offset;
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}
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iowrite8_rep(dst, (const u8 *)buf + offset, len);
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return 0;
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}
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static int aspeed_spi_send_cmd_addr(struct aspeed_spi_chip *chip, u8 addr_nbytes,
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u64 offset, u32 opcode)
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{
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__be32 temp;
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u32 cmdaddr;
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switch (addr_nbytes) {
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case 3:
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cmdaddr = offset & 0xFFFFFF;
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cmdaddr |= opcode << 24;
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temp = cpu_to_be32(cmdaddr);
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aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
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break;
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case 4:
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temp = cpu_to_be32(offset);
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aspeed_spi_write_to_ahb(chip->ahb_base, &opcode, 1);
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aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
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break;
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default:
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WARN_ONCE(1, "Unexpected address width %u", addr_nbytes);
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int aspeed_spi_read_reg(struct aspeed_spi_chip *chip,
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const struct spi_mem_op *op)
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{
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aspeed_spi_start_user(chip);
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aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
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aspeed_spi_read_from_ahb(op->data.buf.in,
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chip->ahb_base, op->data.nbytes);
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aspeed_spi_stop_user(chip);
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return 0;
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}
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static int aspeed_spi_write_reg(struct aspeed_spi_chip *chip,
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const struct spi_mem_op *op)
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{
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aspeed_spi_start_user(chip);
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aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
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aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out,
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op->data.nbytes);
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aspeed_spi_stop_user(chip);
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return 0;
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}
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static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip,
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const struct spi_mem_op *op,
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u64 offset, size_t len, void *buf)
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{
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int io_mode = aspeed_spi_get_io_mode(op);
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u8 dummy = 0xFF;
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int i;
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int ret;
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aspeed_spi_start_user(chip);
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ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode);
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if (ret < 0)
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return ret;
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if (op->dummy.buswidth && op->dummy.nbytes) {
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for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++)
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aspeed_spi_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy));
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}
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aspeed_spi_set_io_mode(chip, io_mode);
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aspeed_spi_read_from_ahb(buf, chip->ahb_base, len);
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aspeed_spi_stop_user(chip);
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return 0;
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}
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static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
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const struct spi_mem_op *op)
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{
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int ret;
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aspeed_spi_start_user(chip);
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ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);
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if (ret < 0)
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return ret;
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aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);
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aspeed_spi_stop_user(chip);
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return 0;
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}
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/* support for 1-1-1, 1-1-2 or 1-1-4 */
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static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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if (op->cmd.buswidth > 1)
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return false;
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if (op->addr.nbytes != 0) {
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if (op->addr.buswidth > 1)
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return false;
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if (op->addr.nbytes < 3 || op->addr.nbytes > 4)
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return false;
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}
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if (op->dummy.nbytes != 0) {
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if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7)
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return false;
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}
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if (op->data.nbytes != 0 && op->data.buswidth > 4)
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return false;
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return spi_mem_default_supports_op(mem, op);
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}
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static const struct aspeed_spi_data ast2400_spi_data;
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static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
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struct aspeed_spi_chip *chip = &aspi->chips[mem->spi->chip_select];
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u32 addr_mode, addr_mode_backup;
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u32 ctl_val;
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int ret = 0;
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dev_dbg(aspi->dev,
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"CE%d %s OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x len:%#x",
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chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
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op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
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op->dummy.buswidth, op->data.buswidth,
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op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
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addr_mode = readl(aspi->regs + CE_CTRL_REG);
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addr_mode_backup = addr_mode;
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ctl_val = chip->ctl_val[ASPEED_SPI_BASE];
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ctl_val &= ~CTRL_IO_CMD_MASK;
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ctl_val |= op->cmd.opcode << CTRL_COMMAND_SHIFT;
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/* 4BYTE address mode */
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if (op->addr.nbytes) {
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if (op->addr.nbytes == 4)
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addr_mode |= (0x11 << chip->cs);
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else
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addr_mode &= ~(0x11 << chip->cs);
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if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
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ctl_val |= CTRL_IO_ADDRESS_4B;
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}
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if (op->dummy.nbytes)
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ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
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if (op->data.nbytes)
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ctl_val |= aspeed_spi_get_io_mode(op);
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if (op->data.dir == SPI_MEM_DATA_OUT)
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ctl_val |= CTRL_IO_MODE_WRITE;
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else
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ctl_val |= CTRL_IO_MODE_READ;
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if (addr_mode != addr_mode_backup)
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writel(addr_mode, aspi->regs + CE_CTRL_REG);
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writel(ctl_val, chip->ctl);
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if (op->data.dir == SPI_MEM_DATA_IN) {
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if (!op->addr.nbytes)
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ret = aspeed_spi_read_reg(chip, op);
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else
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ret = aspeed_spi_read_user(chip, op, op->addr.val,
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op->data.nbytes, op->data.buf.in);
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} else {
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if (!op->addr.nbytes)
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ret = aspeed_spi_write_reg(chip, op);
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else
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ret = aspeed_spi_write_user(chip, op);
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}
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/* Restore defaults */
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if (addr_mode != addr_mode_backup)
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writel(addr_mode_backup, aspi->regs + CE_CTRL_REG);
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writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
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return ret;
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}
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static int aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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int ret;
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ret = do_aspeed_spi_exec_op(mem, op);
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if (ret)
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dev_err(&mem->spi->dev, "operation failed: %d\n", ret);
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return ret;
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}
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static const char *aspeed_spi_get_name(struct spi_mem *mem)
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{
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struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
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struct device *dev = aspi->dev;
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return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
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}
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struct aspeed_spi_window {
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u32 cs;
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u32 offset;
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u32 size;
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};
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static void aspeed_spi_get_windows(struct aspeed_spi *aspi,
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struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS])
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{
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const struct aspeed_spi_data *data = aspi->data;
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u32 reg_val;
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u32 cs;
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for (cs = 0; cs < aspi->data->max_cs; cs++) {
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reg_val = readl(aspi->regs + CE0_SEGMENT_ADDR_REG + cs * 4);
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windows[cs].cs = cs;
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windows[cs].size = data->segment_end(aspi, reg_val) -
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data->segment_start(aspi, reg_val);
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windows[cs].offset = data->segment_start(aspi, reg_val) - aspi->ahb_base_phy;
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dev_vdbg(aspi->dev, "CE%d offset=0x%.8x size=0x%x\n", cs,
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windows[cs].offset, windows[cs].size);
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}
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}
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/*
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* On the AST2600, some CE windows are closed by default at reset but
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* U-Boot should open all.
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*/
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static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
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{
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struct aspeed_spi *aspi = chip->aspi;
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struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
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struct aspeed_spi_window *win = &windows[chip->cs];
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/* No segment registers for the AST2400 SPI controller */
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if (aspi->data == &ast2400_spi_data) {
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win->offset = 0;
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win->size = aspi->ahb_window_size;
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} else {
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aspeed_spi_get_windows(aspi, windows);
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}
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chip->ahb_base = aspi->ahb_base + win->offset;
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chip->ahb_window_size = win->size;
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dev_dbg(aspi->dev, "CE%d default window [ 0x%.8x - 0x%.8x ] %dMB",
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|
chip->cs, aspi->ahb_base_phy + win->offset,
|
|
aspi->ahb_base_phy + win->offset + win->size - 1,
|
|
win->size >> 20);
|
|
|
|
return chip->ahb_window_size ? 0 : -1;
|
|
}
|
|
|
|
static int aspeed_spi_set_window(struct aspeed_spi *aspi,
|
|
const struct aspeed_spi_window *win)
|
|
{
|
|
u32 start = aspi->ahb_base_phy + win->offset;
|
|
u32 end = start + win->size;
|
|
void __iomem *seg_reg = aspi->regs + CE0_SEGMENT_ADDR_REG + win->cs * 4;
|
|
u32 seg_val_backup = readl(seg_reg);
|
|
u32 seg_val = aspi->data->segment_reg(aspi, start, end);
|
|
|
|
if (seg_val == seg_val_backup)
|
|
return 0;
|
|
|
|
writel(seg_val, seg_reg);
|
|
|
|
/*
|
|
* Restore initial value if something goes wrong else we could
|
|
* loose access to the chip.
|
|
*/
|
|
if (seg_val != readl(seg_reg)) {
|
|
dev_err(aspi->dev, "CE%d invalid window [ 0x%.8x - 0x%.8x ] %dMB",
|
|
win->cs, start, end - 1, win->size >> 20);
|
|
writel(seg_val_backup, seg_reg);
|
|
return -EIO;
|
|
}
|
|
|
|
if (win->size)
|
|
dev_dbg(aspi->dev, "CE%d new window [ 0x%.8x - 0x%.8x ] %dMB",
|
|
win->cs, start, end - 1, win->size >> 20);
|
|
else
|
|
dev_dbg(aspi->dev, "CE%d window closed", win->cs);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Yet to be done when possible :
|
|
* - Align mappings on flash size (we don't have the info)
|
|
* - ioremap each window, not strictly necessary since the overall window
|
|
* is correct.
|
|
*/
|
|
static const struct aspeed_spi_data ast2500_spi_data;
|
|
static const struct aspeed_spi_data ast2600_spi_data;
|
|
static const struct aspeed_spi_data ast2600_fmc_data;
|
|
|
|
static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
|
|
u32 local_offset, u32 size)
|
|
{
|
|
struct aspeed_spi *aspi = chip->aspi;
|
|
struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
|
|
struct aspeed_spi_window *win = &windows[chip->cs];
|
|
int ret;
|
|
|
|
/* No segment registers for the AST2400 SPI controller */
|
|
if (aspi->data == &ast2400_spi_data)
|
|
return 0;
|
|
|
|
/*
|
|
* Due to an HW issue on the AST2500 SPI controller, the CE0
|
|
* window size should be smaller than the maximum 128MB.
|
|
*/
|
|
if (aspi->data == &ast2500_spi_data && chip->cs == 0 && size == SZ_128M) {
|
|
size = 120 << 20;
|
|
dev_info(aspi->dev, "CE%d window resized to %dMB (AST2500 HW quirk)",
|
|
chip->cs, size >> 20);
|
|
}
|
|
|
|
/*
|
|
* The decoding size of AST2600 SPI controller should set at
|
|
* least 2MB.
|
|
*/
|
|
if ((aspi->data == &ast2600_spi_data || aspi->data == &ast2600_fmc_data) &&
|
|
size < SZ_2M) {
|
|
size = SZ_2M;
|
|
dev_info(aspi->dev, "CE%d window resized to %dMB (AST2600 Decoding)",
|
|
chip->cs, size >> 20);
|
|
}
|
|
|
|
aspeed_spi_get_windows(aspi, windows);
|
|
|
|
/* Adjust this chip window */
|
|
win->offset += local_offset;
|
|
win->size = size;
|
|
|
|
if (win->offset + win->size > aspi->ahb_window_size) {
|
|
win->size = aspi->ahb_window_size - win->offset;
|
|
dev_warn(aspi->dev, "CE%d window resized to %dMB", chip->cs, win->size >> 20);
|
|
}
|
|
|
|
ret = aspeed_spi_set_window(aspi, win);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Update chip mapping info */
|
|
chip->ahb_base = aspi->ahb_base + win->offset;
|
|
chip->ahb_window_size = win->size;
|
|
|
|
/*
|
|
* Also adjust next chip window to make sure that it does not
|
|
* overlap with the current window.
|
|
*/
|
|
if (chip->cs < aspi->data->max_cs - 1) {
|
|
struct aspeed_spi_window *next = &windows[chip->cs + 1];
|
|
|
|
/* Change offset and size to keep the same end address */
|
|
if ((next->offset + next->size) > (win->offset + win->size))
|
|
next->size = (next->offset + next->size) - (win->offset + win->size);
|
|
else
|
|
next->size = 0;
|
|
next->offset = win->offset + win->size;
|
|
|
|
aspeed_spi_set_window(aspi, next);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
|
|
|
|
static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
|
|
{
|
|
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
|
|
struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
|
|
struct spi_mem_op *op = &desc->info.op_tmpl;
|
|
u32 ctl_val;
|
|
int ret = 0;
|
|
|
|
dev_dbg(aspi->dev,
|
|
"CE%d %s dirmap [ 0x%.8llx - 0x%.8llx ] OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x\n",
|
|
chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
|
|
desc->info.offset, desc->info.offset + desc->info.length,
|
|
op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
|
|
op->dummy.buswidth, op->data.buswidth,
|
|
op->addr.nbytes, op->dummy.nbytes);
|
|
|
|
chip->clk_freq = desc->mem->spi->max_speed_hz;
|
|
|
|
/* Only for reads */
|
|
if (op->data.dir != SPI_MEM_DATA_IN)
|
|
return -EOPNOTSUPP;
|
|
|
|
aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length);
|
|
|
|
if (desc->info.length > chip->ahb_window_size)
|
|
dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
|
|
chip->cs, chip->ahb_window_size >> 20);
|
|
|
|
/* Define the default IO read settings */
|
|
ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
|
|
ctl_val |= aspeed_spi_get_io_mode(op) |
|
|
op->cmd.opcode << CTRL_COMMAND_SHIFT |
|
|
CTRL_IO_MODE_READ;
|
|
|
|
if (op->dummy.nbytes)
|
|
ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
|
|
|
|
/* Tune 4BYTE address mode */
|
|
if (op->addr.nbytes) {
|
|
u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
|
|
|
|
if (op->addr.nbytes == 4)
|
|
addr_mode |= (0x11 << chip->cs);
|
|
else
|
|
addr_mode &= ~(0x11 << chip->cs);
|
|
writel(addr_mode, aspi->regs + CE_CTRL_REG);
|
|
|
|
/* AST2400 SPI controller sets 4BYTE address mode in
|
|
* CE0 Control Register
|
|
*/
|
|
if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
|
|
ctl_val |= CTRL_IO_ADDRESS_4B;
|
|
}
|
|
|
|
/* READ mode is the controller default setting */
|
|
chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
|
|
writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
|
|
|
|
ret = aspeed_spi_do_calibration(chip);
|
|
|
|
dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
|
|
chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
|
|
u64 offset, size_t len, void *buf)
|
|
{
|
|
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
|
|
struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
|
|
|
|
/* Switch to USER command mode if mapping window is too small */
|
|
if (chip->ahb_window_size < offset + len) {
|
|
int ret;
|
|
|
|
ret = aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
|
|
if (ret < 0)
|
|
return ret;
|
|
} else {
|
|
memcpy_fromio(buf, chip->ahb_base + offset, len);
|
|
}
|
|
|
|
return len;
|
|
}
|
|
|
|
static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
|
|
.supports_op = aspeed_spi_supports_op,
|
|
.exec_op = aspeed_spi_exec_op,
|
|
.get_name = aspeed_spi_get_name,
|
|
.dirmap_create = aspeed_spi_dirmap_create,
|
|
.dirmap_read = aspeed_spi_dirmap_read,
|
|
};
|
|
|
|
static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = readl(aspi->regs + CONFIG_REG);
|
|
reg &= ~(0x3 << (cs * 2));
|
|
reg |= type << (cs * 2);
|
|
writel(reg, aspi->regs + CONFIG_REG);
|
|
}
|
|
|
|
static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable)
|
|
{
|
|
u32 we_bit = BIT(aspi->data->we0 + cs);
|
|
u32 reg = readl(aspi->regs + CONFIG_REG);
|
|
|
|
if (enable)
|
|
reg |= we_bit;
|
|
else
|
|
reg &= ~we_bit;
|
|
writel(reg, aspi->regs + CONFIG_REG);
|
|
}
|
|
|
|
static int aspeed_spi_setup(struct spi_device *spi)
|
|
{
|
|
struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
|
|
const struct aspeed_spi_data *data = aspi->data;
|
|
unsigned int cs = spi->chip_select;
|
|
struct aspeed_spi_chip *chip = &aspi->chips[cs];
|
|
|
|
chip->aspi = aspi;
|
|
chip->cs = cs;
|
|
chip->ctl = aspi->regs + data->ctl0 + cs * 4;
|
|
|
|
/* The driver only supports SPI type flash */
|
|
if (data->hastype)
|
|
aspeed_spi_chip_set_type(aspi, cs, CONFIG_TYPE_SPI);
|
|
|
|
if (aspeed_spi_chip_set_default_window(chip) < 0) {
|
|
dev_warn(aspi->dev, "CE%d window invalid", cs);
|
|
return -EINVAL;
|
|
}
|
|
|
|
aspeed_spi_chip_enable(aspi, cs, true);
|
|
|
|
chip->ctl_val[ASPEED_SPI_BASE] = CTRL_CE_STOP_ACTIVE | CTRL_IO_MODE_USER;
|
|
|
|
dev_dbg(aspi->dev, "CE%d setup done\n", cs);
|
|
return 0;
|
|
}
|
|
|
|
static void aspeed_spi_cleanup(struct spi_device *spi)
|
|
{
|
|
struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
|
|
unsigned int cs = spi->chip_select;
|
|
|
|
aspeed_spi_chip_enable(aspi, cs, false);
|
|
|
|
dev_dbg(aspi->dev, "CE%d cleanup done\n", cs);
|
|
}
|
|
|
|
static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable)
|
|
{
|
|
int cs;
|
|
|
|
for (cs = 0; cs < aspi->data->max_cs; cs++)
|
|
aspeed_spi_chip_enable(aspi, cs, enable);
|
|
}
|
|
|
|
static int aspeed_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
const struct aspeed_spi_data *data;
|
|
struct spi_controller *ctlr;
|
|
struct aspeed_spi *aspi;
|
|
struct resource *res;
|
|
int ret;
|
|
|
|
data = of_device_get_match_data(&pdev->dev);
|
|
if (!data)
|
|
return -ENODEV;
|
|
|
|
ctlr = devm_spi_alloc_master(dev, sizeof(*aspi));
|
|
if (!ctlr)
|
|
return -ENOMEM;
|
|
|
|
aspi = spi_controller_get_devdata(ctlr);
|
|
platform_set_drvdata(pdev, aspi);
|
|
aspi->data = data;
|
|
aspi->dev = dev;
|
|
|
|
aspi->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(aspi->regs))
|
|
return PTR_ERR(aspi->regs);
|
|
|
|
aspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
|
|
if (IS_ERR(aspi->ahb_base)) {
|
|
dev_err(dev, "missing AHB mapping window\n");
|
|
return PTR_ERR(aspi->ahb_base);
|
|
}
|
|
|
|
aspi->ahb_window_size = resource_size(res);
|
|
aspi->ahb_base_phy = res->start;
|
|
|
|
aspi->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(aspi->clk)) {
|
|
dev_err(dev, "missing clock\n");
|
|
return PTR_ERR(aspi->clk);
|
|
}
|
|
|
|
aspi->clk_freq = clk_get_rate(aspi->clk);
|
|
if (!aspi->clk_freq) {
|
|
dev_err(dev, "invalid clock\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = clk_prepare_enable(aspi->clk);
|
|
if (ret) {
|
|
dev_err(dev, "can not enable the clock\n");
|
|
return ret;
|
|
}
|
|
|
|
/* IRQ is for DMA, which the driver doesn't support yet */
|
|
|
|
ctlr->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | data->mode_bits;
|
|
ctlr->bus_num = pdev->id;
|
|
ctlr->mem_ops = &aspeed_spi_mem_ops;
|
|
ctlr->setup = aspeed_spi_setup;
|
|
ctlr->cleanup = aspeed_spi_cleanup;
|
|
ctlr->num_chipselect = data->max_cs;
|
|
ctlr->dev.of_node = dev->of_node;
|
|
|
|
ret = devm_spi_register_controller(dev, ctlr);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "spi_register_controller failed\n");
|
|
goto disable_clk;
|
|
}
|
|
return 0;
|
|
|
|
disable_clk:
|
|
clk_disable_unprepare(aspi->clk);
|
|
return ret;
|
|
}
|
|
|
|
static int aspeed_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct aspeed_spi *aspi = platform_get_drvdata(pdev);
|
|
|
|
aspeed_spi_enable(aspi, false);
|
|
clk_disable_unprepare(aspi->clk);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* AHB mappings
|
|
*/
|
|
|
|
/*
|
|
* The Segment Registers of the AST2400 and AST2500 use a 8MB unit.
|
|
* The address range is encoded with absolute addresses in the overall
|
|
* mapping window.
|
|
*/
|
|
static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg)
|
|
{
|
|
return ((reg >> 16) & 0xFF) << 23;
|
|
}
|
|
|
|
static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg)
|
|
{
|
|
return ((reg >> 24) & 0xFF) << 23;
|
|
}
|
|
|
|
static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 end)
|
|
{
|
|
return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24);
|
|
}
|
|
|
|
/*
|
|
* The Segment Registers of the AST2600 use a 1MB unit. The address
|
|
* range is encoded with offsets in the overall mapping window.
|
|
*/
|
|
|
|
#define AST2600_SEG_ADDR_MASK 0x0ff00000
|
|
|
|
static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi,
|
|
u32 reg)
|
|
{
|
|
u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
|
|
|
|
return aspi->ahb_base_phy + start_offset;
|
|
}
|
|
|
|
static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi,
|
|
u32 reg)
|
|
{
|
|
u32 end_offset = reg & AST2600_SEG_ADDR_MASK;
|
|
|
|
/* segment is disabled */
|
|
if (!end_offset)
|
|
return aspi->ahb_base_phy;
|
|
|
|
return aspi->ahb_base_phy + end_offset + 0x100000;
|
|
}
|
|
|
|
static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
|
|
u32 start, u32 end)
|
|
{
|
|
/* disable zero size segments */
|
|
if (start == end)
|
|
return 0;
|
|
|
|
return ((start & AST2600_SEG_ADDR_MASK) >> 16) |
|
|
((end - 1) & AST2600_SEG_ADDR_MASK);
|
|
}
|
|
|
|
/*
|
|
* Read timing compensation sequences
|
|
*/
|
|
|
|
#define CALIBRATE_BUF_SIZE SZ_16K
|
|
|
|
static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip,
|
|
const u8 *golden_buf, u8 *test_buf)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < 10; i++) {
|
|
memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
|
|
if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) {
|
|
#if defined(VERBOSE_DEBUG)
|
|
print_hex_dump_bytes(DEVICE_NAME " fail: ", DUMP_PREFIX_NONE,
|
|
test_buf, 0x100);
|
|
#endif
|
|
return false;
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
#define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8))
|
|
|
|
/*
|
|
* The timing register is shared by all devices. Only update for CE0.
|
|
*/
|
|
static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
|
|
const u8 *golden_buf, u8 *test_buf)
|
|
{
|
|
struct aspeed_spi *aspi = chip->aspi;
|
|
const struct aspeed_spi_data *data = aspi->data;
|
|
int i;
|
|
int good_pass = -1, pass_count = 0;
|
|
u32 shift = (hdiv - 1) << 2;
|
|
u32 mask = ~(0xfu << shift);
|
|
u32 fread_timing_val = 0;
|
|
|
|
/* Try HCLK delay 0..5, each one with/without delay and look for a
|
|
* good pair.
|
|
*/
|
|
for (i = 0; i < 12; i++) {
|
|
bool pass;
|
|
|
|
if (chip->cs == 0) {
|
|
fread_timing_val &= mask;
|
|
fread_timing_val |= FREAD_TPASS(i) << shift;
|
|
writel(fread_timing_val, aspi->regs + data->timing);
|
|
}
|
|
pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
|
|
dev_dbg(aspi->dev,
|
|
" * [%08x] %d HCLK delay, %dns DI delay : %s",
|
|
fread_timing_val, i / 2, (i & 1) ? 0 : 4,
|
|
pass ? "PASS" : "FAIL");
|
|
if (pass) {
|
|
pass_count++;
|
|
if (pass_count == 3) {
|
|
good_pass = i - 1;
|
|
break;
|
|
}
|
|
} else {
|
|
pass_count = 0;
|
|
}
|
|
}
|
|
|
|
/* No good setting for this frequency */
|
|
if (good_pass < 0)
|
|
return -1;
|
|
|
|
/* We have at least one pass of margin, let's use first pass */
|
|
if (chip->cs == 0) {
|
|
fread_timing_val &= mask;
|
|
fread_timing_val |= FREAD_TPASS(good_pass) << shift;
|
|
writel(fread_timing_val, aspi->regs + data->timing);
|
|
}
|
|
dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]",
|
|
good_pass, fread_timing_val);
|
|
return 0;
|
|
}
|
|
|
|
static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size)
|
|
{
|
|
const u32 *tb32 = (const u32 *)test_buf;
|
|
u32 i, cnt = 0;
|
|
|
|
/* We check if we have enough words that are neither all 0
|
|
* nor all 1's so the calibration can be considered valid.
|
|
*
|
|
* I use an arbitrary threshold for now of 64
|
|
*/
|
|
size >>= 2;
|
|
for (i = 0; i < size; i++) {
|
|
if (tb32[i] != 0 && tb32[i] != 0xffffffff)
|
|
cnt++;
|
|
}
|
|
return cnt >= 64;
|
|
}
|
|
|
|
static const u32 aspeed_spi_hclk_divs[] = {
|
|
0xf, /* HCLK */
|
|
0x7, /* HCLK/2 */
|
|
0xe, /* HCLK/3 */
|
|
0x6, /* HCLK/4 */
|
|
0xd, /* HCLK/5 */
|
|
};
|
|
|
|
#define ASPEED_SPI_HCLK_DIV(i) \
|
|
(aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT)
|
|
|
|
static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip)
|
|
{
|
|
struct aspeed_spi *aspi = chip->aspi;
|
|
const struct aspeed_spi_data *data = aspi->data;
|
|
u32 ahb_freq = aspi->clk_freq;
|
|
u32 max_freq = chip->clk_freq;
|
|
u32 ctl_val;
|
|
u8 *golden_buf = NULL;
|
|
u8 *test_buf = NULL;
|
|
int i, rc, best_div = -1;
|
|
|
|
dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
|
|
ahb_freq / 1000000);
|
|
|
|
/*
|
|
* use the related low frequency to get check calibration data
|
|
* and get golden data.
|
|
*/
|
|
ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask;
|
|
writel(ctl_val, chip->ctl);
|
|
|
|
test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL);
|
|
if (!test_buf)
|
|
return -ENOMEM;
|
|
|
|
golden_buf = test_buf + CALIBRATE_BUF_SIZE;
|
|
|
|
memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
|
|
if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {
|
|
dev_info(aspi->dev, "Calibration area too uniform, using low speed");
|
|
goto no_calib;
|
|
}
|
|
|
|
#if defined(VERBOSE_DEBUG)
|
|
print_hex_dump_bytes(DEVICE_NAME " good: ", DUMP_PREFIX_NONE,
|
|
golden_buf, 0x100);
|
|
#endif
|
|
|
|
/* Now we iterate the HCLK dividers until we find our breaking point */
|
|
for (i = ARRAY_SIZE(aspeed_spi_hclk_divs); i > data->hdiv_max - 1; i--) {
|
|
u32 tv, freq;
|
|
|
|
freq = ahb_freq / i;
|
|
if (freq > max_freq)
|
|
continue;
|
|
|
|
/* Set the timing */
|
|
tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i);
|
|
writel(tv, chip->ctl);
|
|
dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv);
|
|
rc = data->calibrate(chip, i, golden_buf, test_buf);
|
|
if (rc == 0)
|
|
best_div = i;
|
|
}
|
|
|
|
/* Nothing found ? */
|
|
if (best_div < 0) {
|
|
dev_warn(aspi->dev, "No good frequency, using dumb slow");
|
|
} else {
|
|
dev_dbg(aspi->dev, "Found good read timings at HCLK/%d", best_div);
|
|
|
|
/* Record the freq */
|
|
for (i = 0; i < ASPEED_SPI_MAX; i++)
|
|
chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) |
|
|
ASPEED_SPI_HCLK_DIV(best_div);
|
|
}
|
|
|
|
no_calib:
|
|
writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
|
|
kfree(test_buf);
|
|
return 0;
|
|
}
|
|
|
|
#define TIMING_DELAY_DI BIT(3)
|
|
#define TIMING_DELAY_HCYCLE_MAX 5
|
|
#define TIMING_REG_AST2600(chip) \
|
|
((chip)->aspi->regs + (chip)->aspi->data->timing + \
|
|
(chip)->cs * 4)
|
|
|
|
static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
|
|
const u8 *golden_buf, u8 *test_buf)
|
|
{
|
|
struct aspeed_spi *aspi = chip->aspi;
|
|
int hcycle;
|
|
u32 shift = (hdiv - 2) << 3;
|
|
u32 mask = ~(0xfu << shift);
|
|
u32 fread_timing_val = 0;
|
|
|
|
for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) {
|
|
int delay_ns;
|
|
bool pass = false;
|
|
|
|
fread_timing_val &= mask;
|
|
fread_timing_val |= hcycle << shift;
|
|
|
|
/* no DI input delay first */
|
|
writel(fread_timing_val, TIMING_REG_AST2600(chip));
|
|
pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
|
|
dev_dbg(aspi->dev,
|
|
" * [%08x] %d HCLK delay, DI delay none : %s",
|
|
fread_timing_val, hcycle, pass ? "PASS" : "FAIL");
|
|
if (pass)
|
|
return 0;
|
|
|
|
/* Add DI input delays */
|
|
fread_timing_val &= mask;
|
|
fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift;
|
|
|
|
for (delay_ns = 0; delay_ns < 0x10; delay_ns++) {
|
|
fread_timing_val &= ~(0xf << (4 + shift));
|
|
fread_timing_val |= delay_ns << (4 + shift);
|
|
|
|
writel(fread_timing_val, TIMING_REG_AST2600(chip));
|
|
pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
|
|
dev_dbg(aspi->dev,
|
|
" * [%08x] %d HCLK delay, DI delay %d.%dns : %s",
|
|
fread_timing_val, hcycle, (delay_ns + 1) / 2,
|
|
(delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL");
|
|
/*
|
|
* TODO: This is optimistic. We should look
|
|
* for a working interval and save the middle
|
|
* value in the read timing register.
|
|
*/
|
|
if (pass)
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/* No good setting for this frequency */
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Platform definitions
|
|
*/
|
|
static const struct aspeed_spi_data ast2400_fmc_data = {
|
|
.max_cs = 5,
|
|
.hastype = true,
|
|
.we0 = 16,
|
|
.ctl0 = CE0_CTRL_REG,
|
|
.timing = CE0_TIMING_COMPENSATION_REG,
|
|
.hclk_mask = 0xfffff0ff,
|
|
.hdiv_max = 1,
|
|
.calibrate = aspeed_spi_calibrate,
|
|
.segment_start = aspeed_spi_segment_start,
|
|
.segment_end = aspeed_spi_segment_end,
|
|
.segment_reg = aspeed_spi_segment_reg,
|
|
};
|
|
|
|
static const struct aspeed_spi_data ast2400_spi_data = {
|
|
.max_cs = 1,
|
|
.hastype = false,
|
|
.we0 = 0,
|
|
.ctl0 = 0x04,
|
|
.timing = 0x14,
|
|
.hclk_mask = 0xfffff0ff,
|
|
.hdiv_max = 1,
|
|
.calibrate = aspeed_spi_calibrate,
|
|
/* No segment registers */
|
|
};
|
|
|
|
static const struct aspeed_spi_data ast2500_fmc_data = {
|
|
.max_cs = 3,
|
|
.hastype = true,
|
|
.we0 = 16,
|
|
.ctl0 = CE0_CTRL_REG,
|
|
.timing = CE0_TIMING_COMPENSATION_REG,
|
|
.hclk_mask = 0xffffd0ff,
|
|
.hdiv_max = 1,
|
|
.calibrate = aspeed_spi_calibrate,
|
|
.segment_start = aspeed_spi_segment_start,
|
|
.segment_end = aspeed_spi_segment_end,
|
|
.segment_reg = aspeed_spi_segment_reg,
|
|
};
|
|
|
|
static const struct aspeed_spi_data ast2500_spi_data = {
|
|
.max_cs = 2,
|
|
.hastype = false,
|
|
.we0 = 16,
|
|
.ctl0 = CE0_CTRL_REG,
|
|
.timing = CE0_TIMING_COMPENSATION_REG,
|
|
.hclk_mask = 0xffffd0ff,
|
|
.hdiv_max = 1,
|
|
.calibrate = aspeed_spi_calibrate,
|
|
.segment_start = aspeed_spi_segment_start,
|
|
.segment_end = aspeed_spi_segment_end,
|
|
.segment_reg = aspeed_spi_segment_reg,
|
|
};
|
|
|
|
static const struct aspeed_spi_data ast2600_fmc_data = {
|
|
.max_cs = 3,
|
|
.hastype = false,
|
|
.mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
|
|
.we0 = 16,
|
|
.ctl0 = CE0_CTRL_REG,
|
|
.timing = CE0_TIMING_COMPENSATION_REG,
|
|
.hclk_mask = 0xf0fff0ff,
|
|
.hdiv_max = 2,
|
|
.calibrate = aspeed_spi_ast2600_calibrate,
|
|
.segment_start = aspeed_spi_segment_ast2600_start,
|
|
.segment_end = aspeed_spi_segment_ast2600_end,
|
|
.segment_reg = aspeed_spi_segment_ast2600_reg,
|
|
};
|
|
|
|
static const struct aspeed_spi_data ast2600_spi_data = {
|
|
.max_cs = 2,
|
|
.hastype = false,
|
|
.mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
|
|
.we0 = 16,
|
|
.ctl0 = CE0_CTRL_REG,
|
|
.timing = CE0_TIMING_COMPENSATION_REG,
|
|
.hclk_mask = 0xf0fff0ff,
|
|
.hdiv_max = 2,
|
|
.calibrate = aspeed_spi_ast2600_calibrate,
|
|
.segment_start = aspeed_spi_segment_ast2600_start,
|
|
.segment_end = aspeed_spi_segment_ast2600_end,
|
|
.segment_reg = aspeed_spi_segment_ast2600_reg,
|
|
};
|
|
|
|
static const struct of_device_id aspeed_spi_matches[] = {
|
|
{ .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
|
|
{ .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data },
|
|
{ .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
|
|
{ .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
|
|
{ .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
|
|
{ .compatible = "aspeed,ast2600-spi", .data = &ast2600_spi_data },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, aspeed_spi_matches);
|
|
|
|
static struct platform_driver aspeed_spi_driver = {
|
|
.probe = aspeed_spi_probe,
|
|
.remove = aspeed_spi_remove,
|
|
.driver = {
|
|
.name = DEVICE_NAME,
|
|
.of_match_table = aspeed_spi_matches,
|
|
}
|
|
};
|
|
|
|
module_platform_driver(aspeed_spi_driver);
|
|
|
|
MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver");
|
|
MODULE_AUTHOR("Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>");
|
|
MODULE_AUTHOR("Cedric Le Goater <clg@kaod.org>");
|
|
MODULE_LICENSE("GPL v2");
|