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![Dan Carpenter](/assets/img/avatar_default.png)
This code accidentally returns success instead of a negative error code.
Fixes: a38a2233f2
("spi: bcmbca-hsspi: Add driver for newer HSSPI controller")
Signed-off-by: Dan Carpenter <error27@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/Y+zmrNJ9zjNQpzWq@kili
Signed-off-by: Mark Brown <broonie@kernel.org>
654 lines
17 KiB
C
654 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Broadcom BCMBCA High Speed SPI Controller driver
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*
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* Copyright 2000-2010 Broadcom Corporation
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* Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
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* Copyright 2019-2022 Broadcom Ltd
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/spi/spi.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/spi/spi-mem.h>
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#include <linux/pm_runtime.h>
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#define HSSPI_GLOBAL_CTRL_REG 0x0
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#define GLOBAL_CTRL_CS_POLARITY_SHIFT 0
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#define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff
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#define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8
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#define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00
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#define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16)
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#define GLOBAL_CTRL_CLK_POLARITY BIT(17)
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#define GLOBAL_CTRL_MOSI_IDLE BIT(18)
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#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
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#define HSSPI_INT_STATUS_REG 0x8
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#define HSSPI_INT_STATUS_MASKED_REG 0xc
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#define HSSPI_INT_MASK_REG 0x10
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#define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0)
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#define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1)
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#define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2)
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#define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3)
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#define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4)
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#define HSSPI_INT_CLEAR_ALL 0xff001f1f
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#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
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#define PINGPONG_CMD_COMMAND_MASK 0xf
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#define PINGPONG_COMMAND_NOOP 0
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#define PINGPONG_COMMAND_START_NOW 1
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#define PINGPONG_COMMAND_START_TRIGGER 2
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#define PINGPONG_COMMAND_HALT 3
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#define PINGPONG_COMMAND_FLUSH 4
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#define PINGPONG_CMD_PROFILE_SHIFT 8
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#define PINGPONG_CMD_SS_SHIFT 12
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#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
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#define HSSPI_PINGPONG_STATUS_SRC_BUSY BIT(1)
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#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
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#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff
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#define CLK_CTRL_SPI_CLK_2X_SEL BIT(14)
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#define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15)
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#define CLK_CTRL_CLK_POLARITY BIT(16)
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#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
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#define SIGNAL_CTRL_LATCH_RISING BIT(12)
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#define SIGNAL_CTRL_LAUNCH_RISING BIT(13)
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#define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16)
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#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
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#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
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#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
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#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
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#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
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#define MODE_CTRL_MODE_3WIRE BIT(20)
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#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
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#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
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#define HSSPI_OP_MULTIBIT BIT(11)
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#define HSSPI_OP_CODE_SHIFT 13
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#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
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#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
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#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
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#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
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#define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT)
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#define HSSPI_BUFFER_LEN 512
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#define HSSPI_OPCODE_LEN 2
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#define HSSPI_MAX_PREPEND_LEN 15
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#define HSSPI_MAX_SYNC_CLOCK 30000000
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#define HSSPI_SPI_MAX_CS 8
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#define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
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#define HSSPI_POLL_STATUS_TIMEOUT_MS 100
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#define HSSPI_WAIT_MODE_POLLING 0
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#define HSSPI_WAIT_MODE_INTR 1
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#define HSSPI_WAIT_MODE_MAX HSSPI_WAIT_MODE_INTR
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#define SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT 0
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#define SPIM_CTRL_CS_OVERRIDE_SEL_MASK 0xff
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#define SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT 8
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#define SPIM_CTRL_CS_OVERRIDE_VAL_MASK 0xff
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struct bcmbca_hsspi {
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struct completion done;
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struct mutex bus_mutex;
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struct mutex msg_mutex;
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struct platform_device *pdev;
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struct clk *clk;
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struct clk *pll_clk;
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void __iomem *regs;
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void __iomem *spim_ctrl;
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u8 __iomem *fifo;
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u32 speed_hz;
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u8 cs_polarity;
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u32 wait_mode;
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};
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static ssize_t wait_mode_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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struct spi_controller *ctrl = dev_get_drvdata(dev);
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struct bcmbca_hsspi *bs = spi_master_get_devdata(ctrl);
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return sprintf(buf, "%d\n", bs->wait_mode);
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}
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static ssize_t wait_mode_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct spi_controller *ctrl = dev_get_drvdata(dev);
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struct bcmbca_hsspi *bs = spi_master_get_devdata(ctrl);
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u32 val;
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if (kstrtou32(buf, 10, &val))
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return -EINVAL;
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if (val > HSSPI_WAIT_MODE_MAX) {
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dev_warn(dev, "invalid wait mode %u\n", val);
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return -EINVAL;
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}
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mutex_lock(&bs->msg_mutex);
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bs->wait_mode = val;
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/* clear interrupt status to avoid spurious int on next transfer */
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if (val == HSSPI_WAIT_MODE_INTR)
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__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
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mutex_unlock(&bs->msg_mutex);
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return count;
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}
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static DEVICE_ATTR_RW(wait_mode);
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static struct attribute *bcmbca_hsspi_attrs[] = {
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&dev_attr_wait_mode.attr,
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NULL,
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};
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static const struct attribute_group bcmbca_hsspi_group = {
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.attrs = bcmbca_hsspi_attrs,
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};
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static void bcmbca_hsspi_set_cs(struct bcmbca_hsspi *bs, unsigned int cs,
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bool active)
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{
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u32 reg;
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/* No cs orerriden needed for SS7 internal cs on pcm based voice dev */
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if (cs == 7)
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return;
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mutex_lock(&bs->bus_mutex);
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reg = __raw_readl(bs->spim_ctrl);
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if (active)
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reg |= BIT(cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT);
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else
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reg &= ~BIT(cs + SPIM_CTRL_CS_OVERRIDE_SEL_SHIFT);
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__raw_writel(reg, bs->spim_ctrl);
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mutex_unlock(&bs->bus_mutex);
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}
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static void bcmbca_hsspi_set_clk(struct bcmbca_hsspi *bs,
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struct spi_device *spi, int hz)
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{
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unsigned int profile = spi->chip_select;
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u32 reg;
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reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
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__raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
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bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
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reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
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if (hz > HSSPI_MAX_SYNC_CLOCK)
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reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
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else
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reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
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__raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
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mutex_lock(&bs->bus_mutex);
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/* setup clock polarity */
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reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
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reg &= ~GLOBAL_CTRL_CLK_POLARITY;
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if (spi->mode & SPI_CPOL)
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reg |= GLOBAL_CTRL_CLK_POLARITY;
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__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
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mutex_unlock(&bs->bus_mutex);
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}
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static int bcmbca_hsspi_wait_cmd(struct bcmbca_hsspi *bs, unsigned int cs)
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{
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unsigned long limit;
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u32 reg = 0;
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int rc = 0;
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if (bs->wait_mode == HSSPI_WAIT_MODE_INTR) {
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if (wait_for_completion_timeout(&bs->done, HZ) == 0)
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rc = 1;
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} else {
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limit = jiffies + msecs_to_jiffies(HSSPI_POLL_STATUS_TIMEOUT_MS);
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while (!time_after(jiffies, limit)) {
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reg = __raw_readl(bs->regs + HSSPI_PINGPONG_STATUS_REG(0));
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if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY)
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cpu_relax();
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else
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break;
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}
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if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY)
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rc = 1;
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}
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if (rc)
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dev_err(&bs->pdev->dev, "transfer timed out!\n");
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return rc;
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}
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static int bcmbca_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t,
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struct spi_message *msg)
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{
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struct bcmbca_hsspi *bs = spi_master_get_devdata(spi->master);
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unsigned int chip_select = spi->chip_select;
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u16 opcode = 0, val;
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int pending = t->len;
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int step_size = HSSPI_BUFFER_LEN;
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const u8 *tx = t->tx_buf;
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u8 *rx = t->rx_buf;
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u32 reg = 0, cs_act = 0;
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bcmbca_hsspi_set_clk(bs, spi, t->speed_hz);
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if (tx && rx)
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opcode = HSSPI_OP_READ_WRITE;
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else if (tx)
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opcode = HSSPI_OP_WRITE;
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else if (rx)
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opcode = HSSPI_OP_READ;
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if (opcode != HSSPI_OP_READ)
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step_size -= HSSPI_OPCODE_LEN;
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if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
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(opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) {
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opcode |= HSSPI_OP_MULTIBIT;
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if (t->rx_nbits == SPI_NBITS_DUAL)
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reg |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT;
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if (t->tx_nbits == SPI_NBITS_DUAL)
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reg |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT;
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}
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__raw_writel(reg | 0xff,
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bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
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while (pending > 0) {
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int curr_step = min_t(int, step_size, pending);
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reinit_completion(&bs->done);
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if (tx) {
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memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
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tx += curr_step;
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}
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*(__be16 *)(&val) = cpu_to_be16(opcode | curr_step);
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__raw_writew(val, bs->fifo);
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/* enable interrupt */
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if (bs->wait_mode == HSSPI_WAIT_MODE_INTR)
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__raw_writel(HSSPI_PINGx_CMD_DONE(0),
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bs->regs + HSSPI_INT_MASK_REG);
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if (!cs_act) {
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/* must apply cs signal as close as the cmd starts */
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bcmbca_hsspi_set_cs(bs, chip_select, true);
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cs_act = 1;
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}
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reg = chip_select << PINGPONG_CMD_SS_SHIFT |
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chip_select << PINGPONG_CMD_PROFILE_SHIFT |
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PINGPONG_COMMAND_START_NOW;
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__raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
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if (bcmbca_hsspi_wait_cmd(bs, spi->chip_select))
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return -ETIMEDOUT;
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pending -= curr_step;
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if (rx) {
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memcpy_fromio(rx, bs->fifo, curr_step);
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rx += curr_step;
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}
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}
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return 0;
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}
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static int bcmbca_hsspi_setup(struct spi_device *spi)
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{
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struct bcmbca_hsspi *bs = spi_master_get_devdata(spi->master);
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u32 reg;
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reg = __raw_readl(bs->regs +
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HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
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reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
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if (spi->mode & SPI_CPHA)
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reg |= SIGNAL_CTRL_LAUNCH_RISING;
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else
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reg |= SIGNAL_CTRL_LATCH_RISING;
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__raw_writel(reg, bs->regs +
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HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
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mutex_lock(&bs->bus_mutex);
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reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
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if (spi->mode & SPI_CS_HIGH)
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reg |= BIT(spi->chip_select);
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else
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reg &= ~BIT(spi->chip_select);
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__raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
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if (spi->mode & SPI_CS_HIGH)
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bs->cs_polarity |= BIT(spi->chip_select);
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else
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bs->cs_polarity &= ~BIT(spi->chip_select);
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reg = __raw_readl(bs->spim_ctrl);
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reg &= ~BIT(spi->chip_select + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
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if (spi->mode & SPI_CS_HIGH)
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reg |= BIT(spi->chip_select + SPIM_CTRL_CS_OVERRIDE_VAL_SHIFT);
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__raw_writel(reg, bs->spim_ctrl);
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mutex_unlock(&bs->bus_mutex);
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return 0;
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}
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static int bcmbca_hsspi_transfer_one(struct spi_master *master,
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struct spi_message *msg)
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{
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struct bcmbca_hsspi *bs = spi_master_get_devdata(master);
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struct spi_transfer *t;
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struct spi_device *spi = msg->spi;
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int status = -EINVAL;
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bool keep_cs = false;
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mutex_lock(&bs->msg_mutex);
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list_for_each_entry(t, &msg->transfers, transfer_list) {
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status = bcmbca_hsspi_do_txrx(spi, t, msg);
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if (status)
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break;
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spi_transfer_delay_exec(t);
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if (t->cs_change) {
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if (list_is_last(&t->transfer_list, &msg->transfers)) {
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keep_cs = true;
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} else {
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if (!t->cs_off)
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bcmbca_hsspi_set_cs(bs, spi->chip_select, false);
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spi_transfer_cs_change_delay_exec(msg, t);
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if (!list_next_entry(t, transfer_list)->cs_off)
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bcmbca_hsspi_set_cs(bs, spi->chip_select, true);
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}
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} else if (!list_is_last(&t->transfer_list, &msg->transfers) &&
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t->cs_off != list_next_entry(t, transfer_list)->cs_off) {
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bcmbca_hsspi_set_cs(bs, spi->chip_select, t->cs_off);
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}
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msg->actual_length += t->len;
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}
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mutex_unlock(&bs->msg_mutex);
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if (status || !keep_cs)
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bcmbca_hsspi_set_cs(bs, spi->chip_select, false);
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msg->status = status;
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spi_finalize_current_message(master);
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return 0;
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}
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static irqreturn_t bcmbca_hsspi_interrupt(int irq, void *dev_id)
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{
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struct bcmbca_hsspi *bs = (struct bcmbca_hsspi *)dev_id;
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if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
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return IRQ_NONE;
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__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
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__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
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complete(&bs->done);
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return IRQ_HANDLED;
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}
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static int bcmbca_hsspi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct bcmbca_hsspi *bs;
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struct resource *res_mem;
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void __iomem *spim_ctrl;
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void __iomem *regs;
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struct device *dev = &pdev->dev;
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struct clk *clk, *pll_clk = NULL;
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int irq, ret;
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u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
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irq = platform_get_irq(pdev, 0);
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|
if (irq < 0)
|
|
return irq;
|
|
|
|
res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsspi");
|
|
if (!res_mem)
|
|
return -EINVAL;
|
|
regs = devm_ioremap_resource(dev, res_mem);
|
|
if (IS_ERR(regs))
|
|
return PTR_ERR(regs);
|
|
|
|
res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spim-ctrl");
|
|
if (!res_mem)
|
|
return -EINVAL;
|
|
spim_ctrl = devm_ioremap_resource(dev, res_mem);
|
|
if (IS_ERR(spim_ctrl))
|
|
return PTR_ERR(spim_ctrl);
|
|
|
|
clk = devm_clk_get(dev, "hsspi");
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
ret = clk_prepare_enable(clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
rate = clk_get_rate(clk);
|
|
if (!rate) {
|
|
pll_clk = devm_clk_get(dev, "pll");
|
|
|
|
if (IS_ERR(pll_clk)) {
|
|
ret = PTR_ERR(pll_clk);
|
|
goto out_disable_clk;
|
|
}
|
|
|
|
ret = clk_prepare_enable(pll_clk);
|
|
if (ret)
|
|
goto out_disable_clk;
|
|
|
|
rate = clk_get_rate(pll_clk);
|
|
if (!rate) {
|
|
ret = -EINVAL;
|
|
goto out_disable_pll_clk;
|
|
}
|
|
}
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*bs));
|
|
if (!master) {
|
|
ret = -ENOMEM;
|
|
goto out_disable_pll_clk;
|
|
}
|
|
|
|
bs = spi_master_get_devdata(master);
|
|
bs->pdev = pdev;
|
|
bs->clk = clk;
|
|
bs->pll_clk = pll_clk;
|
|
bs->regs = regs;
|
|
bs->spim_ctrl = spim_ctrl;
|
|
bs->speed_hz = rate;
|
|
bs->fifo = (u8 __iomem *) (bs->regs + HSSPI_FIFO_REG(0));
|
|
bs->wait_mode = HSSPI_WAIT_MODE_POLLING;
|
|
|
|
mutex_init(&bs->bus_mutex);
|
|
mutex_init(&bs->msg_mutex);
|
|
init_completion(&bs->done);
|
|
|
|
master->dev.of_node = dev->of_node;
|
|
if (!dev->of_node)
|
|
master->bus_num = HSSPI_BUS_NUM;
|
|
|
|
of_property_read_u32(dev->of_node, "num-cs", &num_cs);
|
|
if (num_cs > 8) {
|
|
dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
|
|
num_cs);
|
|
num_cs = HSSPI_SPI_MAX_CS;
|
|
}
|
|
master->num_chipselect = num_cs;
|
|
master->setup = bcmbca_hsspi_setup;
|
|
master->transfer_one_message = bcmbca_hsspi_transfer_one;
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
|
|
SPI_RX_DUAL | SPI_TX_DUAL;
|
|
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
|
master->auto_runtime_pm = true;
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
/* Initialize the hardware */
|
|
__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
|
|
|
|
/* clean up any pending interrupts */
|
|
__raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
|
|
|
|
/* read out default CS polarities */
|
|
reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
|
|
bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
|
|
__raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
|
|
bs->regs + HSSPI_GLOBAL_CTRL_REG);
|
|
|
|
if (irq > 0) {
|
|
ret = devm_request_irq(dev, irq, bcmbca_hsspi_interrupt, IRQF_SHARED,
|
|
pdev->name, bs);
|
|
if (ret)
|
|
goto out_put_master;
|
|
}
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
ret = sysfs_create_group(&pdev->dev.kobj, &bcmbca_hsspi_group);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "couldn't register sysfs group\n");
|
|
goto out_pm_disable;
|
|
}
|
|
|
|
/* register and we are done */
|
|
ret = devm_spi_register_master(dev, master);
|
|
if (ret)
|
|
goto out_sysgroup_disable;
|
|
|
|
dev_info(dev, "Broadcom BCMBCA High Speed SPI Controller driver");
|
|
|
|
return 0;
|
|
|
|
out_sysgroup_disable:
|
|
sysfs_remove_group(&pdev->dev.kobj, &bcmbca_hsspi_group);
|
|
out_pm_disable:
|
|
pm_runtime_disable(&pdev->dev);
|
|
out_put_master:
|
|
spi_master_put(master);
|
|
out_disable_pll_clk:
|
|
clk_disable_unprepare(pll_clk);
|
|
out_disable_clk:
|
|
clk_disable_unprepare(clk);
|
|
return ret;
|
|
}
|
|
|
|
static int bcmbca_hsspi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct bcmbca_hsspi *bs = spi_master_get_devdata(master);
|
|
|
|
/* reset the hardware and block queue progress */
|
|
__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
|
|
clk_disable_unprepare(bs->pll_clk);
|
|
clk_disable_unprepare(bs->clk);
|
|
sysfs_remove_group(&pdev->dev.kobj, &bcmbca_hsspi_group);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int bcmbca_hsspi_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct bcmbca_hsspi *bs = spi_master_get_devdata(master);
|
|
|
|
spi_master_suspend(master);
|
|
clk_disable_unprepare(bs->pll_clk);
|
|
clk_disable_unprepare(bs->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bcmbca_hsspi_resume(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct bcmbca_hsspi *bs = spi_master_get_devdata(master);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(bs->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (bs->pll_clk) {
|
|
ret = clk_prepare_enable(bs->pll_clk);
|
|
if (ret) {
|
|
clk_disable_unprepare(bs->clk);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
spi_master_resume(master);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(bcmbca_hsspi_pm_ops, bcmbca_hsspi_suspend,
|
|
bcmbca_hsspi_resume);
|
|
|
|
static const struct of_device_id bcmbca_hsspi_of_match[] = {
|
|
{ .compatible = "brcm,bcmbca-hsspi-v1.1", },
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, bcmbca_hsspi_of_match);
|
|
|
|
static struct platform_driver bcmbca_hsspi_driver = {
|
|
.driver = {
|
|
.name = "bcmbca-hsspi",
|
|
.pm = &bcmbca_hsspi_pm_ops,
|
|
.of_match_table = bcmbca_hsspi_of_match,
|
|
},
|
|
.probe = bcmbca_hsspi_probe,
|
|
.remove = bcmbca_hsspi_remove,
|
|
};
|
|
|
|
module_platform_driver(bcmbca_hsspi_driver);
|
|
|
|
MODULE_ALIAS("platform:bcmbca_hsspi");
|
|
MODULE_DESCRIPTION("Broadcom BCMBCA High Speed SPI Controller driver");
|
|
MODULE_LICENSE("GPL");
|