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![Xiongfeng Wang](/assets/img/avatar_default.png)
pci_get_device() will increase the reference count for the returned
pci_dev. Since 'dma_dev' is only used to filter the channel in
dw_spi_dma_chan_filer() after using it we need to call pci_dev_put() to
decrease the reference count. Also add pci_dev_put() for the error case.
Fixes: 7063c0d942
("spi/dw_spi: add DMA support")
Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Acked-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/r/20221116093204.46700-1-wangxiongfeng2@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
671 lines
17 KiB
C
671 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Special handling for DW DMA core
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*
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* Copyright (c) 2009, 2014 Intel Corporation.
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*/
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#include <linux/completion.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/irqreturn.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_data/dma-dw.h>
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#include <linux/spi/spi.h>
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#include <linux/types.h>
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#include "spi-dw.h"
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#define DW_SPI_RX_BUSY 0
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#define DW_SPI_RX_BURST_LEVEL 16
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#define DW_SPI_TX_BUSY 1
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#define DW_SPI_TX_BURST_LEVEL 16
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static bool dw_spi_dma_chan_filter(struct dma_chan *chan, void *param)
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{
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struct dw_dma_slave *s = param;
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if (s->dma_dev != chan->device->dev)
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return false;
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chan->private = s;
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return true;
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}
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static void dw_spi_dma_maxburst_init(struct dw_spi *dws)
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{
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struct dma_slave_caps caps;
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u32 max_burst, def_burst;
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int ret;
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def_burst = dws->fifo_len / 2;
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ret = dma_get_slave_caps(dws->rxchan, &caps);
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if (!ret && caps.max_burst)
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max_burst = caps.max_burst;
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else
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max_burst = DW_SPI_RX_BURST_LEVEL;
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dws->rxburst = min(max_burst, def_burst);
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dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);
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ret = dma_get_slave_caps(dws->txchan, &caps);
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if (!ret && caps.max_burst)
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max_burst = caps.max_burst;
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else
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max_burst = DW_SPI_TX_BURST_LEVEL;
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/*
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* Having a Rx DMA channel serviced with higher priority than a Tx DMA
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* channel might not be enough to provide a well balanced DMA-based
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* SPI transfer interface. There might still be moments when the Tx DMA
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* channel is occasionally handled faster than the Rx DMA channel.
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* That in its turn will eventually cause the SPI Rx FIFO overflow if
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* SPI bus speed is high enough to fill the SPI Rx FIFO in before it's
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* cleared by the Rx DMA channel. In order to fix the problem the Tx
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* DMA activity is intentionally slowed down by limiting the SPI Tx
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* FIFO depth with a value twice bigger than the Tx burst length.
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*/
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dws->txburst = min(max_burst, def_burst);
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dw_writel(dws, DW_SPI_DMATDLR, dws->txburst);
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}
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static void dw_spi_dma_sg_burst_init(struct dw_spi *dws)
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{
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struct dma_slave_caps tx = {0}, rx = {0};
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dma_get_slave_caps(dws->txchan, &tx);
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dma_get_slave_caps(dws->rxchan, &rx);
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if (tx.max_sg_burst > 0 && rx.max_sg_burst > 0)
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dws->dma_sg_burst = min(tx.max_sg_burst, rx.max_sg_burst);
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else if (tx.max_sg_burst > 0)
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dws->dma_sg_burst = tx.max_sg_burst;
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else if (rx.max_sg_burst > 0)
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dws->dma_sg_burst = rx.max_sg_burst;
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else
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dws->dma_sg_burst = 0;
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}
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static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
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{
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struct dw_dma_slave dma_tx = { .dst_id = 1 }, *tx = &dma_tx;
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struct dw_dma_slave dma_rx = { .src_id = 0 }, *rx = &dma_rx;
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struct pci_dev *dma_dev;
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dma_cap_mask_t mask;
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/*
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* Get pci device for DMA controller, currently it could only
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* be the DMA controller of Medfield
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*/
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dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
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if (!dma_dev)
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return -ENODEV;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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/* 1. Init rx channel */
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rx->dma_dev = &dma_dev->dev;
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dws->rxchan = dma_request_channel(mask, dw_spi_dma_chan_filter, rx);
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if (!dws->rxchan)
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goto err_exit;
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/* 2. Init tx channel */
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tx->dma_dev = &dma_dev->dev;
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dws->txchan = dma_request_channel(mask, dw_spi_dma_chan_filter, tx);
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if (!dws->txchan)
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goto free_rxchan;
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dws->master->dma_rx = dws->rxchan;
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dws->master->dma_tx = dws->txchan;
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init_completion(&dws->dma_completion);
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dw_spi_dma_maxburst_init(dws);
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dw_spi_dma_sg_burst_init(dws);
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pci_dev_put(dma_dev);
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return 0;
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free_rxchan:
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dma_release_channel(dws->rxchan);
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dws->rxchan = NULL;
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err_exit:
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pci_dev_put(dma_dev);
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return -EBUSY;
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}
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static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
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{
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int ret;
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dws->rxchan = dma_request_chan(dev, "rx");
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if (IS_ERR(dws->rxchan)) {
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ret = PTR_ERR(dws->rxchan);
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dws->rxchan = NULL;
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goto err_exit;
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}
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dws->txchan = dma_request_chan(dev, "tx");
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if (IS_ERR(dws->txchan)) {
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ret = PTR_ERR(dws->txchan);
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dws->txchan = NULL;
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goto free_rxchan;
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}
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dws->master->dma_rx = dws->rxchan;
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dws->master->dma_tx = dws->txchan;
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init_completion(&dws->dma_completion);
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dw_spi_dma_maxburst_init(dws);
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dw_spi_dma_sg_burst_init(dws);
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return 0;
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free_rxchan:
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dma_release_channel(dws->rxchan);
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dws->rxchan = NULL;
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err_exit:
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return ret;
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}
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static void dw_spi_dma_exit(struct dw_spi *dws)
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{
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if (dws->txchan) {
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dmaengine_terminate_sync(dws->txchan);
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dma_release_channel(dws->txchan);
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}
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if (dws->rxchan) {
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dmaengine_terminate_sync(dws->rxchan);
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dma_release_channel(dws->rxchan);
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}
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}
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static irqreturn_t dw_spi_dma_transfer_handler(struct dw_spi *dws)
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{
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dw_spi_check_status(dws, false);
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complete(&dws->dma_completion);
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return IRQ_HANDLED;
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}
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static bool dw_spi_can_dma(struct spi_controller *master,
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struct spi_device *spi, struct spi_transfer *xfer)
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{
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struct dw_spi *dws = spi_controller_get_devdata(master);
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return xfer->len > dws->fifo_len;
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}
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static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
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{
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if (n_bytes == 1)
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return DMA_SLAVE_BUSWIDTH_1_BYTE;
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else if (n_bytes == 2)
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return DMA_SLAVE_BUSWIDTH_2_BYTES;
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return DMA_SLAVE_BUSWIDTH_UNDEFINED;
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}
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static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed)
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{
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unsigned long long ms;
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ms = len * MSEC_PER_SEC * BITS_PER_BYTE;
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do_div(ms, speed);
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ms += ms + 200;
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if (ms > UINT_MAX)
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ms = UINT_MAX;
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ms = wait_for_completion_timeout(&dws->dma_completion,
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msecs_to_jiffies(ms));
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if (ms == 0) {
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dev_err(&dws->master->cur_msg->spi->dev,
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"DMA transaction timed out\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static inline bool dw_spi_dma_tx_busy(struct dw_spi *dws)
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{
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return !(dw_readl(dws, DW_SPI_SR) & DW_SPI_SR_TF_EMPT);
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}
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static int dw_spi_dma_wait_tx_done(struct dw_spi *dws,
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struct spi_transfer *xfer)
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{
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int retry = DW_SPI_WAIT_RETRIES;
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struct spi_delay delay;
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u32 nents;
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nents = dw_readl(dws, DW_SPI_TXFLR);
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delay.unit = SPI_DELAY_UNIT_SCK;
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delay.value = nents * dws->n_bytes * BITS_PER_BYTE;
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while (dw_spi_dma_tx_busy(dws) && retry--)
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spi_delay_exec(&delay, xfer);
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if (retry < 0) {
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dev_err(&dws->master->dev, "Tx hanged up\n");
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return -EIO;
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}
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return 0;
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}
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/*
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* dws->dma_chan_busy is set before the dma transfer starts, callback for tx
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* channel will clear a corresponding bit.
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*/
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static void dw_spi_dma_tx_done(void *arg)
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{
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struct dw_spi *dws = arg;
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clear_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy);
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if (test_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy))
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return;
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complete(&dws->dma_completion);
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}
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static int dw_spi_dma_config_tx(struct dw_spi *dws)
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{
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struct dma_slave_config txconf;
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memset(&txconf, 0, sizeof(txconf));
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txconf.direction = DMA_MEM_TO_DEV;
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txconf.dst_addr = dws->dma_addr;
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txconf.dst_maxburst = dws->txburst;
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txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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txconf.dst_addr_width = dw_spi_dma_convert_width(dws->n_bytes);
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txconf.device_fc = false;
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return dmaengine_slave_config(dws->txchan, &txconf);
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}
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static int dw_spi_dma_submit_tx(struct dw_spi *dws, struct scatterlist *sgl,
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unsigned int nents)
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{
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struct dma_async_tx_descriptor *txdesc;
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dma_cookie_t cookie;
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int ret;
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txdesc = dmaengine_prep_slave_sg(dws->txchan, sgl, nents,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!txdesc)
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return -ENOMEM;
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txdesc->callback = dw_spi_dma_tx_done;
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txdesc->callback_param = dws;
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cookie = dmaengine_submit(txdesc);
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ret = dma_submit_error(cookie);
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if (ret) {
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dmaengine_terminate_sync(dws->txchan);
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return ret;
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}
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set_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy);
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return 0;
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}
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static inline bool dw_spi_dma_rx_busy(struct dw_spi *dws)
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{
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return !!(dw_readl(dws, DW_SPI_SR) & DW_SPI_SR_RF_NOT_EMPT);
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}
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static int dw_spi_dma_wait_rx_done(struct dw_spi *dws)
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{
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int retry = DW_SPI_WAIT_RETRIES;
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struct spi_delay delay;
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unsigned long ns, us;
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u32 nents;
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/*
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* It's unlikely that DMA engine is still doing the data fetching, but
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* if it's let's give it some reasonable time. The timeout calculation
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* is based on the synchronous APB/SSI reference clock rate, on a
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* number of data entries left in the Rx FIFO, times a number of clock
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* periods normally needed for a single APB read/write transaction
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* without PREADY signal utilized (which is true for the DW APB SSI
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* controller).
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*/
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nents = dw_readl(dws, DW_SPI_RXFLR);
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ns = 4U * NSEC_PER_SEC / dws->max_freq * nents;
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if (ns <= NSEC_PER_USEC) {
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delay.unit = SPI_DELAY_UNIT_NSECS;
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delay.value = ns;
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} else {
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us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
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delay.unit = SPI_DELAY_UNIT_USECS;
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delay.value = clamp_val(us, 0, USHRT_MAX);
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}
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while (dw_spi_dma_rx_busy(dws) && retry--)
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spi_delay_exec(&delay, NULL);
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if (retry < 0) {
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dev_err(&dws->master->dev, "Rx hanged up\n");
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return -EIO;
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}
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return 0;
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}
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/*
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* dws->dma_chan_busy is set before the dma transfer starts, callback for rx
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* channel will clear a corresponding bit.
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*/
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static void dw_spi_dma_rx_done(void *arg)
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{
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struct dw_spi *dws = arg;
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clear_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy);
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if (test_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy))
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return;
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complete(&dws->dma_completion);
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}
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static int dw_spi_dma_config_rx(struct dw_spi *dws)
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{
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struct dma_slave_config rxconf;
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memset(&rxconf, 0, sizeof(rxconf));
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rxconf.direction = DMA_DEV_TO_MEM;
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rxconf.src_addr = dws->dma_addr;
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rxconf.src_maxburst = dws->rxburst;
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rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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rxconf.src_addr_width = dw_spi_dma_convert_width(dws->n_bytes);
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rxconf.device_fc = false;
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return dmaengine_slave_config(dws->rxchan, &rxconf);
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}
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static int dw_spi_dma_submit_rx(struct dw_spi *dws, struct scatterlist *sgl,
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unsigned int nents)
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{
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struct dma_async_tx_descriptor *rxdesc;
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dma_cookie_t cookie;
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int ret;
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rxdesc = dmaengine_prep_slave_sg(dws->rxchan, sgl, nents,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!rxdesc)
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return -ENOMEM;
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rxdesc->callback = dw_spi_dma_rx_done;
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rxdesc->callback_param = dws;
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cookie = dmaengine_submit(rxdesc);
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ret = dma_submit_error(cookie);
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if (ret) {
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dmaengine_terminate_sync(dws->rxchan);
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return ret;
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}
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set_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy);
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return 0;
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}
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static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
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{
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u16 imr, dma_ctrl;
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int ret;
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if (!xfer->tx_buf)
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return -EINVAL;
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/* Setup DMA channels */
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ret = dw_spi_dma_config_tx(dws);
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if (ret)
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return ret;
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if (xfer->rx_buf) {
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ret = dw_spi_dma_config_rx(dws);
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if (ret)
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return ret;
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}
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/* Set the DMA handshaking interface */
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dma_ctrl = DW_SPI_DMACR_TDMAE;
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if (xfer->rx_buf)
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dma_ctrl |= DW_SPI_DMACR_RDMAE;
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dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
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/* Set the interrupt mask */
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imr = DW_SPI_INT_TXOI;
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if (xfer->rx_buf)
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imr |= DW_SPI_INT_RXUI | DW_SPI_INT_RXOI;
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dw_spi_umask_intr(dws, imr);
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reinit_completion(&dws->dma_completion);
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dws->transfer_handler = dw_spi_dma_transfer_handler;
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return 0;
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}
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static int dw_spi_dma_transfer_all(struct dw_spi *dws,
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struct spi_transfer *xfer)
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{
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int ret;
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/* Submit the DMA Tx transfer */
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ret = dw_spi_dma_submit_tx(dws, xfer->tx_sg.sgl, xfer->tx_sg.nents);
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if (ret)
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goto err_clear_dmac;
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/* Submit the DMA Rx transfer if required */
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if (xfer->rx_buf) {
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ret = dw_spi_dma_submit_rx(dws, xfer->rx_sg.sgl,
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xfer->rx_sg.nents);
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if (ret)
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goto err_clear_dmac;
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/* rx must be started before tx due to spi instinct */
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dma_async_issue_pending(dws->rxchan);
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}
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dma_async_issue_pending(dws->txchan);
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ret = dw_spi_dma_wait(dws, xfer->len, xfer->effective_speed_hz);
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err_clear_dmac:
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dw_writel(dws, DW_SPI_DMACR, 0);
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|
return ret;
|
|
}
|
|
|
|
/*
|
|
* In case if at least one of the requested DMA channels doesn't support the
|
|
* hardware accelerated SG list entries traverse, the DMA driver will most
|
|
* likely work that around by performing the IRQ-based SG list entries
|
|
* resubmission. That might and will cause a problem if the DMA Tx channel is
|
|
* recharged and re-executed before the Rx DMA channel. Due to
|
|
* non-deterministic IRQ-handler execution latency the DMA Tx channel will
|
|
* start pushing data to the SPI bus before the Rx DMA channel is even
|
|
* reinitialized with the next inbound SG list entry. By doing so the DMA Tx
|
|
* channel will implicitly start filling the DW APB SSI Rx FIFO up, which while
|
|
* the DMA Rx channel being recharged and re-executed will eventually be
|
|
* overflown.
|
|
*
|
|
* In order to solve the problem we have to feed the DMA engine with SG list
|
|
* entries one-by-one. It shall keep the DW APB SSI Tx and Rx FIFOs
|
|
* synchronized and prevent the Rx FIFO overflow. Since in general the tx_sg
|
|
* and rx_sg lists may have different number of entries of different lengths
|
|
* (though total length should match) let's virtually split the SG-lists to the
|
|
* set of DMA transfers, which length is a minimum of the ordered SG-entries
|
|
* lengths. An ASCII-sketch of the implemented algo is following:
|
|
* xfer->len
|
|
* |___________|
|
|
* tx_sg list: |___|____|__|
|
|
* rx_sg list: |_|____|____|
|
|
* DMA transfers: |_|_|__|_|__|
|
|
*
|
|
* Note in order to have this workaround solving the denoted problem the DMA
|
|
* engine driver should properly initialize the max_sg_burst capability and set
|
|
* the DMA device max segment size parameter with maximum data block size the
|
|
* DMA engine supports.
|
|
*/
|
|
|
|
static int dw_spi_dma_transfer_one(struct dw_spi *dws,
|
|
struct spi_transfer *xfer)
|
|
{
|
|
struct scatterlist *tx_sg = NULL, *rx_sg = NULL, tx_tmp, rx_tmp;
|
|
unsigned int tx_len = 0, rx_len = 0;
|
|
unsigned int base, len;
|
|
int ret;
|
|
|
|
sg_init_table(&tx_tmp, 1);
|
|
sg_init_table(&rx_tmp, 1);
|
|
|
|
for (base = 0, len = 0; base < xfer->len; base += len) {
|
|
/* Fetch next Tx DMA data chunk */
|
|
if (!tx_len) {
|
|
tx_sg = !tx_sg ? &xfer->tx_sg.sgl[0] : sg_next(tx_sg);
|
|
sg_dma_address(&tx_tmp) = sg_dma_address(tx_sg);
|
|
tx_len = sg_dma_len(tx_sg);
|
|
}
|
|
|
|
/* Fetch next Rx DMA data chunk */
|
|
if (!rx_len) {
|
|
rx_sg = !rx_sg ? &xfer->rx_sg.sgl[0] : sg_next(rx_sg);
|
|
sg_dma_address(&rx_tmp) = sg_dma_address(rx_sg);
|
|
rx_len = sg_dma_len(rx_sg);
|
|
}
|
|
|
|
len = min(tx_len, rx_len);
|
|
|
|
sg_dma_len(&tx_tmp) = len;
|
|
sg_dma_len(&rx_tmp) = len;
|
|
|
|
/* Submit DMA Tx transfer */
|
|
ret = dw_spi_dma_submit_tx(dws, &tx_tmp, 1);
|
|
if (ret)
|
|
break;
|
|
|
|
/* Submit DMA Rx transfer */
|
|
ret = dw_spi_dma_submit_rx(dws, &rx_tmp, 1);
|
|
if (ret)
|
|
break;
|
|
|
|
/* Rx must be started before Tx due to SPI instinct */
|
|
dma_async_issue_pending(dws->rxchan);
|
|
|
|
dma_async_issue_pending(dws->txchan);
|
|
|
|
/*
|
|
* Here we only need to wait for the DMA transfer to be
|
|
* finished since SPI controller is kept enabled during the
|
|
* procedure this loop implements and there is no risk to lose
|
|
* data left in the Tx/Rx FIFOs.
|
|
*/
|
|
ret = dw_spi_dma_wait(dws, len, xfer->effective_speed_hz);
|
|
if (ret)
|
|
break;
|
|
|
|
reinit_completion(&dws->dma_completion);
|
|
|
|
sg_dma_address(&tx_tmp) += len;
|
|
sg_dma_address(&rx_tmp) += len;
|
|
tx_len -= len;
|
|
rx_len -= len;
|
|
}
|
|
|
|
dw_writel(dws, DW_SPI_DMACR, 0);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
|
|
{
|
|
unsigned int nents;
|
|
int ret;
|
|
|
|
nents = max(xfer->tx_sg.nents, xfer->rx_sg.nents);
|
|
|
|
/*
|
|
* Execute normal DMA-based transfer (which submits the Rx and Tx SG
|
|
* lists directly to the DMA engine at once) if either full hardware
|
|
* accelerated SG list traverse is supported by both channels, or the
|
|
* Tx-only SPI transfer is requested, or the DMA engine is capable to
|
|
* handle both SG lists on hardware accelerated basis.
|
|
*/
|
|
if (!dws->dma_sg_burst || !xfer->rx_buf || nents <= dws->dma_sg_burst)
|
|
ret = dw_spi_dma_transfer_all(dws, xfer);
|
|
else
|
|
ret = dw_spi_dma_transfer_one(dws, xfer);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (dws->master->cur_msg->status == -EINPROGRESS) {
|
|
ret = dw_spi_dma_wait_tx_done(dws, xfer);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (xfer->rx_buf && dws->master->cur_msg->status == -EINPROGRESS)
|
|
ret = dw_spi_dma_wait_rx_done(dws);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void dw_spi_dma_stop(struct dw_spi *dws)
|
|
{
|
|
if (test_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy)) {
|
|
dmaengine_terminate_sync(dws->txchan);
|
|
clear_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy);
|
|
}
|
|
if (test_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy)) {
|
|
dmaengine_terminate_sync(dws->rxchan);
|
|
clear_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy);
|
|
}
|
|
}
|
|
|
|
static const struct dw_spi_dma_ops dw_spi_dma_mfld_ops = {
|
|
.dma_init = dw_spi_dma_init_mfld,
|
|
.dma_exit = dw_spi_dma_exit,
|
|
.dma_setup = dw_spi_dma_setup,
|
|
.can_dma = dw_spi_can_dma,
|
|
.dma_transfer = dw_spi_dma_transfer,
|
|
.dma_stop = dw_spi_dma_stop,
|
|
};
|
|
|
|
void dw_spi_dma_setup_mfld(struct dw_spi *dws)
|
|
{
|
|
dws->dma_ops = &dw_spi_dma_mfld_ops;
|
|
}
|
|
EXPORT_SYMBOL_NS_GPL(dw_spi_dma_setup_mfld, SPI_DW_CORE);
|
|
|
|
static const struct dw_spi_dma_ops dw_spi_dma_generic_ops = {
|
|
.dma_init = dw_spi_dma_init_generic,
|
|
.dma_exit = dw_spi_dma_exit,
|
|
.dma_setup = dw_spi_dma_setup,
|
|
.can_dma = dw_spi_can_dma,
|
|
.dma_transfer = dw_spi_dma_transfer,
|
|
.dma_stop = dw_spi_dma_stop,
|
|
};
|
|
|
|
void dw_spi_dma_setup_generic(struct dw_spi *dws)
|
|
{
|
|
dws->dma_ops = &dw_spi_dma_generic_ops;
|
|
}
|
|
EXPORT_SYMBOL_NS_GPL(dw_spi_dma_setup_generic, SPI_DW_CORE);
|