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![Alexander Sverdlin](/assets/img/avatar_default.png)
Use clk_prepare_enable()/clk_disable_unprepare() in preparation for switch to Common Clock Framework, otherwise the following is visible: WARNING: CPU: 0 PID: 1 at drivers/clk/clk.c:1011 clk_core_enable+0x9c/0xbc Enabling unprepared ep93xx-spi.0 ... Hardware name: Cirrus Logic EDB9302 Evaluation Board ... clk_core_enable clk_core_enable_lock ep93xx_spi_prepare_hardware __spi_pump_messages __spi_sync spi_sync spi_sync_transfer.constprop.0 regmap_spi_write _regmap_raw_write_impl _regmap_bus_raw_write _regmap_update_bits regmap_update_bits_base cs4271_component_probe snd_soc_component_probe soc_probe_component snd_soc_bind_card edb93xx_probe ... spi_master spi0: failed to prepare transfer hardware: -108 Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me> Acked-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20210726140001.24820-3-nikita.shubin@maquefel.me Signed-off-by: Mark Brown <broonie@kernel.org>
770 lines
19 KiB
C
770 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Driver for Cirrus Logic EP93xx SPI controller.
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*
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* Copyright (C) 2010-2011 Mika Westerberg
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*
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* Explicit FIFO handling code was inspired by amba-pl022 driver.
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*
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* Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
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*
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* For more information about the SPI controller see documentation on Cirrus
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* Logic web site:
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* https://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/scatterlist.h>
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#include <linux/spi/spi.h>
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#include <linux/platform_data/dma-ep93xx.h>
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#include <linux/platform_data/spi-ep93xx.h>
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#define SSPCR0 0x0000
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#define SSPCR0_SPO BIT(6)
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#define SSPCR0_SPH BIT(7)
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#define SSPCR0_SCR_SHIFT 8
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#define SSPCR1 0x0004
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#define SSPCR1_RIE BIT(0)
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#define SSPCR1_TIE BIT(1)
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#define SSPCR1_RORIE BIT(2)
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#define SSPCR1_LBM BIT(3)
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#define SSPCR1_SSE BIT(4)
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#define SSPCR1_MS BIT(5)
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#define SSPCR1_SOD BIT(6)
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#define SSPDR 0x0008
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#define SSPSR 0x000c
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#define SSPSR_TFE BIT(0)
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#define SSPSR_TNF BIT(1)
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#define SSPSR_RNE BIT(2)
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#define SSPSR_RFF BIT(3)
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#define SSPSR_BSY BIT(4)
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#define SSPCPSR 0x0010
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#define SSPIIR 0x0014
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#define SSPIIR_RIS BIT(0)
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#define SSPIIR_TIS BIT(1)
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#define SSPIIR_RORIS BIT(2)
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#define SSPICR SSPIIR
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/* timeout in milliseconds */
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#define SPI_TIMEOUT 5
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/* maximum depth of RX/TX FIFO */
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#define SPI_FIFO_SIZE 8
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/**
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* struct ep93xx_spi - EP93xx SPI controller structure
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* @clk: clock for the controller
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* @mmio: pointer to ioremap()'d registers
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* @sspdr_phys: physical address of the SSPDR register
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* @tx: current byte in transfer to transmit
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* @rx: current byte in transfer to receive
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* @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
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* frame decreases this level and sending one frame increases it.
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* @dma_rx: RX DMA channel
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* @dma_tx: TX DMA channel
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* @dma_rx_data: RX parameters passed to the DMA engine
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* @dma_tx_data: TX parameters passed to the DMA engine
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* @rx_sgt: sg table for RX transfers
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* @tx_sgt: sg table for TX transfers
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* @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
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* the client
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*/
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struct ep93xx_spi {
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struct clk *clk;
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void __iomem *mmio;
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unsigned long sspdr_phys;
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size_t tx;
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size_t rx;
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size_t fifo_level;
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struct dma_chan *dma_rx;
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struct dma_chan *dma_tx;
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struct ep93xx_dma_data dma_rx_data;
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struct ep93xx_dma_data dma_tx_data;
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struct sg_table rx_sgt;
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struct sg_table tx_sgt;
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void *zeropage;
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};
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/* converts bits per word to CR0.DSS value */
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#define bits_per_word_to_dss(bpw) ((bpw) - 1)
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/**
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* ep93xx_spi_calc_divisors() - calculates SPI clock divisors
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* @master: SPI master
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* @rate: desired SPI output clock rate
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* @div_cpsr: pointer to return the cpsr (pre-scaler) divider
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* @div_scr: pointer to return the scr divider
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*/
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static int ep93xx_spi_calc_divisors(struct spi_master *master,
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u32 rate, u8 *div_cpsr, u8 *div_scr)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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unsigned long spi_clk_rate = clk_get_rate(espi->clk);
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int cpsr, scr;
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/*
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* Make sure that max value is between values supported by the
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* controller.
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*/
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rate = clamp(rate, master->min_speed_hz, master->max_speed_hz);
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/*
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* Calculate divisors so that we can get speed according the
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* following formula:
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* rate = spi_clock_rate / (cpsr * (1 + scr))
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*
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* cpsr must be even number and starts from 2, scr can be any number
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* between 0 and 255.
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*/
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for (cpsr = 2; cpsr <= 254; cpsr += 2) {
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for (scr = 0; scr <= 255; scr++) {
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if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
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*div_scr = (u8)scr;
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*div_cpsr = (u8)cpsr;
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return 0;
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}
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}
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}
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return -EINVAL;
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}
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static int ep93xx_spi_chip_setup(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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u8 dss = bits_per_word_to_dss(xfer->bits_per_word);
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u8 div_cpsr = 0;
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u8 div_scr = 0;
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u16 cr0;
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int err;
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err = ep93xx_spi_calc_divisors(master, xfer->speed_hz,
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&div_cpsr, &div_scr);
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if (err)
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return err;
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cr0 = div_scr << SSPCR0_SCR_SHIFT;
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if (spi->mode & SPI_CPOL)
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cr0 |= SSPCR0_SPO;
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if (spi->mode & SPI_CPHA)
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cr0 |= SSPCR0_SPH;
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cr0 |= dss;
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dev_dbg(&master->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
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spi->mode, div_cpsr, div_scr, dss);
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dev_dbg(&master->dev, "setup: cr0 %#x\n", cr0);
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writel(div_cpsr, espi->mmio + SSPCPSR);
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writel(cr0, espi->mmio + SSPCR0);
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return 0;
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}
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static void ep93xx_do_write(struct spi_master *master)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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struct spi_transfer *xfer = master->cur_msg->state;
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u32 val = 0;
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if (xfer->bits_per_word > 8) {
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if (xfer->tx_buf)
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val = ((u16 *)xfer->tx_buf)[espi->tx];
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espi->tx += 2;
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} else {
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if (xfer->tx_buf)
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val = ((u8 *)xfer->tx_buf)[espi->tx];
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espi->tx += 1;
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}
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writel(val, espi->mmio + SSPDR);
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}
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static void ep93xx_do_read(struct spi_master *master)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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struct spi_transfer *xfer = master->cur_msg->state;
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u32 val;
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val = readl(espi->mmio + SSPDR);
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if (xfer->bits_per_word > 8) {
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if (xfer->rx_buf)
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((u16 *)xfer->rx_buf)[espi->rx] = val;
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espi->rx += 2;
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} else {
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if (xfer->rx_buf)
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((u8 *)xfer->rx_buf)[espi->rx] = val;
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espi->rx += 1;
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}
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}
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/**
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* ep93xx_spi_read_write() - perform next RX/TX transfer
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* @master: SPI master
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*
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* This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
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* called several times, the whole transfer will be completed. Returns
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* %-EINPROGRESS when current transfer was not yet completed otherwise %0.
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*
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* When this function is finished, RX FIFO should be empty and TX FIFO should be
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* full.
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*/
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static int ep93xx_spi_read_write(struct spi_master *master)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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struct spi_transfer *xfer = master->cur_msg->state;
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/* read as long as RX FIFO has frames in it */
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while ((readl(espi->mmio + SSPSR) & SSPSR_RNE)) {
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ep93xx_do_read(master);
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espi->fifo_level--;
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}
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/* write as long as TX FIFO has room */
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while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < xfer->len) {
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ep93xx_do_write(master);
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espi->fifo_level++;
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}
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if (espi->rx == xfer->len)
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return 0;
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return -EINPROGRESS;
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}
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static enum dma_transfer_direction
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ep93xx_dma_data_to_trans_dir(enum dma_data_direction dir)
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{
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switch (dir) {
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case DMA_TO_DEVICE:
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return DMA_MEM_TO_DEV;
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case DMA_FROM_DEVICE:
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return DMA_DEV_TO_MEM;
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default:
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return DMA_TRANS_NONE;
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}
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}
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/**
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* ep93xx_spi_dma_prepare() - prepares a DMA transfer
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* @master: SPI master
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* @dir: DMA transfer direction
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*
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* Function configures the DMA, maps the buffer and prepares the DMA
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* descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
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* in case of failure.
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*/
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static struct dma_async_tx_descriptor *
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ep93xx_spi_dma_prepare(struct spi_master *master,
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enum dma_data_direction dir)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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struct spi_transfer *xfer = master->cur_msg->state;
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struct dma_async_tx_descriptor *txd;
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enum dma_slave_buswidth buswidth;
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struct dma_slave_config conf;
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struct scatterlist *sg;
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struct sg_table *sgt;
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struct dma_chan *chan;
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const void *buf, *pbuf;
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size_t len = xfer->len;
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int i, ret, nents;
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if (xfer->bits_per_word > 8)
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buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
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else
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buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
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memset(&conf, 0, sizeof(conf));
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conf.direction = ep93xx_dma_data_to_trans_dir(dir);
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if (dir == DMA_FROM_DEVICE) {
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chan = espi->dma_rx;
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buf = xfer->rx_buf;
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sgt = &espi->rx_sgt;
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conf.src_addr = espi->sspdr_phys;
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conf.src_addr_width = buswidth;
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} else {
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chan = espi->dma_tx;
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buf = xfer->tx_buf;
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sgt = &espi->tx_sgt;
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conf.dst_addr = espi->sspdr_phys;
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conf.dst_addr_width = buswidth;
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}
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ret = dmaengine_slave_config(chan, &conf);
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if (ret)
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return ERR_PTR(ret);
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/*
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* We need to split the transfer into PAGE_SIZE'd chunks. This is
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* because we are using @espi->zeropage to provide a zero RX buffer
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* for the TX transfers and we have only allocated one page for that.
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*
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* For performance reasons we allocate a new sg_table only when
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* needed. Otherwise we will re-use the current one. Eventually the
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* last sg_table is released in ep93xx_spi_release_dma().
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*/
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nents = DIV_ROUND_UP(len, PAGE_SIZE);
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if (nents != sgt->nents) {
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sg_free_table(sgt);
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ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
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if (ret)
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return ERR_PTR(ret);
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}
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pbuf = buf;
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for_each_sg(sgt->sgl, sg, sgt->nents, i) {
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size_t bytes = min_t(size_t, len, PAGE_SIZE);
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if (buf) {
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sg_set_page(sg, virt_to_page(pbuf), bytes,
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offset_in_page(pbuf));
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} else {
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sg_set_page(sg, virt_to_page(espi->zeropage),
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bytes, 0);
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}
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pbuf += bytes;
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len -= bytes;
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}
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if (WARN_ON(len)) {
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dev_warn(&master->dev, "len = %zu expected 0!\n", len);
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return ERR_PTR(-EINVAL);
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}
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nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
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if (!nents)
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return ERR_PTR(-ENOMEM);
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txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, conf.direction,
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DMA_CTRL_ACK);
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if (!txd) {
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dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
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return ERR_PTR(-ENOMEM);
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}
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return txd;
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}
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/**
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* ep93xx_spi_dma_finish() - finishes with a DMA transfer
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* @master: SPI master
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* @dir: DMA transfer direction
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*
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* Function finishes with the DMA transfer. After this, the DMA buffer is
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* unmapped.
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*/
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static void ep93xx_spi_dma_finish(struct spi_master *master,
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enum dma_data_direction dir)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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struct dma_chan *chan;
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struct sg_table *sgt;
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if (dir == DMA_FROM_DEVICE) {
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chan = espi->dma_rx;
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sgt = &espi->rx_sgt;
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} else {
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chan = espi->dma_tx;
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sgt = &espi->tx_sgt;
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}
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dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
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}
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static void ep93xx_spi_dma_callback(void *callback_param)
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{
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struct spi_master *master = callback_param;
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ep93xx_spi_dma_finish(master, DMA_TO_DEVICE);
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ep93xx_spi_dma_finish(master, DMA_FROM_DEVICE);
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spi_finalize_current_transfer(master);
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}
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static int ep93xx_spi_dma_transfer(struct spi_master *master)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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struct dma_async_tx_descriptor *rxd, *txd;
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rxd = ep93xx_spi_dma_prepare(master, DMA_FROM_DEVICE);
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if (IS_ERR(rxd)) {
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dev_err(&master->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
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return PTR_ERR(rxd);
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}
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txd = ep93xx_spi_dma_prepare(master, DMA_TO_DEVICE);
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if (IS_ERR(txd)) {
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ep93xx_spi_dma_finish(master, DMA_FROM_DEVICE);
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dev_err(&master->dev, "DMA TX failed: %ld\n", PTR_ERR(txd));
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return PTR_ERR(txd);
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}
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/* We are ready when RX is done */
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rxd->callback = ep93xx_spi_dma_callback;
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rxd->callback_param = master;
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/* Now submit both descriptors and start DMA */
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dmaengine_submit(rxd);
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dmaengine_submit(txd);
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dma_async_issue_pending(espi->dma_rx);
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dma_async_issue_pending(espi->dma_tx);
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/* signal that we need to wait for completion */
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return 1;
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}
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static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
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{
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struct spi_master *master = dev_id;
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struct ep93xx_spi *espi = spi_master_get_devdata(master);
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u32 val;
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/*
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* If we got ROR (receive overrun) interrupt we know that something is
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* wrong. Just abort the message.
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*/
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if (readl(espi->mmio + SSPIIR) & SSPIIR_RORIS) {
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/* clear the overrun interrupt */
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writel(0, espi->mmio + SSPICR);
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dev_warn(&master->dev,
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"receive overrun, aborting the message\n");
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master->cur_msg->status = -EIO;
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} else {
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/*
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* Interrupt is either RX (RIS) or TX (TIS). For both cases we
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* simply execute next data transfer.
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*/
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if (ep93xx_spi_read_write(master)) {
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/*
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* In normal case, there still is some processing left
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* for current transfer. Let's wait for the next
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* interrupt then.
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*/
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return IRQ_HANDLED;
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}
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}
|
|
|
|
/*
|
|
* Current transfer is finished, either with error or with success. In
|
|
* any case we disable interrupts and notify the worker to handle
|
|
* any post-processing of the message.
|
|
*/
|
|
val = readl(espi->mmio + SSPCR1);
|
|
val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
|
|
writel(val, espi->mmio + SSPCR1);
|
|
|
|
spi_finalize_current_transfer(master);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int ep93xx_spi_transfer_one(struct spi_master *master,
|
|
struct spi_device *spi,
|
|
struct spi_transfer *xfer)
|
|
{
|
|
struct ep93xx_spi *espi = spi_master_get_devdata(master);
|
|
u32 val;
|
|
int ret;
|
|
|
|
ret = ep93xx_spi_chip_setup(master, spi, xfer);
|
|
if (ret) {
|
|
dev_err(&master->dev, "failed to setup chip for transfer\n");
|
|
return ret;
|
|
}
|
|
|
|
master->cur_msg->state = xfer;
|
|
espi->rx = 0;
|
|
espi->tx = 0;
|
|
|
|
/*
|
|
* There is no point of setting up DMA for the transfers which will
|
|
* fit into the FIFO and can be transferred with a single interrupt.
|
|
* So in these cases we will be using PIO and don't bother for DMA.
|
|
*/
|
|
if (espi->dma_rx && xfer->len > SPI_FIFO_SIZE)
|
|
return ep93xx_spi_dma_transfer(master);
|
|
|
|
/* Using PIO so prime the TX FIFO and enable interrupts */
|
|
ep93xx_spi_read_write(master);
|
|
|
|
val = readl(espi->mmio + SSPCR1);
|
|
val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
|
|
writel(val, espi->mmio + SSPCR1);
|
|
|
|
/* signal that we need to wait for completion */
|
|
return 1;
|
|
}
|
|
|
|
static int ep93xx_spi_prepare_message(struct spi_master *master,
|
|
struct spi_message *msg)
|
|
{
|
|
struct ep93xx_spi *espi = spi_master_get_devdata(master);
|
|
unsigned long timeout;
|
|
|
|
/*
|
|
* Just to be sure: flush any data from RX FIFO.
|
|
*/
|
|
timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
|
|
while (readl(espi->mmio + SSPSR) & SSPSR_RNE) {
|
|
if (time_after(jiffies, timeout)) {
|
|
dev_warn(&master->dev,
|
|
"timeout while flushing RX FIFO\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
readl(espi->mmio + SSPDR);
|
|
}
|
|
|
|
/*
|
|
* We explicitly handle FIFO level. This way we don't have to check TX
|
|
* FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
|
|
*/
|
|
espi->fifo_level = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ep93xx_spi_prepare_hardware(struct spi_master *master)
|
|
{
|
|
struct ep93xx_spi *espi = spi_master_get_devdata(master);
|
|
u32 val;
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(espi->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
val = readl(espi->mmio + SSPCR1);
|
|
val |= SSPCR1_SSE;
|
|
writel(val, espi->mmio + SSPCR1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ep93xx_spi_unprepare_hardware(struct spi_master *master)
|
|
{
|
|
struct ep93xx_spi *espi = spi_master_get_devdata(master);
|
|
u32 val;
|
|
|
|
val = readl(espi->mmio + SSPCR1);
|
|
val &= ~SSPCR1_SSE;
|
|
writel(val, espi->mmio + SSPCR1);
|
|
|
|
clk_disable_unprepare(espi->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param)
|
|
{
|
|
if (ep93xx_dma_chan_is_m2p(chan))
|
|
return false;
|
|
|
|
chan->private = filter_param;
|
|
return true;
|
|
}
|
|
|
|
static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi)
|
|
{
|
|
dma_cap_mask_t mask;
|
|
int ret;
|
|
|
|
espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
|
|
if (!espi->zeropage)
|
|
return -ENOMEM;
|
|
|
|
dma_cap_zero(mask);
|
|
dma_cap_set(DMA_SLAVE, mask);
|
|
|
|
espi->dma_rx_data.port = EP93XX_DMA_SSP;
|
|
espi->dma_rx_data.direction = DMA_DEV_TO_MEM;
|
|
espi->dma_rx_data.name = "ep93xx-spi-rx";
|
|
|
|
espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter,
|
|
&espi->dma_rx_data);
|
|
if (!espi->dma_rx) {
|
|
ret = -ENODEV;
|
|
goto fail_free_page;
|
|
}
|
|
|
|
espi->dma_tx_data.port = EP93XX_DMA_SSP;
|
|
espi->dma_tx_data.direction = DMA_MEM_TO_DEV;
|
|
espi->dma_tx_data.name = "ep93xx-spi-tx";
|
|
|
|
espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter,
|
|
&espi->dma_tx_data);
|
|
if (!espi->dma_tx) {
|
|
ret = -ENODEV;
|
|
goto fail_release_rx;
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail_release_rx:
|
|
dma_release_channel(espi->dma_rx);
|
|
espi->dma_rx = NULL;
|
|
fail_free_page:
|
|
free_page((unsigned long)espi->zeropage);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void ep93xx_spi_release_dma(struct ep93xx_spi *espi)
|
|
{
|
|
if (espi->dma_rx) {
|
|
dma_release_channel(espi->dma_rx);
|
|
sg_free_table(&espi->rx_sgt);
|
|
}
|
|
if (espi->dma_tx) {
|
|
dma_release_channel(espi->dma_tx);
|
|
sg_free_table(&espi->tx_sgt);
|
|
}
|
|
|
|
if (espi->zeropage)
|
|
free_page((unsigned long)espi->zeropage);
|
|
}
|
|
|
|
static int ep93xx_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master;
|
|
struct ep93xx_spi_info *info;
|
|
struct ep93xx_spi *espi;
|
|
struct resource *res;
|
|
int irq;
|
|
int error;
|
|
|
|
info = dev_get_platdata(&pdev->dev);
|
|
if (!info) {
|
|
dev_err(&pdev->dev, "missing platform data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return -EBUSY;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "unable to get iomem resource\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*espi));
|
|
if (!master)
|
|
return -ENOMEM;
|
|
|
|
master->use_gpio_descriptors = true;
|
|
master->prepare_transfer_hardware = ep93xx_spi_prepare_hardware;
|
|
master->unprepare_transfer_hardware = ep93xx_spi_unprepare_hardware;
|
|
master->prepare_message = ep93xx_spi_prepare_message;
|
|
master->transfer_one = ep93xx_spi_transfer_one;
|
|
master->bus_num = pdev->id;
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
|
|
/*
|
|
* The SPI core will count the number of GPIO descriptors to figure
|
|
* out the number of chip selects available on the platform.
|
|
*/
|
|
master->num_chipselect = 0;
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
espi = spi_master_get_devdata(master);
|
|
|
|
espi->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(espi->clk)) {
|
|
dev_err(&pdev->dev, "unable to get spi clock\n");
|
|
error = PTR_ERR(espi->clk);
|
|
goto fail_release_master;
|
|
}
|
|
|
|
/*
|
|
* Calculate maximum and minimum supported clock rates
|
|
* for the controller.
|
|
*/
|
|
master->max_speed_hz = clk_get_rate(espi->clk) / 2;
|
|
master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);
|
|
|
|
espi->sspdr_phys = res->start + SSPDR;
|
|
|
|
espi->mmio = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(espi->mmio)) {
|
|
error = PTR_ERR(espi->mmio);
|
|
goto fail_release_master;
|
|
}
|
|
|
|
error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,
|
|
0, "ep93xx-spi", master);
|
|
if (error) {
|
|
dev_err(&pdev->dev, "failed to request irq\n");
|
|
goto fail_release_master;
|
|
}
|
|
|
|
if (info->use_dma && ep93xx_spi_setup_dma(espi))
|
|
dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
|
|
|
|
/* make sure that the hardware is disabled */
|
|
writel(0, espi->mmio + SSPCR1);
|
|
|
|
error = devm_spi_register_master(&pdev->dev, master);
|
|
if (error) {
|
|
dev_err(&pdev->dev, "failed to register SPI master\n");
|
|
goto fail_free_dma;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
|
|
(unsigned long)res->start, irq);
|
|
|
|
return 0;
|
|
|
|
fail_free_dma:
|
|
ep93xx_spi_release_dma(espi);
|
|
fail_release_master:
|
|
spi_master_put(master);
|
|
|
|
return error;
|
|
}
|
|
|
|
static int ep93xx_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct ep93xx_spi *espi = spi_master_get_devdata(master);
|
|
|
|
ep93xx_spi_release_dma(espi);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver ep93xx_spi_driver = {
|
|
.driver = {
|
|
.name = "ep93xx-spi",
|
|
},
|
|
.probe = ep93xx_spi_probe,
|
|
.remove = ep93xx_spi_remove,
|
|
};
|
|
module_platform_driver(ep93xx_spi_driver);
|
|
|
|
MODULE_DESCRIPTION("EP93xx SPI Controller driver");
|
|
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:ep93xx-spi");
|