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![Andy Shevchenko](/assets/img/avatar_default.png)
gpiod_count() either returns positive number of the CS or negative error code. In the stm32_qspi_setup() we check that configuration has enough CS for the dual flash mode and SPI mode is not changing over the lines of the code. Taking all above into considertion, refactor dual flash mode enable check by dropping unneeded CS check and reusing local mode variable. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220830182821.47919-2-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
982 lines
24 KiB
C
982 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/sizes.h>
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#include <linux/spi/spi-mem.h>
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#define QSPI_CR 0x00
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#define CR_EN BIT(0)
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#define CR_ABORT BIT(1)
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#define CR_DMAEN BIT(2)
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#define CR_TCEN BIT(3)
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#define CR_SSHIFT BIT(4)
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#define CR_DFM BIT(6)
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#define CR_FSEL BIT(7)
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#define CR_FTHRES_SHIFT 8
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#define CR_TEIE BIT(16)
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#define CR_TCIE BIT(17)
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#define CR_FTIE BIT(18)
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#define CR_SMIE BIT(19)
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#define CR_TOIE BIT(20)
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#define CR_APMS BIT(22)
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#define CR_PRESC_MASK GENMASK(31, 24)
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#define QSPI_DCR 0x04
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#define DCR_FSIZE_MASK GENMASK(20, 16)
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#define QSPI_SR 0x08
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#define SR_TEF BIT(0)
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#define SR_TCF BIT(1)
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#define SR_FTF BIT(2)
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#define SR_SMF BIT(3)
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#define SR_TOF BIT(4)
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#define SR_BUSY BIT(5)
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#define SR_FLEVEL_MASK GENMASK(13, 8)
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#define QSPI_FCR 0x0c
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#define FCR_CTEF BIT(0)
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#define FCR_CTCF BIT(1)
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#define FCR_CSMF BIT(3)
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#define QSPI_DLR 0x10
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#define QSPI_CCR 0x14
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#define CCR_INST_MASK GENMASK(7, 0)
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#define CCR_IMODE_MASK GENMASK(9, 8)
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#define CCR_ADMODE_MASK GENMASK(11, 10)
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#define CCR_ADSIZE_MASK GENMASK(13, 12)
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#define CCR_DCYC_MASK GENMASK(22, 18)
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#define CCR_DMODE_MASK GENMASK(25, 24)
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#define CCR_FMODE_MASK GENMASK(27, 26)
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#define CCR_FMODE_INDW (0U << 26)
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#define CCR_FMODE_INDR (1U << 26)
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#define CCR_FMODE_APM (2U << 26)
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#define CCR_FMODE_MM (3U << 26)
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#define CCR_BUSWIDTH_0 0x0
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#define CCR_BUSWIDTH_1 0x1
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#define CCR_BUSWIDTH_2 0x2
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#define CCR_BUSWIDTH_4 0x3
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#define QSPI_AR 0x18
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#define QSPI_ABR 0x1c
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#define QSPI_DR 0x20
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#define QSPI_PSMKR 0x24
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#define QSPI_PSMAR 0x28
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#define QSPI_PIR 0x2c
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#define QSPI_LPTR 0x30
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#define STM32_QSPI_MAX_MMAP_SZ SZ_256M
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#define STM32_QSPI_MAX_NORCHIP 2
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#define STM32_FIFO_TIMEOUT_US 30000
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#define STM32_BUSY_TIMEOUT_US 100000
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#define STM32_ABT_TIMEOUT_US 100000
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#define STM32_COMP_TIMEOUT_MS 1000
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#define STM32_AUTOSUSPEND_DELAY -1
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struct stm32_qspi_flash {
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u32 cs;
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u32 presc;
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};
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struct stm32_qspi {
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struct device *dev;
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struct spi_controller *ctrl;
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phys_addr_t phys_base;
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void __iomem *io_base;
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void __iomem *mm_base;
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resource_size_t mm_size;
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struct clk *clk;
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u32 clk_rate;
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struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
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struct completion data_completion;
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struct completion match_completion;
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u32 fmode;
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struct dma_chan *dma_chtx;
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struct dma_chan *dma_chrx;
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struct completion dma_completion;
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u32 cr_reg;
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u32 dcr_reg;
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unsigned long status_timeout;
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/*
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* to protect device configuration, could be different between
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* 2 flash access (bk1, bk2)
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*/
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struct mutex lock;
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};
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static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
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{
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struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
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u32 cr, sr;
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cr = readl_relaxed(qspi->io_base + QSPI_CR);
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sr = readl_relaxed(qspi->io_base + QSPI_SR);
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if (cr & CR_SMIE && sr & SR_SMF) {
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/* disable irq */
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cr &= ~CR_SMIE;
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writel_relaxed(cr, qspi->io_base + QSPI_CR);
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complete(&qspi->match_completion);
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return IRQ_HANDLED;
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}
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if (sr & (SR_TEF | SR_TCF)) {
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/* disable irq */
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cr &= ~CR_TCIE & ~CR_TEIE;
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writel_relaxed(cr, qspi->io_base + QSPI_CR);
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complete(&qspi->data_completion);
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}
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return IRQ_HANDLED;
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}
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static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
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{
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*val = readb_relaxed(addr);
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}
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static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
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{
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writeb_relaxed(*val, addr);
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}
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static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
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const struct spi_mem_op *op)
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{
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void (*tx_fifo)(u8 *val, void __iomem *addr);
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u32 len = op->data.nbytes, sr;
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u8 *buf;
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int ret;
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if (op->data.dir == SPI_MEM_DATA_IN) {
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tx_fifo = stm32_qspi_read_fifo;
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buf = op->data.buf.in;
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} else {
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tx_fifo = stm32_qspi_write_fifo;
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buf = (u8 *)op->data.buf.out;
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}
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while (len--) {
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ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
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sr, (sr & SR_FTF), 1,
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STM32_FIFO_TIMEOUT_US);
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if (ret) {
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dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
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len, sr);
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return ret;
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}
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tx_fifo(buf++, qspi->io_base + QSPI_DR);
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}
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return 0;
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}
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static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
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const struct spi_mem_op *op)
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{
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memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
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op->data.nbytes);
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return 0;
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}
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static void stm32_qspi_dma_callback(void *arg)
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{
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struct completion *dma_completion = arg;
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complete(dma_completion);
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}
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static int stm32_qspi_tx_dma(struct stm32_qspi *qspi,
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const struct spi_mem_op *op)
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{
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struct dma_async_tx_descriptor *desc;
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enum dma_transfer_direction dma_dir;
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struct dma_chan *dma_ch;
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struct sg_table sgt;
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dma_cookie_t cookie;
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u32 cr, t_out;
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int err;
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if (op->data.dir == SPI_MEM_DATA_IN) {
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dma_dir = DMA_DEV_TO_MEM;
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dma_ch = qspi->dma_chrx;
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} else {
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dma_dir = DMA_MEM_TO_DEV;
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dma_ch = qspi->dma_chtx;
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}
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/*
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* spi_map_buf return -EINVAL if the buffer is not DMA-able
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* (DMA-able: in vmalloc | kmap | virt_addr_valid)
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*/
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err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt);
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if (err)
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return err;
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desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents,
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dma_dir, DMA_PREP_INTERRUPT);
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if (!desc) {
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err = -ENOMEM;
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goto out_unmap;
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}
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cr = readl_relaxed(qspi->io_base + QSPI_CR);
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reinit_completion(&qspi->dma_completion);
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desc->callback = stm32_qspi_dma_callback;
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desc->callback_param = &qspi->dma_completion;
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cookie = dmaengine_submit(desc);
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err = dma_submit_error(cookie);
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if (err)
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goto out;
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dma_async_issue_pending(dma_ch);
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writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
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t_out = sgt.nents * STM32_COMP_TIMEOUT_MS;
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if (!wait_for_completion_timeout(&qspi->dma_completion,
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msecs_to_jiffies(t_out)))
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err = -ETIMEDOUT;
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if (err)
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dmaengine_terminate_all(dma_ch);
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out:
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writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
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out_unmap:
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spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt);
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return err;
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}
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static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
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{
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if (!op->data.nbytes)
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return 0;
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if (qspi->fmode == CCR_FMODE_MM)
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return stm32_qspi_tx_mm(qspi, op);
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else if (((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) ||
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(op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx)) &&
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op->data.nbytes > 4)
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if (!stm32_qspi_tx_dma(qspi, op))
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return 0;
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return stm32_qspi_tx_poll(qspi, op);
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}
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static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
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{
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u32 sr;
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return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
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!(sr & SR_BUSY), 1,
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STM32_BUSY_TIMEOUT_US);
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}
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static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi)
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{
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u32 cr, sr;
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int err = 0;
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if ((readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF) ||
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qspi->fmode == CCR_FMODE_APM)
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goto out;
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reinit_completion(&qspi->data_completion);
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cr = readl_relaxed(qspi->io_base + QSPI_CR);
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writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
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if (!wait_for_completion_timeout(&qspi->data_completion,
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msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) {
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err = -ETIMEDOUT;
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} else {
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sr = readl_relaxed(qspi->io_base + QSPI_SR);
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if (sr & SR_TEF)
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err = -EIO;
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}
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out:
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/* clear flags */
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writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
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if (!err)
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err = stm32_qspi_wait_nobusy(qspi);
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return err;
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}
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static int stm32_qspi_wait_poll_status(struct stm32_qspi *qspi)
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{
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u32 cr;
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reinit_completion(&qspi->match_completion);
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cr = readl_relaxed(qspi->io_base + QSPI_CR);
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writel_relaxed(cr | CR_SMIE, qspi->io_base + QSPI_CR);
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if (!wait_for_completion_timeout(&qspi->match_completion,
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msecs_to_jiffies(qspi->status_timeout)))
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return -ETIMEDOUT;
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writel_relaxed(FCR_CSMF, qspi->io_base + QSPI_FCR);
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return 0;
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}
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static int stm32_qspi_get_mode(u8 buswidth)
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{
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if (buswidth == 4)
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return CCR_BUSWIDTH_4;
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return buswidth;
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}
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static int stm32_qspi_send(struct spi_device *spi, const struct spi_mem_op *op)
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{
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struct stm32_qspi *qspi = spi_controller_get_devdata(spi->master);
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struct stm32_qspi_flash *flash = &qspi->flash[spi->chip_select];
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u32 ccr, cr;
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int timeout, err = 0, err_poll_status = 0;
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dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
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op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
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op->dummy.buswidth, op->data.buswidth,
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op->addr.val, op->data.nbytes);
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cr = readl_relaxed(qspi->io_base + QSPI_CR);
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cr &= ~CR_PRESC_MASK & ~CR_FSEL;
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cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
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cr |= FIELD_PREP(CR_FSEL, flash->cs);
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writel_relaxed(cr, qspi->io_base + QSPI_CR);
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if (op->data.nbytes)
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writel_relaxed(op->data.nbytes - 1,
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qspi->io_base + QSPI_DLR);
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ccr = qspi->fmode;
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ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
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ccr |= FIELD_PREP(CCR_IMODE_MASK,
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stm32_qspi_get_mode(op->cmd.buswidth));
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if (op->addr.nbytes) {
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ccr |= FIELD_PREP(CCR_ADMODE_MASK,
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stm32_qspi_get_mode(op->addr.buswidth));
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ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
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}
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if (op->dummy.nbytes)
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ccr |= FIELD_PREP(CCR_DCYC_MASK,
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op->dummy.nbytes * 8 / op->dummy.buswidth);
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if (op->data.nbytes) {
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ccr |= FIELD_PREP(CCR_DMODE_MASK,
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stm32_qspi_get_mode(op->data.buswidth));
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}
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writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
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if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
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writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
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if (qspi->fmode == CCR_FMODE_APM)
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err_poll_status = stm32_qspi_wait_poll_status(qspi);
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err = stm32_qspi_tx(qspi, op);
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/*
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* Abort in:
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* -error case
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* -read memory map: prefetching must be stopped if we read the last
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* byte of device (device size - fifo size). like device size is not
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* knows, the prefetching is always stop.
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*/
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if (err || err_poll_status || qspi->fmode == CCR_FMODE_MM)
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goto abort;
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|
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/* wait end of tx in indirect mode */
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err = stm32_qspi_wait_cmd(qspi);
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if (err)
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goto abort;
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return 0;
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abort:
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cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
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writel_relaxed(cr, qspi->io_base + QSPI_CR);
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/* wait clear of abort bit by hw */
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timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
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cr, !(cr & CR_ABORT), 1,
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STM32_ABT_TIMEOUT_US);
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writel_relaxed(FCR_CTCF | FCR_CSMF, qspi->io_base + QSPI_FCR);
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if (err || err_poll_status || timeout)
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dev_err(qspi->dev, "%s err:%d err_poll_status:%d abort timeout:%d\n",
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__func__, err, err_poll_status, timeout);
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return err;
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}
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|
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static int stm32_qspi_poll_status(struct spi_mem *mem, const struct spi_mem_op *op,
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u16 mask, u16 match,
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unsigned long initial_delay_us,
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unsigned long polling_rate_us,
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unsigned long timeout_ms)
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{
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struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
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int ret;
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if (!spi_mem_supports_op(mem, op))
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return -EOPNOTSUPP;
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|
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ret = pm_runtime_resume_and_get(qspi->dev);
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if (ret < 0)
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return ret;
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|
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mutex_lock(&qspi->lock);
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|
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writel_relaxed(mask, qspi->io_base + QSPI_PSMKR);
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writel_relaxed(match, qspi->io_base + QSPI_PSMAR);
|
|
qspi->fmode = CCR_FMODE_APM;
|
|
qspi->status_timeout = timeout_ms;
|
|
|
|
ret = stm32_qspi_send(mem->spi, op);
|
|
mutex_unlock(&qspi->lock);
|
|
|
|
pm_runtime_mark_last_busy(qspi->dev);
|
|
pm_runtime_put_autosuspend(qspi->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
|
|
{
|
|
struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
|
|
int ret;
|
|
|
|
ret = pm_runtime_resume_and_get(qspi->dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
mutex_lock(&qspi->lock);
|
|
if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes)
|
|
qspi->fmode = CCR_FMODE_INDR;
|
|
else
|
|
qspi->fmode = CCR_FMODE_INDW;
|
|
|
|
ret = stm32_qspi_send(mem->spi, op);
|
|
mutex_unlock(&qspi->lock);
|
|
|
|
pm_runtime_mark_last_busy(qspi->dev);
|
|
pm_runtime_put_autosuspend(qspi->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int stm32_qspi_dirmap_create(struct spi_mem_dirmap_desc *desc)
|
|
{
|
|
struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->master);
|
|
|
|
if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
|
|
return -EOPNOTSUPP;
|
|
|
|
/* should never happen, as mm_base == null is an error probe exit condition */
|
|
if (!qspi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
|
|
return -EOPNOTSUPP;
|
|
|
|
if (!qspi->mm_size)
|
|
return -EOPNOTSUPP;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static ssize_t stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc *desc,
|
|
u64 offs, size_t len, void *buf)
|
|
{
|
|
struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->master);
|
|
struct spi_mem_op op;
|
|
u32 addr_max;
|
|
int ret;
|
|
|
|
ret = pm_runtime_resume_and_get(qspi->dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
mutex_lock(&qspi->lock);
|
|
/* make a local copy of desc op_tmpl and complete dirmap rdesc
|
|
* spi_mem_op template with offs, len and *buf in order to get
|
|
* all needed transfer information into struct spi_mem_op
|
|
*/
|
|
memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op));
|
|
dev_dbg(qspi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf);
|
|
|
|
op.data.nbytes = len;
|
|
op.addr.val = desc->info.offset + offs;
|
|
op.data.buf.in = buf;
|
|
|
|
addr_max = op.addr.val + op.data.nbytes + 1;
|
|
if (addr_max < qspi->mm_size && op.addr.buswidth)
|
|
qspi->fmode = CCR_FMODE_MM;
|
|
else
|
|
qspi->fmode = CCR_FMODE_INDR;
|
|
|
|
ret = stm32_qspi_send(desc->mem->spi, &op);
|
|
mutex_unlock(&qspi->lock);
|
|
|
|
pm_runtime_mark_last_busy(qspi->dev);
|
|
pm_runtime_put_autosuspend(qspi->dev);
|
|
|
|
return ret ?: len;
|
|
}
|
|
|
|
static int stm32_qspi_transfer_one_message(struct spi_controller *ctrl,
|
|
struct spi_message *msg)
|
|
{
|
|
struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
|
|
struct spi_transfer *transfer;
|
|
struct spi_device *spi = msg->spi;
|
|
struct spi_mem_op op;
|
|
int ret = 0;
|
|
|
|
if (!spi->cs_gpiod)
|
|
return -EOPNOTSUPP;
|
|
|
|
ret = pm_runtime_resume_and_get(qspi->dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
mutex_lock(&qspi->lock);
|
|
|
|
gpiod_set_value_cansleep(spi->cs_gpiod, true);
|
|
|
|
list_for_each_entry(transfer, &msg->transfers, transfer_list) {
|
|
u8 dummy_bytes = 0;
|
|
|
|
memset(&op, 0, sizeof(op));
|
|
|
|
dev_dbg(qspi->dev, "tx_buf:%p tx_nbits:%d rx_buf:%p rx_nbits:%d len:%d dummy_data:%d\n",
|
|
transfer->tx_buf, transfer->tx_nbits,
|
|
transfer->rx_buf, transfer->rx_nbits,
|
|
transfer->len, transfer->dummy_data);
|
|
|
|
/*
|
|
* QSPI hardware supports dummy bytes transfer.
|
|
* If current transfer is dummy byte, merge it with the next
|
|
* transfer in order to take into account QSPI block constraint
|
|
*/
|
|
if (transfer->dummy_data) {
|
|
op.dummy.buswidth = transfer->tx_nbits;
|
|
op.dummy.nbytes = transfer->len;
|
|
dummy_bytes = transfer->len;
|
|
|
|
/* if happens, means that message is not correctly built */
|
|
if (list_is_last(&transfer->transfer_list, &msg->transfers)) {
|
|
ret = -EINVAL;
|
|
goto end_of_transfer;
|
|
}
|
|
|
|
transfer = list_next_entry(transfer, transfer_list);
|
|
}
|
|
|
|
op.data.nbytes = transfer->len;
|
|
|
|
if (transfer->rx_buf) {
|
|
qspi->fmode = CCR_FMODE_INDR;
|
|
op.data.buswidth = transfer->rx_nbits;
|
|
op.data.dir = SPI_MEM_DATA_IN;
|
|
op.data.buf.in = transfer->rx_buf;
|
|
} else {
|
|
qspi->fmode = CCR_FMODE_INDW;
|
|
op.data.buswidth = transfer->tx_nbits;
|
|
op.data.dir = SPI_MEM_DATA_OUT;
|
|
op.data.buf.out = transfer->tx_buf;
|
|
}
|
|
|
|
ret = stm32_qspi_send(spi, &op);
|
|
if (ret)
|
|
goto end_of_transfer;
|
|
|
|
msg->actual_length += transfer->len + dummy_bytes;
|
|
}
|
|
|
|
end_of_transfer:
|
|
gpiod_set_value_cansleep(spi->cs_gpiod, false);
|
|
|
|
mutex_unlock(&qspi->lock);
|
|
|
|
msg->status = ret;
|
|
spi_finalize_current_message(ctrl);
|
|
|
|
pm_runtime_mark_last_busy(qspi->dev);
|
|
pm_runtime_put_autosuspend(qspi->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int stm32_qspi_setup(struct spi_device *spi)
|
|
{
|
|
struct spi_controller *ctrl = spi->master;
|
|
struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
|
|
struct stm32_qspi_flash *flash;
|
|
u32 presc, mode;
|
|
int ret;
|
|
|
|
if (ctrl->busy)
|
|
return -EBUSY;
|
|
|
|
if (!spi->max_speed_hz)
|
|
return -EINVAL;
|
|
|
|
mode = spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL);
|
|
if ((mode == SPI_TX_OCTAL || mode == SPI_RX_OCTAL) ||
|
|
((mode == (SPI_TX_OCTAL | SPI_RX_OCTAL)) &&
|
|
gpiod_count(qspi->dev, "cs") == -ENOENT)) {
|
|
dev_err(qspi->dev, "spi-rx-bus-width\\/spi-tx-bus-width\\/cs-gpios\n");
|
|
dev_err(qspi->dev, "configuration not supported\n");
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = pm_runtime_resume_and_get(qspi->dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
|
|
|
|
flash = &qspi->flash[spi->chip_select];
|
|
flash->cs = spi->chip_select;
|
|
flash->presc = presc;
|
|
|
|
mutex_lock(&qspi->lock);
|
|
qspi->cr_reg = CR_APMS | 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
|
|
|
|
/*
|
|
* Dual flash mode is only enable in case SPI_TX_OCTAL and SPI_TX_OCTAL
|
|
* are both set in spi->mode and "cs-gpios" properties is found in DT
|
|
*/
|
|
if (mode == (SPI_TX_OCTAL | SPI_RX_OCTAL)) {
|
|
qspi->cr_reg |= CR_DFM;
|
|
dev_dbg(qspi->dev, "Dual flash mode enable");
|
|
}
|
|
|
|
writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
|
|
|
|
/* set dcr fsize to max address */
|
|
qspi->dcr_reg = DCR_FSIZE_MASK;
|
|
writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
|
|
mutex_unlock(&qspi->lock);
|
|
|
|
pm_runtime_mark_last_busy(qspi->dev);
|
|
pm_runtime_put_autosuspend(qspi->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_qspi_dma_setup(struct stm32_qspi *qspi)
|
|
{
|
|
struct dma_slave_config dma_cfg;
|
|
struct device *dev = qspi->dev;
|
|
int ret = 0;
|
|
|
|
memset(&dma_cfg, 0, sizeof(dma_cfg));
|
|
|
|
dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
|
dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
|
dma_cfg.src_addr = qspi->phys_base + QSPI_DR;
|
|
dma_cfg.dst_addr = qspi->phys_base + QSPI_DR;
|
|
dma_cfg.src_maxburst = 4;
|
|
dma_cfg.dst_maxburst = 4;
|
|
|
|
qspi->dma_chrx = dma_request_chan(dev, "rx");
|
|
if (IS_ERR(qspi->dma_chrx)) {
|
|
ret = PTR_ERR(qspi->dma_chrx);
|
|
qspi->dma_chrx = NULL;
|
|
if (ret == -EPROBE_DEFER)
|
|
goto out;
|
|
} else {
|
|
if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) {
|
|
dev_err(dev, "dma rx config failed\n");
|
|
dma_release_channel(qspi->dma_chrx);
|
|
qspi->dma_chrx = NULL;
|
|
}
|
|
}
|
|
|
|
qspi->dma_chtx = dma_request_chan(dev, "tx");
|
|
if (IS_ERR(qspi->dma_chtx)) {
|
|
ret = PTR_ERR(qspi->dma_chtx);
|
|
qspi->dma_chtx = NULL;
|
|
} else {
|
|
if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) {
|
|
dev_err(dev, "dma tx config failed\n");
|
|
dma_release_channel(qspi->dma_chtx);
|
|
qspi->dma_chtx = NULL;
|
|
}
|
|
}
|
|
|
|
out:
|
|
init_completion(&qspi->dma_completion);
|
|
|
|
if (ret != -EPROBE_DEFER)
|
|
ret = 0;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void stm32_qspi_dma_free(struct stm32_qspi *qspi)
|
|
{
|
|
if (qspi->dma_chtx)
|
|
dma_release_channel(qspi->dma_chtx);
|
|
if (qspi->dma_chrx)
|
|
dma_release_channel(qspi->dma_chrx);
|
|
}
|
|
|
|
/*
|
|
* no special host constraint, so use default spi_mem_default_supports_op
|
|
* to check supported mode.
|
|
*/
|
|
static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
|
|
.exec_op = stm32_qspi_exec_op,
|
|
.dirmap_create = stm32_qspi_dirmap_create,
|
|
.dirmap_read = stm32_qspi_dirmap_read,
|
|
.poll_status = stm32_qspi_poll_status,
|
|
};
|
|
|
|
static int stm32_qspi_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct spi_controller *ctrl;
|
|
struct reset_control *rstc;
|
|
struct stm32_qspi *qspi;
|
|
struct resource *res;
|
|
int ret, irq;
|
|
|
|
ctrl = devm_spi_alloc_master(dev, sizeof(*qspi));
|
|
if (!ctrl)
|
|
return -ENOMEM;
|
|
|
|
qspi = spi_controller_get_devdata(ctrl);
|
|
qspi->ctrl = ctrl;
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
|
|
qspi->io_base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(qspi->io_base))
|
|
return PTR_ERR(qspi->io_base);
|
|
|
|
qspi->phys_base = res->start;
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
|
|
qspi->mm_base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(qspi->mm_base))
|
|
return PTR_ERR(qspi->mm_base);
|
|
|
|
qspi->mm_size = resource_size(res);
|
|
if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ)
|
|
return -EINVAL;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
|
|
dev_name(dev), qspi);
|
|
if (ret) {
|
|
dev_err(dev, "failed to request irq\n");
|
|
return ret;
|
|
}
|
|
|
|
init_completion(&qspi->data_completion);
|
|
init_completion(&qspi->match_completion);
|
|
|
|
qspi->clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(qspi->clk))
|
|
return PTR_ERR(qspi->clk);
|
|
|
|
qspi->clk_rate = clk_get_rate(qspi->clk);
|
|
if (!qspi->clk_rate)
|
|
return -EINVAL;
|
|
|
|
ret = clk_prepare_enable(qspi->clk);
|
|
if (ret) {
|
|
dev_err(dev, "can not enable the clock\n");
|
|
return ret;
|
|
}
|
|
|
|
rstc = devm_reset_control_get_exclusive(dev, NULL);
|
|
if (IS_ERR(rstc)) {
|
|
ret = PTR_ERR(rstc);
|
|
if (ret == -EPROBE_DEFER)
|
|
goto err_clk_disable;
|
|
} else {
|
|
reset_control_assert(rstc);
|
|
udelay(2);
|
|
reset_control_deassert(rstc);
|
|
}
|
|
|
|
qspi->dev = dev;
|
|
platform_set_drvdata(pdev, qspi);
|
|
ret = stm32_qspi_dma_setup(qspi);
|
|
if (ret)
|
|
goto err_dma_free;
|
|
|
|
mutex_init(&qspi->lock);
|
|
|
|
ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL
|
|
| SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_OCTAL;
|
|
ctrl->setup = stm32_qspi_setup;
|
|
ctrl->bus_num = -1;
|
|
ctrl->mem_ops = &stm32_qspi_mem_ops;
|
|
ctrl->use_gpio_descriptors = true;
|
|
ctrl->transfer_one_message = stm32_qspi_transfer_one_message;
|
|
ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
|
|
ctrl->dev.of_node = dev->of_node;
|
|
|
|
pm_runtime_set_autosuspend_delay(dev, STM32_AUTOSUSPEND_DELAY);
|
|
pm_runtime_use_autosuspend(dev);
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
pm_runtime_get_noresume(dev);
|
|
|
|
ret = spi_register_master(ctrl);
|
|
if (ret)
|
|
goto err_pm_runtime_free;
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
pm_runtime_put_autosuspend(dev);
|
|
|
|
return 0;
|
|
|
|
err_pm_runtime_free:
|
|
pm_runtime_get_sync(qspi->dev);
|
|
/* disable qspi */
|
|
writel_relaxed(0, qspi->io_base + QSPI_CR);
|
|
mutex_destroy(&qspi->lock);
|
|
pm_runtime_put_noidle(qspi->dev);
|
|
pm_runtime_disable(qspi->dev);
|
|
pm_runtime_set_suspended(qspi->dev);
|
|
pm_runtime_dont_use_autosuspend(qspi->dev);
|
|
err_dma_free:
|
|
stm32_qspi_dma_free(qspi);
|
|
err_clk_disable:
|
|
clk_disable_unprepare(qspi->clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int stm32_qspi_remove(struct platform_device *pdev)
|
|
{
|
|
struct stm32_qspi *qspi = platform_get_drvdata(pdev);
|
|
|
|
pm_runtime_get_sync(qspi->dev);
|
|
spi_unregister_master(qspi->ctrl);
|
|
/* disable qspi */
|
|
writel_relaxed(0, qspi->io_base + QSPI_CR);
|
|
stm32_qspi_dma_free(qspi);
|
|
mutex_destroy(&qspi->lock);
|
|
pm_runtime_put_noidle(qspi->dev);
|
|
pm_runtime_disable(qspi->dev);
|
|
pm_runtime_set_suspended(qspi->dev);
|
|
pm_runtime_dont_use_autosuspend(qspi->dev);
|
|
clk_disable_unprepare(qspi->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused stm32_qspi_runtime_suspend(struct device *dev)
|
|
{
|
|
struct stm32_qspi *qspi = dev_get_drvdata(dev);
|
|
|
|
clk_disable_unprepare(qspi->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused stm32_qspi_runtime_resume(struct device *dev)
|
|
{
|
|
struct stm32_qspi *qspi = dev_get_drvdata(dev);
|
|
|
|
return clk_prepare_enable(qspi->clk);
|
|
}
|
|
|
|
static int __maybe_unused stm32_qspi_suspend(struct device *dev)
|
|
{
|
|
pinctrl_pm_select_sleep_state(dev);
|
|
|
|
return pm_runtime_force_suspend(dev);
|
|
}
|
|
|
|
static int __maybe_unused stm32_qspi_resume(struct device *dev)
|
|
{
|
|
struct stm32_qspi *qspi = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = pm_runtime_force_resume(dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
pinctrl_pm_select_default_state(dev);
|
|
|
|
ret = pm_runtime_resume_and_get(dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
|
|
writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
pm_runtime_put_autosuspend(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
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static const struct dev_pm_ops stm32_qspi_pm_ops = {
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SET_RUNTIME_PM_OPS(stm32_qspi_runtime_suspend,
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stm32_qspi_runtime_resume, NULL)
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SET_SYSTEM_SLEEP_PM_OPS(stm32_qspi_suspend, stm32_qspi_resume)
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};
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|
|
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static const struct of_device_id stm32_qspi_match[] = {
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|
{.compatible = "st,stm32f469-qspi"},
|
|
{}
|
|
};
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MODULE_DEVICE_TABLE(of, stm32_qspi_match);
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|
|
|
static struct platform_driver stm32_qspi_driver = {
|
|
.probe = stm32_qspi_probe,
|
|
.remove = stm32_qspi_remove,
|
|
.driver = {
|
|
.name = "stm32-qspi",
|
|
.of_match_table = stm32_qspi_match,
|
|
.pm = &stm32_qspi_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(stm32_qspi_driver);
|
|
|
|
MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
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|
MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
|
|
MODULE_LICENSE("GPL v2");
|