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![Li-hao Kuo](/assets/img/avatar_default.png)
remove spin_lock_irq spin_unlock_irq and variable in the irq funciton Signed-off-by: Li-hao Kuo <lhjeff911@gmail.com> Link: https://lore.kernel.org/r/f9991d6064d892d22ac7c2dfabe16309e9d03888.1650010304.git.lhjeff911@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
578 lines
17 KiB
C
578 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (c) 2021 Sunplus Inc.
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// Author: Li-hao Kuo <lhjeff911@gmail.com>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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#define SP7021_DATA_RDY_REG 0x0044
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#define SP7021_SLAVE_DMA_CTRL_REG 0x0048
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#define SP7021_SLAVE_DMA_LENGTH_REG 0x004c
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#define SP7021_SLAVE_DMA_ADDR_REG 0x004c
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#define SP7021_SLAVE_DATA_RDY BIT(0)
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#define SP7021_SLAVE_SW_RST BIT(1)
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#define SP7021_SLA_DMA_W_INT BIT(8)
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#define SP7021_SLAVE_CLR_INT BIT(8)
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#define SP7021_SLAVE_DMA_EN BIT(0)
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#define SP7021_SLAVE_DMA_RW BIT(6)
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#define SP7021_SLAVE_DMA_CMD GENMASK(3, 2)
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#define SP7021_FIFO_REG 0x0034
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#define SP7021_SPI_STATUS_REG 0x0038
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#define SP7021_SPI_CONFIG_REG 0x003c
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#define SP7021_INT_BUSY_REG 0x004c
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#define SP7021_DMA_CTRL_REG 0x0050
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#define SP7021_SPI_START_FD BIT(0)
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#define SP7021_FD_SW_RST BIT(1)
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#define SP7021_TX_EMP_FLAG BIT(2)
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#define SP7021_RX_EMP_FLAG BIT(4)
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#define SP7021_RX_FULL_FLAG BIT(5)
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#define SP7021_FINISH_FLAG BIT(6)
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#define SP7021_TX_CNT_MASK GENMASK(11, 8)
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#define SP7021_RX_CNT_MASK GENMASK(15, 12)
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#define SP7021_TX_LEN_MASK GENMASK(23, 16)
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#define SP7021_GET_LEN_MASK GENMASK(31, 24)
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#define SP7021_SET_TX_LEN GENMASK(23, 16)
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#define SP7021_SET_XFER_LEN GENMASK(31, 24)
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#define SP7021_CPOL_FD BIT(0)
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#define SP7021_CPHA_R BIT(1)
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#define SP7021_CPHA_W BIT(2)
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#define SP7021_LSB_SEL BIT(4)
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#define SP7021_CS_POR BIT(5)
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#define SP7021_FD_SEL BIT(6)
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#define SP7021_RX_UNIT GENMASK(8, 7)
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#define SP7021_TX_UNIT GENMASK(10, 9)
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#define SP7021_TX_EMP_FLAG_MASK BIT(11)
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#define SP7021_RX_FULL_FLAG_MASK BIT(14)
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#define SP7021_FINISH_FLAG_MASK BIT(15)
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#define SP7021_CLEAN_RW_BYTE GENMASK(10, 7)
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#define SP7021_CLEAN_FLUG_MASK GENMASK(15, 11)
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#define SP7021_CLK_MASK GENMASK(31, 16)
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#define SP7021_INT_BYPASS BIT(3)
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#define SP7021_CLR_MASTER_INT BIT(6)
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#define SP7021_SPI_DATA_SIZE (255)
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#define SP7021_FIFO_DATA_LEN (16)
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enum {
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SP7021_MASTER_MODE = 0,
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SP7021_SLAVE_MODE = 1,
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};
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struct sp7021_spi_ctlr {
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struct device *dev;
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struct spi_controller *ctlr;
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void __iomem *m_base;
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void __iomem *s_base;
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u32 xfer_conf;
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int mode;
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int m_irq;
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int s_irq;
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struct clk *spi_clk;
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struct reset_control *rstc;
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// data xfer lock
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struct mutex buf_lock;
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struct completion isr_done;
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struct completion slave_isr;
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unsigned int rx_cur_len;
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unsigned int tx_cur_len;
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unsigned int data_unit;
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const u8 *tx_buf;
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u8 *rx_buf;
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};
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static irqreturn_t sp7021_spi_slave_irq(int irq, void *dev)
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{
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struct sp7021_spi_ctlr *pspim = dev;
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unsigned int data_status;
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data_status = readl(pspim->s_base + SP7021_DATA_RDY_REG);
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data_status |= SP7021_SLAVE_CLR_INT;
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writel(data_status , pspim->s_base + SP7021_DATA_RDY_REG);
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complete(&pspim->slave_isr);
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return IRQ_HANDLED;
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}
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static int sp7021_spi_slave_abort(struct spi_controller *ctlr)
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{
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struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
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complete(&pspim->slave_isr);
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complete(&pspim->isr_done);
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return 0;
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}
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static int sp7021_spi_slave_tx(struct spi_device *spi, struct spi_transfer *xfer)
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{
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struct sp7021_spi_ctlr *pspim = spi_controller_get_devdata(spi->controller);
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u32 value;
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reinit_completion(&pspim->slave_isr);
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value = SP7021_SLAVE_DMA_EN | SP7021_SLAVE_DMA_RW | FIELD_PREP(SP7021_SLAVE_DMA_CMD, 3);
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writel(value, pspim->s_base + SP7021_SLAVE_DMA_CTRL_REG);
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writel(xfer->len, pspim->s_base + SP7021_SLAVE_DMA_LENGTH_REG);
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writel(xfer->tx_dma, pspim->s_base + SP7021_SLAVE_DMA_ADDR_REG);
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value = readl(pspim->s_base + SP7021_DATA_RDY_REG);
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value |= SP7021_SLAVE_DATA_RDY;
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writel(value, pspim->s_base + SP7021_DATA_RDY_REG);
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if (wait_for_completion_interruptible(&pspim->isr_done)) {
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dev_err(&spi->dev, "%s() wait_for_completion err\n", __func__);
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return -EINTR;
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}
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return 0;
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}
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static int sp7021_spi_slave_rx(struct spi_device *spi, struct spi_transfer *xfer)
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{
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struct sp7021_spi_ctlr *pspim = spi_controller_get_devdata(spi->controller);
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u32 value;
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reinit_completion(&pspim->isr_done);
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value = SP7021_SLAVE_DMA_EN | FIELD_PREP(SP7021_SLAVE_DMA_CMD, 3);
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writel(value, pspim->s_base + SP7021_SLAVE_DMA_CTRL_REG);
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writel(xfer->len, pspim->s_base + SP7021_SLAVE_DMA_LENGTH_REG);
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writel(xfer->rx_dma, pspim->s_base + SP7021_SLAVE_DMA_ADDR_REG);
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if (wait_for_completion_interruptible(&pspim->isr_done)) {
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dev_err(&spi->dev, "%s() wait_for_completion err\n", __func__);
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return -EINTR;
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}
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writel(SP7021_SLAVE_SW_RST, pspim->s_base + SP7021_SLAVE_DMA_CTRL_REG);
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return 0;
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}
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static void sp7021_spi_master_rb(struct sp7021_spi_ctlr *pspim, unsigned int len)
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{
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int i;
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for (i = 0; i < len; i++) {
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pspim->rx_buf[pspim->rx_cur_len] =
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readl(pspim->m_base + SP7021_FIFO_REG);
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pspim->rx_cur_len++;
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}
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}
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static void sp7021_spi_master_wb(struct sp7021_spi_ctlr *pspim, unsigned int len)
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{
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int i;
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for (i = 0; i < len; i++) {
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writel(pspim->tx_buf[pspim->tx_cur_len],
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pspim->m_base + SP7021_FIFO_REG);
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pspim->tx_cur_len++;
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}
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}
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static irqreturn_t sp7021_spi_master_irq(int irq, void *dev)
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{
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struct sp7021_spi_ctlr *pspim = dev;
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unsigned int tx_cnt, total_len;
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unsigned int tx_len, rx_cnt;
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unsigned int fd_status;
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bool isrdone = false;
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u32 value;
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fd_status = readl(pspim->m_base + SP7021_SPI_STATUS_REG);
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tx_cnt = FIELD_GET(SP7021_TX_CNT_MASK, fd_status);
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tx_len = FIELD_GET(SP7021_TX_LEN_MASK, fd_status);
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total_len = FIELD_GET(SP7021_GET_LEN_MASK, fd_status);
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if ((fd_status & SP7021_TX_EMP_FLAG) && (fd_status & SP7021_RX_EMP_FLAG) && total_len == 0)
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return IRQ_NONE;
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if (tx_len == 0 && total_len == 0)
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return IRQ_NONE;
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rx_cnt = FIELD_GET(SP7021_RX_CNT_MASK, fd_status);
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if (fd_status & SP7021_RX_FULL_FLAG)
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rx_cnt = pspim->data_unit;
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tx_cnt = min(tx_len - pspim->tx_cur_len, pspim->data_unit - tx_cnt);
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dev_dbg(pspim->dev, "fd_st=0x%x rx_c:%d tx_c:%d tx_l:%d",
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fd_status, rx_cnt, tx_cnt, tx_len);
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if (rx_cnt > 0)
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sp7021_spi_master_rb(pspim, rx_cnt);
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if (tx_cnt > 0)
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sp7021_spi_master_wb(pspim, tx_cnt);
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fd_status = readl(pspim->m_base + SP7021_SPI_STATUS_REG);
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tx_len = FIELD_GET(SP7021_TX_LEN_MASK, fd_status);
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total_len = FIELD_GET(SP7021_GET_LEN_MASK, fd_status);
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if (fd_status & SP7021_FINISH_FLAG || tx_len == pspim->tx_cur_len) {
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while (total_len != pspim->rx_cur_len) {
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fd_status = readl(pspim->m_base + SP7021_SPI_STATUS_REG);
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total_len = FIELD_GET(SP7021_GET_LEN_MASK, fd_status);
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if (fd_status & SP7021_RX_FULL_FLAG)
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rx_cnt = pspim->data_unit;
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else
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rx_cnt = FIELD_GET(SP7021_RX_CNT_MASK, fd_status);
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if (rx_cnt > 0)
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sp7021_spi_master_rb(pspim, rx_cnt);
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}
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value = readl(pspim->m_base + SP7021_INT_BUSY_REG);
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value |= SP7021_CLR_MASTER_INT;
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writel(value, pspim->m_base + SP7021_INT_BUSY_REG);
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writel(SP7021_FINISH_FLAG, pspim->m_base + SP7021_SPI_STATUS_REG);
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isrdone = true;
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}
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if (isrdone)
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complete(&pspim->isr_done);
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return IRQ_HANDLED;
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}
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static void sp7021_prep_transfer(struct spi_controller *ctlr, struct spi_device *spi)
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{
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struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
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pspim->tx_cur_len = 0;
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pspim->rx_cur_len = 0;
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pspim->data_unit = SP7021_FIFO_DATA_LEN;
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}
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// preliminary set CS, CPOL, CPHA and LSB
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static int sp7021_spi_controller_prepare_message(struct spi_controller *ctlr,
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struct spi_message *msg)
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{
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struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
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struct spi_device *s = msg->spi;
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u32 valus, rs = 0;
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valus = readl(pspim->m_base + SP7021_SPI_STATUS_REG);
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valus |= SP7021_FD_SW_RST;
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writel(valus, pspim->m_base + SP7021_SPI_STATUS_REG);
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rs |= SP7021_FD_SEL;
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if (s->mode & SPI_CPOL)
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rs |= SP7021_CPOL_FD;
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if (s->mode & SPI_LSB_FIRST)
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rs |= SP7021_LSB_SEL;
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if (s->mode & SPI_CS_HIGH)
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rs |= SP7021_CS_POR;
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if (s->mode & SPI_CPHA)
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rs |= SP7021_CPHA_R;
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else
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rs |= SP7021_CPHA_W;
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rs |= FIELD_PREP(SP7021_TX_UNIT, 0) | FIELD_PREP(SP7021_RX_UNIT, 0);
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pspim->xfer_conf = rs;
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if (pspim->xfer_conf & SP7021_CPOL_FD)
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writel(pspim->xfer_conf, pspim->m_base + SP7021_SPI_CONFIG_REG);
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return 0;
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}
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static void sp7021_spi_setup_clk(struct spi_controller *ctlr, struct spi_transfer *xfer)
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{
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struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
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u32 clk_rate, clk_sel, div;
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clk_rate = clk_get_rate(pspim->spi_clk);
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div = max(2U, clk_rate / xfer->speed_hz);
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clk_sel = (div / 2) - 1;
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pspim->xfer_conf &= ~SP7021_CLK_MASK;
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pspim->xfer_conf |= FIELD_PREP(SP7021_CLK_MASK, clk_sel);
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writel(pspim->xfer_conf, pspim->m_base + SP7021_SPI_CONFIG_REG);
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}
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static int sp7021_spi_master_transfer_one(struct spi_controller *ctlr, struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
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unsigned long timeout = msecs_to_jiffies(1000);
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unsigned int xfer_cnt, xfer_len, last_len;
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unsigned int i, len_temp;
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u32 reg_temp;
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xfer_cnt = xfer->len / SP7021_SPI_DATA_SIZE;
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last_len = xfer->len % SP7021_SPI_DATA_SIZE;
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for (i = 0; i <= xfer_cnt; i++) {
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mutex_lock(&pspim->buf_lock);
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sp7021_prep_transfer(ctlr, spi);
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sp7021_spi_setup_clk(ctlr, xfer);
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reinit_completion(&pspim->isr_done);
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if (i == xfer_cnt)
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xfer_len = last_len;
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else
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xfer_len = SP7021_SPI_DATA_SIZE;
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pspim->tx_buf = xfer->tx_buf + i * SP7021_SPI_DATA_SIZE;
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pspim->rx_buf = xfer->rx_buf + i * SP7021_SPI_DATA_SIZE;
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if (pspim->tx_cur_len < xfer_len) {
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len_temp = min(pspim->data_unit, xfer_len);
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sp7021_spi_master_wb(pspim, len_temp);
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}
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reg_temp = readl(pspim->m_base + SP7021_SPI_CONFIG_REG);
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reg_temp &= ~SP7021_CLEAN_RW_BYTE;
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reg_temp &= ~SP7021_CLEAN_FLUG_MASK;
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reg_temp |= SP7021_FD_SEL | SP7021_FINISH_FLAG_MASK |
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SP7021_TX_EMP_FLAG_MASK | SP7021_RX_FULL_FLAG_MASK |
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FIELD_PREP(SP7021_TX_UNIT, 0) | FIELD_PREP(SP7021_RX_UNIT, 0);
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writel(reg_temp, pspim->m_base + SP7021_SPI_CONFIG_REG);
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reg_temp = FIELD_PREP(SP7021_SET_TX_LEN, xfer_len) |
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FIELD_PREP(SP7021_SET_XFER_LEN, xfer_len) |
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SP7021_SPI_START_FD;
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writel(reg_temp, pspim->m_base + SP7021_SPI_STATUS_REG);
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if (!wait_for_completion_interruptible_timeout(&pspim->isr_done, timeout)) {
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dev_err(&spi->dev, "wait_for_completion err\n");
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mutex_unlock(&pspim->buf_lock);
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return -ETIMEDOUT;
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}
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reg_temp = readl(pspim->m_base + SP7021_SPI_STATUS_REG);
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if (reg_temp & SP7021_FINISH_FLAG) {
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writel(SP7021_FINISH_FLAG, pspim->m_base + SP7021_SPI_STATUS_REG);
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writel(readl(pspim->m_base + SP7021_SPI_CONFIG_REG) &
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SP7021_CLEAN_FLUG_MASK, pspim->m_base + SP7021_SPI_CONFIG_REG);
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}
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if (pspim->xfer_conf & SP7021_CPOL_FD)
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writel(pspim->xfer_conf, pspim->m_base + SP7021_SPI_CONFIG_REG);
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mutex_unlock(&pspim->buf_lock);
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}
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return 0;
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}
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static int sp7021_spi_slave_transfer_one(struct spi_controller *ctlr, struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
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struct device *dev = pspim->dev;
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int ret;
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if (xfer->tx_buf && !xfer->rx_buf) {
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xfer->tx_dma = dma_map_single(dev, (void *)xfer->tx_buf,
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xfer->len, DMA_TO_DEVICE);
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if (dma_mapping_error(dev, xfer->tx_dma))
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return -ENOMEM;
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ret = sp7021_spi_slave_tx(spi, xfer);
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dma_unmap_single(dev, xfer->tx_dma, xfer->len, DMA_TO_DEVICE);
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} else if (xfer->rx_buf && !xfer->tx_buf) {
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xfer->rx_dma = dma_map_single(dev, xfer->rx_buf, xfer->len,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(dev, xfer->rx_dma))
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return -ENOMEM;
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ret = sp7021_spi_slave_rx(spi, xfer);
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dma_unmap_single(dev, xfer->rx_dma, xfer->len, DMA_FROM_DEVICE);
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} else {
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dev_dbg(&ctlr->dev, "%s() wrong command\n", __func__);
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return -EINVAL;
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}
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spi_finalize_current_transfer(ctlr);
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return ret;
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}
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static void sp7021_spi_disable_unprepare(void *data)
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{
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clk_disable_unprepare(data);
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}
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static void sp7021_spi_reset_control_assert(void *data)
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{
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reset_control_assert(data);
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}
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static int sp7021_spi_controller_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
|
|
struct sp7021_spi_ctlr *pspim;
|
|
struct spi_controller *ctlr;
|
|
int mode, ret;
|
|
|
|
pdev->id = of_alias_get_id(pdev->dev.of_node, "sp_spi");
|
|
|
|
if (device_property_read_bool(dev, "spi-slave"))
|
|
mode = SP7021_SLAVE_MODE;
|
|
else
|
|
mode = SP7021_MASTER_MODE;
|
|
|
|
if (mode == SP7021_SLAVE_MODE)
|
|
ctlr = devm_spi_alloc_slave(dev, sizeof(*pspim));
|
|
else
|
|
ctlr = devm_spi_alloc_master(dev, sizeof(*pspim));
|
|
if (!ctlr)
|
|
return -ENOMEM;
|
|
device_set_node(&ctlr->dev, dev_fwnode(dev));
|
|
ctlr->bus_num = pdev->id;
|
|
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
|
|
ctlr->auto_runtime_pm = true;
|
|
ctlr->prepare_message = sp7021_spi_controller_prepare_message;
|
|
if (mode == SP7021_SLAVE_MODE) {
|
|
ctlr->transfer_one = sp7021_spi_slave_transfer_one;
|
|
ctlr->slave_abort = sp7021_spi_slave_abort;
|
|
ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
|
|
} else {
|
|
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
|
|
ctlr->min_speed_hz = 40000;
|
|
ctlr->max_speed_hz = 25000000;
|
|
ctlr->use_gpio_descriptors = true;
|
|
ctlr->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
|
|
ctlr->transfer_one = sp7021_spi_master_transfer_one;
|
|
}
|
|
platform_set_drvdata(pdev, ctlr);
|
|
pspim = spi_controller_get_devdata(ctlr);
|
|
pspim->mode = mode;
|
|
pspim->ctlr = ctlr;
|
|
pspim->dev = dev;
|
|
mutex_init(&pspim->buf_lock);
|
|
init_completion(&pspim->isr_done);
|
|
init_completion(&pspim->slave_isr);
|
|
|
|
pspim->m_base = devm_platform_ioremap_resource_byname(pdev, "master");
|
|
if (IS_ERR(pspim->m_base))
|
|
return dev_err_probe(dev, PTR_ERR(pspim->m_base), "m_base get fail\n");
|
|
|
|
pspim->s_base = devm_platform_ioremap_resource_byname(pdev, "slave");
|
|
if (IS_ERR(pspim->s_base))
|
|
return dev_err_probe(dev, PTR_ERR(pspim->s_base), "s_base get fail\n");
|
|
|
|
pspim->m_irq = platform_get_irq_byname(pdev, "master_risc");
|
|
if (pspim->m_irq < 0)
|
|
return pspim->m_irq;
|
|
|
|
pspim->s_irq = platform_get_irq_byname(pdev, "slave_risc");
|
|
if (pspim->s_irq < 0)
|
|
return pspim->s_irq;
|
|
|
|
pspim->spi_clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(pspim->spi_clk))
|
|
return dev_err_probe(dev, PTR_ERR(pspim->spi_clk), "clk get fail\n");
|
|
|
|
pspim->rstc = devm_reset_control_get_exclusive(dev, NULL);
|
|
if (IS_ERR(pspim->rstc))
|
|
return dev_err_probe(dev, PTR_ERR(pspim->rstc), "rst get fail\n");
|
|
|
|
ret = clk_prepare_enable(pspim->spi_clk);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "failed to enable clk\n");
|
|
|
|
ret = devm_add_action_or_reset(dev, sp7021_spi_disable_unprepare, pspim->spi_clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = reset_control_deassert(pspim->rstc);
|
|
if (ret)
|
|
return dev_err_probe(dev, ret, "failed to deassert reset\n");
|
|
|
|
ret = devm_add_action_or_reset(dev, sp7021_spi_reset_control_assert, pspim->rstc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = devm_request_irq(dev, pspim->m_irq, sp7021_spi_master_irq,
|
|
IRQF_TRIGGER_RISING, pdev->name, pspim);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = devm_request_irq(dev, pspim->s_irq, sp7021_spi_slave_irq,
|
|
IRQF_TRIGGER_RISING, pdev->name, pspim);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pm_runtime_enable(dev);
|
|
ret = spi_register_controller(ctlr);
|
|
if (ret) {
|
|
pm_runtime_disable(dev);
|
|
return dev_err_probe(dev, ret, "spi_register_master fail\n");
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int sp7021_spi_controller_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
|
|
|
|
spi_unregister_controller(ctlr);
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused sp7021_spi_controller_suspend(struct device *dev)
|
|
{
|
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
|
|
|
|
return reset_control_assert(pspim->rstc);
|
|
}
|
|
|
|
static int __maybe_unused sp7021_spi_controller_resume(struct device *dev)
|
|
{
|
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
|
|
|
|
reset_control_deassert(pspim->rstc);
|
|
return clk_prepare_enable(pspim->spi_clk);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int sp7021_spi_runtime_suspend(struct device *dev)
|
|
{
|
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
|
|
|
|
return reset_control_assert(pspim->rstc);
|
|
}
|
|
|
|
static int sp7021_spi_runtime_resume(struct device *dev)
|
|
{
|
|
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
|
struct sp7021_spi_ctlr *pspim = spi_master_get_devdata(ctlr);
|
|
|
|
return reset_control_deassert(pspim->rstc);
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops sp7021_spi_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(sp7021_spi_runtime_suspend,
|
|
sp7021_spi_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(sp7021_spi_controller_suspend,
|
|
sp7021_spi_controller_resume)
|
|
};
|
|
|
|
static const struct of_device_id sp7021_spi_controller_ids[] = {
|
|
{ .compatible = "sunplus,sp7021-spi" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sp7021_spi_controller_ids);
|
|
|
|
static struct platform_driver sp7021_spi_controller_driver = {
|
|
.probe = sp7021_spi_controller_probe,
|
|
.remove = sp7021_spi_controller_remove,
|
|
.driver = {
|
|
.name = "sunplus,sp7021-spi-controller",
|
|
.of_match_table = sp7021_spi_controller_ids,
|
|
.pm = &sp7021_spi_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(sp7021_spi_controller_driver);
|
|
|
|
MODULE_AUTHOR("Li-hao Kuo <lhjeff911@gmail.com>");
|
|
MODULE_DESCRIPTION("Sunplus SPI controller driver");
|
|
MODULE_LICENSE("GPL");
|