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![Marek Szyprowski](/assets/img/avatar_default.png)
It is allowed to enable/disable clocks from interrupts, so common Exynos ARM clock management code for CPUfreq should use 'irqsave' version of spin_lock calls to avoid potential deadlock caused by spin_lock recursion. The same spin_lock is used by gate/mux clocks during enable/disable calls. This deadlock, can be reproduced by enabling CPUfreq (ondemand or userspace) and decoding video with s5p-mfc driver. Relevant stack trace: [ 5928.061534] BUG: spinlock recursion on CPU#0, bash/1252 [ 5928.061609] lock: 0xee80454c, .magic: dead4ead, .owner: bash/1252, .owner_cpu: 0 [ 5928.068586] CPU: 0 PID: 1252 Comm: bash Tainted: G W 4.4.0-rc4-00001-g447a7fd #678 [ 5928.077260] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) [ 5928.083359] [<c00153dc>] (unwind_backtrace) from [<c00121b4>] (show_stack+0x10/0x14) [ 5928.091072] [<c00121b4>] (show_stack) from [<c0213e28>] (dump_stack+0x68/0xb8) [ 5928.098275] [<c0213e28>] (dump_stack) from [<c005c1ec>] (do_raw_spin_lock+0x184/0x1ac) [ 5928.106177] [<c005c1ec>] (do_raw_spin_lock) from [<c05cfa98>] (_raw_spin_lock_irqsave+0x20/0x28) [ 5928.114943] [<c05cfa98>] (_raw_spin_lock_irqsave) from [<c0468698>] (clk_gate_endisable+0x24/0x98) [ 5928.123882] [<c0468698>] (clk_gate_endisable) from [<c0464d40>] (clk_core_disable+0x60/0x84) [ 5928.132299] [<c0464d40>] (clk_core_disable) from [<c0465e00>] (clk_disable+0x24/0x30) [ 5928.140117] [<c0465e00>] (clk_disable) from [<c03f3b80>] (s5p_mfc_handle_frame+0x254/0x860) [ 5928.148445] [<c03f3b80>] (s5p_mfc_handle_frame) from [<c03f4b34>] (s5p_mfc_irq+0x890/0xa24) [ 5928.156778] [<c03f4b34>] (s5p_mfc_irq) from [<c00627bc>] (handle_irq_event_percpu+0x50/0x14c) [ 5928.165283] [<c00627bc>] (handle_irq_event_percpu) from [<c00628f0>] (handle_irq_event+0x38/0x5c) [ 5928.174143] [<c00628f0>] (handle_irq_event) from [<c0065864>] (handle_fasteoi_irq+0xdc/0x1a4) [ 5928.182645] [<c0065864>] (handle_fasteoi_irq) from [<c0062090>] (generic_handle_irq+0x18/0x28) [ 5928.191236] [<c0062090>] (generic_handle_irq) from [<c00621a4>] (__handle_domain_irq+0x6c/0xdc) [ 5928.199917] [<c00621a4>] (__handle_domain_irq) from [<c0009470>] (gic_handle_irq+0x4c/0x98) [ 5928.208249] [<c0009470>] (gic_handle_irq) from [<c0012c54>] (__irq_svc+0x54/0x90) [ 5928.215709] Exception stack(0xeddb5cb8 to 0xeddb5d00) [ 5928.220745] 5ca0: ee80454c faddfadc [ 5928.228906] 5cc0: 00000000 01000001 ee831ce0 f8114200 ee807c00 01130520 00000403 eddb5d84 [ 5928.237063] 5ce0: ee807c48 2faf0800 ee807c0c eddb5d08 c046b618 c046b634 20000053 ffffffff [ 5928.245225] [<c0012c54>] (__irq_svc) from [<c046b634>] (exynos_cpuclk_notifier_cb+0x170/0x270) [ 5928.253823] [<c046b634>] (exynos_cpuclk_notifier_cb) from [<c003cb58>] (notifier_call_chain+0x44/0x84) [ 5928.263106] [<c003cb58>] (notifier_call_chain) from [<c003ccd4>] (__srcu_notifier_call_chain+0x6c/0x9c) [ 5928.272480] [<c003ccd4>] (__srcu_notifier_call_chain) from [<c003cd1c>] (srcu_notifier_call_chain+0x18/0x20) [ 5928.282288] [<c003cd1c>] (srcu_notifier_call_chain) from [<c0464ed0>] (__clk_notify+0x6c/0x74) [ 5928.290881] [<c0464ed0>] (__clk_notify) from [<c0465388>] (clk_propagate_rate_change+0xa0/0xac) [ 5928.299561] [<c0465388>] (clk_propagate_rate_change) from [<c0465378>] (clk_propagate_rate_change+0x90/0xac) [ 5928.309370] [<c0465378>] (clk_propagate_rate_change) from [<c04666fc>] (clk_core_set_rate_nolock+0x64/0xa8) [ 5928.319091] [<c04666fc>] (clk_core_set_rate_nolock) from [<c0466760>] (clk_set_rate+0x20/0x30) [ 5928.327686] [<c0466760>] (clk_set_rate) from [<c0428c70>] (set_target+0xe8/0x23c) [ 5928.335152] [<c0428c70>] (set_target) from [<c04244d0>] (__cpufreq_driver_target+0x184/0x29c) [ 5928.343655] [<c04244d0>] (__cpufreq_driver_target) from [<c0427128>] (cpufreq_set+0x44/0x64) [ 5928.352074] [<c0427128>] (cpufreq_set) from [<c0423948>] (store_scaling_setspeed+0x5c/0x74) [ 5928.360407] [<c0423948>] (store_scaling_setspeed) from [<c04238d0>] (store+0x7c/0x98) [ 5928.368221] [<c04238d0>] (store) from [<c0132540>] (sysfs_kf_write+0x44/0x48) [ 5928.375338] [<c0132540>] (sysfs_kf_write) from [<c0131b9c>] (kernfs_fop_write+0xb8/0x1bc) [ 5928.383496] [<c0131b9c>] (kernfs_fop_write) from [<c00d71f8>] (__vfs_write+0x2c/0xd4) [ 5928.391308] [<c00d71f8>] (__vfs_write) from [<c00d7de8>] (vfs_write+0xa0/0x144) [ 5928.398598] [<c00d7de8>] (vfs_write) from [<c00d8048>] (SyS_write+0x44/0x84) [ 5928.405631] [<c00d8048>] (SyS_write) from [<c000f540>] (ret_fast_syscall+0x0/0x3c) CC: stable@vger.kernel.org # v4.2+ Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
354 lines
11 KiB
C
354 lines
11 KiB
C
/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This file contains the utility function to register CPU clock for Samsung
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* Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
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* group of CPUs. The CPU clock is typically derived from a hierarchy of clock
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* blocks which includes mux and divider blocks. There are a number of other
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* auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
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* clock for CPU domain. The rates of these auxiliary clocks are related to the
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* CPU clock rate and this relation is usually specified in the hardware manual
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* of the SoC or supplied after the SoC characterization.
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*
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* The below implementation of the CPU clock allows the rate changes of the CPU
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* clock and the corresponding rate changes of the auxillary clocks of the CPU
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* domain. The platform clock driver provides a clock register configuration
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* for each configurable rate which is then used to program the clock hardware
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* registers to acheive a fast co-oridinated rate change for all the CPU domain
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* clocks.
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*
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* On a rate change request for the CPU clock, the rate change is propagated
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* upto the PLL supplying the clock to the CPU domain clock blocks. While the
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* CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
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* alternate clock source. If required, the alternate clock source is divided
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* down in order to keep the output clock rate within the previous OPP limits.
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*/
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include "clk-cpu.h"
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#define E4210_SRC_CPU 0x0
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#define E4210_STAT_CPU 0x200
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#define E4210_DIV_CPU0 0x300
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#define E4210_DIV_CPU1 0x304
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#define E4210_DIV_STAT_CPU0 0x400
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#define E4210_DIV_STAT_CPU1 0x404
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#define E4210_DIV0_RATIO0_MASK 0x7
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#define E4210_DIV1_HPM_MASK (0x7 << 4)
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#define E4210_DIV1_COPY_MASK (0x7 << 0)
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#define E4210_MUX_HPM_MASK (1 << 20)
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#define E4210_DIV0_ATB_SHIFT 16
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#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
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#define MAX_DIV 8
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#define DIV_MASK 7
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#define DIV_MASK_ALL 0xffffffff
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#define MUX_MASK 7
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/*
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* Helper function to wait until divider(s) have stabilized after the divider
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* value has changed.
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*/
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static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(10);
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do {
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if (!(readl(div_reg) & mask))
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return;
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} while (time_before(jiffies, timeout));
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if (!(readl(div_reg) & mask))
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return;
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pr_err("%s: timeout in divider stablization\n", __func__);
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}
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/*
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* Helper function to wait until mux has stabilized after the mux selection
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* value was changed.
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*/
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static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
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unsigned long mux_value)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(10);
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do {
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if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
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return;
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} while (time_before(jiffies, timeout));
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if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
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return;
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pr_err("%s: re-parenting mux timed-out\n", __func__);
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}
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/* common round rate callback useable for all types of CPU clocks */
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static long exynos_cpuclk_round_rate(struct clk_hw *hw,
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unsigned long drate, unsigned long *prate)
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{
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struct clk_hw *parent = clk_hw_get_parent(hw);
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*prate = clk_hw_round_rate(parent, drate);
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return *prate;
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}
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/* common recalc rate callback useable for all types of CPU clocks */
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static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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/*
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* The CPU clock output (armclk) rate is the same as its parent
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* rate. Although there exist certain dividers inside the CPU
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* clock block that could be used to divide the parent clock,
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* the driver does not make use of them currently, except during
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* frequency transitions.
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*/
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return parent_rate;
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}
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static const struct clk_ops exynos_cpuclk_clk_ops = {
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.recalc_rate = exynos_cpuclk_recalc_rate,
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.round_rate = exynos_cpuclk_round_rate,
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};
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/*
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* Helper function to set the 'safe' dividers for the CPU clock. The parameters
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* div and mask contain the divider value and the register bit mask of the
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* dividers to be programmed.
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*/
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static void exynos_set_safe_div(void __iomem *base, unsigned long div,
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unsigned long mask)
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{
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unsigned long div0;
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div0 = readl(base + E4210_DIV_CPU0);
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div0 = (div0 & ~mask) | (div & mask);
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writel(div0, base + E4210_DIV_CPU0);
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wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask);
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}
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/* handler for pre-rate change notification from parent clock */
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static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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struct exynos_cpuclk *cpuclk, void __iomem *base)
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{
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const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
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unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent);
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unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
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unsigned long div0, div1 = 0, mux_reg;
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unsigned long flags;
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/* find out the divider values to use for clock data */
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while ((cfg_data->prate * 1000) != ndata->new_rate) {
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if (cfg_data->prate == 0)
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return -EINVAL;
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cfg_data++;
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}
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spin_lock_irqsave(cpuclk->lock, flags);
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/*
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* For the selected PLL clock frequency, get the pre-defined divider
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* values. If the clock for sclk_hpm is not sourced from apll, then
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* the values for DIV_COPY and DIV_HPM dividers need not be set.
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*/
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div0 = cfg_data->div0;
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if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
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div1 = cfg_data->div1;
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if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK)
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div1 = readl(base + E4210_DIV_CPU1) &
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(E4210_DIV1_HPM_MASK | E4210_DIV1_COPY_MASK);
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}
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/*
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* If the old parent clock speed is less than the clock speed of
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* the alternate parent, then it should be ensured that at no point
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* the armclk speed is more than the old_prate until the dividers are
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* set. Also workaround the issue of the dividers being set to lower
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* values before the parent clock speed is set to new lower speed
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* (this can result in too high speed of armclk output clocks).
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*/
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if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
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unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
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alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
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WARN_ON(alt_div >= MAX_DIV);
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if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
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/*
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* In Exynos4210, ATB clock parent is also mout_core. So
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* ATB clock also needs to be mantained at safe speed.
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*/
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alt_div |= E4210_DIV0_ATB_MASK;
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alt_div_mask |= E4210_DIV0_ATB_MASK;
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}
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exynos_set_safe_div(base, alt_div, alt_div_mask);
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div0 |= alt_div;
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}
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/* select sclk_mpll as the alternate parent */
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mux_reg = readl(base + E4210_SRC_CPU);
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writel(mux_reg | (1 << 16), base + E4210_SRC_CPU);
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wait_until_mux_stable(base + E4210_STAT_CPU, 16, 2);
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/* alternate parent is active now. set the dividers */
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writel(div0, base + E4210_DIV_CPU0);
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wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL);
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if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
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writel(div1, base + E4210_DIV_CPU1);
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wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,
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DIV_MASK_ALL);
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}
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spin_unlock_irqrestore(cpuclk->lock, flags);
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return 0;
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}
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/* handler for post-rate change notification from parent clock */
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static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
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struct exynos_cpuclk *cpuclk, void __iomem *base)
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{
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const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
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unsigned long div = 0, div_mask = DIV_MASK;
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unsigned long mux_reg;
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unsigned long flags;
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/* find out the divider values to use for clock data */
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if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
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while ((cfg_data->prate * 1000) != ndata->new_rate) {
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if (cfg_data->prate == 0)
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return -EINVAL;
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cfg_data++;
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}
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}
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spin_lock_irqsave(cpuclk->lock, flags);
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/* select mout_apll as the alternate parent */
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mux_reg = readl(base + E4210_SRC_CPU);
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writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);
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wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1);
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if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
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div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
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div_mask |= E4210_DIV0_ATB_MASK;
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}
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exynos_set_safe_div(base, div, div_mask);
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spin_unlock_irqrestore(cpuclk->lock, flags);
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return 0;
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}
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/*
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* This notifier function is called for the pre-rate and post-rate change
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* notifications of the parent clock of cpuclk.
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*/
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static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct exynos_cpuclk *cpuclk;
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void __iomem *base;
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int err = 0;
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cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
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base = cpuclk->ctrl_base;
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if (event == PRE_RATE_CHANGE)
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err = exynos_cpuclk_pre_rate_change(ndata, cpuclk, base);
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else if (event == POST_RATE_CHANGE)
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err = exynos_cpuclk_post_rate_change(ndata, cpuclk, base);
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return notifier_from_errno(err);
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}
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/* helper function to register a CPU clock */
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int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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unsigned int lookup_id, const char *name, const char *parent,
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const char *alt_parent, unsigned long offset,
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const struct exynos_cpuclk_cfg_data *cfg,
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unsigned long num_cfgs, unsigned long flags)
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{
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struct exynos_cpuclk *cpuclk;
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struct clk_init_data init;
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struct clk *clk;
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int ret = 0;
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cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
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if (!cpuclk)
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return -ENOMEM;
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init.name = name;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = &parent;
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init.num_parents = 1;
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init.ops = &exynos_cpuclk_clk_ops;
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cpuclk->hw.init = &init;
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cpuclk->ctrl_base = ctx->reg_base + offset;
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cpuclk->lock = &ctx->lock;
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cpuclk->flags = flags;
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cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
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cpuclk->alt_parent = __clk_lookup(alt_parent);
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if (!cpuclk->alt_parent) {
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pr_err("%s: could not lookup alternate parent %s\n",
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__func__, alt_parent);
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ret = -EINVAL;
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goto free_cpuclk;
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}
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clk = __clk_lookup(parent);
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if (!clk) {
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pr_err("%s: could not lookup parent clock %s\n",
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__func__, parent);
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ret = -EINVAL;
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goto free_cpuclk;
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}
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ret = clk_notifier_register(clk, &cpuclk->clk_nb);
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if (ret) {
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pr_err("%s: failed to register clock notifier for %s\n",
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__func__, name);
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goto free_cpuclk;
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}
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cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL);
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if (!cpuclk->cfg) {
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pr_err("%s: could not allocate memory for cpuclk data\n",
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__func__);
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ret = -ENOMEM;
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goto unregister_clk_nb;
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}
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clk = clk_register(NULL, &cpuclk->hw);
|
|
if (IS_ERR(clk)) {
|
|
pr_err("%s: could not register cpuclk %s\n", __func__, name);
|
|
ret = PTR_ERR(clk);
|
|
goto free_cpuclk_data;
|
|
}
|
|
|
|
samsung_clk_add_lookup(ctx, clk, lookup_id);
|
|
return 0;
|
|
|
|
free_cpuclk_data:
|
|
kfree(cpuclk->cfg);
|
|
unregister_clk_nb:
|
|
clk_notifier_unregister(__clk_lookup(parent), &cpuclk->clk_nb);
|
|
free_cpuclk:
|
|
kfree(cpuclk);
|
|
return ret;
|
|
}
|