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![Linus Torvalds](/assets/img/avatar_default.png)
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (163 commits) omap: complete removal of machine_desc.io_pg_offst and .phys_io omap: UART: fix wakeup registers for OMAP24xx UART2 omap: Fix spotty MMC voltages ASoC: OMAP4: MCPDM: Remove unnecessary include of plat/control.h serial: omap-serial: fix signess error OMAP3: DMA: Errata i541: sDMA FIFO draining does not finish omap: dma: Fix buffering disable bit setting for omap24xx omap: serial: Fix the boot-up crash/reboot without CONFIG_PM OMAP3: PM: fix scratchpad memory accesses for off-mode omap4: pandaboard: enable the ehci port on pandaboard omap4: pandaboard: Fix the init if CONFIG_MMC_OMAP_HS is not set omap4: pandaboard: remove unused hsmmc definition OMAP: McBSP: Remove null omap44xx ops comment OMAP: McBSP: Swap CLKS source definition OMAP: McBSP: Fix CLKR and FSR signal muxing OMAP2+: clock: reduce the amount of standard debugging while disabling unused clocks OMAP: control: move plat-omap/control.h to mach-omap2/control.h OMAP: split plat-omap/common.c OMAP: McBSP: implement functional clock switching via clock framework OMAP: McBSP: implement McBSP CLKR and FSR signal muxing via mach-omap2/mcbsp.c ... Fixed up trivial conflicts in arch/arm/mach-omap2/ {board-zoom-peripherals.c,devices.c} as per Tony
1070 lines
25 KiB
C
1070 lines
25 KiB
C
/*
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* linux/arch/arm/mach-omap2/devices.c
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*
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* OMAP2 platform device setup/initialization
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <asm/mach-types.h>
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#include <asm/mach/map.h>
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#include <asm/pmu.h>
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#include <plat/tc.h>
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#include <plat/board.h>
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#include <plat/mcbsp.h>
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#include <mach/gpio.h>
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#include <plat/mmc.h>
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#include <plat/dma.h>
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#include <plat/omap_hwmod.h>
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#include <plat/omap_device.h>
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#include "mux.h"
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#include "control.h"
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#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
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static struct resource cam_resources[] = {
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{
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.start = OMAP24XX_CAMERA_BASE,
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.end = OMAP24XX_CAMERA_BASE + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_24XX_CAM_IRQ,
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.flags = IORESOURCE_IRQ,
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}
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};
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static struct platform_device omap_cam_device = {
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.name = "omap24xxcam",
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.id = -1,
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.num_resources = ARRAY_SIZE(cam_resources),
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.resource = cam_resources,
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};
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static inline void omap_init_camera(void)
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{
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platform_device_register(&omap_cam_device);
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}
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#elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
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static struct resource omap3isp_resources[] = {
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{
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.start = OMAP3430_ISP_BASE,
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.end = OMAP3430_ISP_END,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP3430_ISP_CBUFF_BASE,
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.end = OMAP3430_ISP_CBUFF_END,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP3430_ISP_CCP2_BASE,
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.end = OMAP3430_ISP_CCP2_END,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP3430_ISP_CCDC_BASE,
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.end = OMAP3430_ISP_CCDC_END,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP3430_ISP_HIST_BASE,
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.end = OMAP3430_ISP_HIST_END,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP3430_ISP_H3A_BASE,
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.end = OMAP3430_ISP_H3A_END,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP3430_ISP_PREV_BASE,
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.end = OMAP3430_ISP_PREV_END,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP3430_ISP_RESZ_BASE,
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.end = OMAP3430_ISP_RESZ_END,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP3430_ISP_SBL_BASE,
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.end = OMAP3430_ISP_SBL_END,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP3430_ISP_CSI2A_BASE,
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.end = OMAP3430_ISP_CSI2A_END,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP3430_ISP_CSI2PHY_BASE,
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.end = OMAP3430_ISP_CSI2PHY_END,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_34XX_CAM_IRQ,
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.flags = IORESOURCE_IRQ,
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}
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};
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static struct platform_device omap3isp_device = {
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.name = "omap3isp",
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.id = -1,
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.num_resources = ARRAY_SIZE(omap3isp_resources),
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.resource = omap3isp_resources,
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};
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static inline void omap_init_camera(void)
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{
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platform_device_register(&omap3isp_device);
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}
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#else
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static inline void omap_init_camera(void)
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{
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}
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#endif
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#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
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#define MBOX_REG_SIZE 0x120
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#ifdef CONFIG_ARCH_OMAP2
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static struct resource omap2_mbox_resources[] = {
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{
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.start = OMAP24XX_MAILBOX_BASE,
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.end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_24XX_MAIL_U0_MPU,
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.flags = IORESOURCE_IRQ,
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.name = "dsp",
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},
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{
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.start = INT_24XX_MAIL_U3_MPU,
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.flags = IORESOURCE_IRQ,
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.name = "iva",
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},
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};
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static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
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#else
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#define omap2_mbox_resources NULL
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#define omap2_mbox_resources_sz 0
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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static struct resource omap3_mbox_resources[] = {
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{
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.start = OMAP34XX_MAILBOX_BASE,
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.end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_24XX_MAIL_U0_MPU,
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.flags = IORESOURCE_IRQ,
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.name = "dsp",
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},
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};
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static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
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#else
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#define omap3_mbox_resources NULL
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#define omap3_mbox_resources_sz 0
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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#define OMAP4_MBOX_REG_SIZE 0x130
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static struct resource omap4_mbox_resources[] = {
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{
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.start = OMAP44XX_MAILBOX_BASE,
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.end = OMAP44XX_MAILBOX_BASE +
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OMAP4_MBOX_REG_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP44XX_IRQ_MAIL_U0,
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.flags = IORESOURCE_IRQ,
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.name = "mbox",
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},
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};
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static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
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#else
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#define omap4_mbox_resources NULL
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#define omap4_mbox_resources_sz 0
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#endif
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static struct platform_device mbox_device = {
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.name = "omap-mailbox",
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.id = -1,
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};
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static inline void omap_init_mbox(void)
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{
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if (cpu_is_omap24xx()) {
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mbox_device.resource = omap2_mbox_resources;
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mbox_device.num_resources = omap2_mbox_resources_sz;
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} else if (cpu_is_omap34xx()) {
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mbox_device.resource = omap3_mbox_resources;
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mbox_device.num_resources = omap3_mbox_resources_sz;
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} else if (cpu_is_omap44xx()) {
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mbox_device.resource = omap4_mbox_resources;
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mbox_device.num_resources = omap4_mbox_resources_sz;
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} else {
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pr_err("%s: platform not supported\n", __func__);
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return;
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}
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platform_device_register(&mbox_device);
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}
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#else
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static inline void omap_init_mbox(void) { }
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#endif /* CONFIG_OMAP_MBOX_FWK */
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static inline void omap_init_sti(void) {}
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#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
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static struct platform_device omap_pcm = {
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.name = "omap-pcm-audio",
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.id = -1,
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};
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/*
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* OMAP2420 has 2 McBSP ports
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* OMAP2430 has 5 McBSP ports
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* OMAP3 has 5 McBSP ports
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* OMAP4 has 4 McBSP ports
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*/
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OMAP_MCBSP_PLATFORM_DEVICE(1);
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OMAP_MCBSP_PLATFORM_DEVICE(2);
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OMAP_MCBSP_PLATFORM_DEVICE(3);
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OMAP_MCBSP_PLATFORM_DEVICE(4);
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OMAP_MCBSP_PLATFORM_DEVICE(5);
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static void omap_init_audio(void)
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{
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platform_device_register(&omap_mcbsp1);
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platform_device_register(&omap_mcbsp2);
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if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
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platform_device_register(&omap_mcbsp3);
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platform_device_register(&omap_mcbsp4);
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}
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if (cpu_is_omap243x() || cpu_is_omap34xx())
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platform_device_register(&omap_mcbsp5);
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platform_device_register(&omap_pcm);
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}
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#else
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static inline void omap_init_audio(void) {}
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#endif
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#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
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#include <plat/mcspi.h>
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#define OMAP2_MCSPI1_BASE 0x48098000
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#define OMAP2_MCSPI2_BASE 0x4809a000
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#define OMAP2_MCSPI3_BASE 0x480b8000
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#define OMAP2_MCSPI4_BASE 0x480ba000
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#define OMAP4_MCSPI1_BASE 0x48098100
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#define OMAP4_MCSPI2_BASE 0x4809a100
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#define OMAP4_MCSPI3_BASE 0x480b8100
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#define OMAP4_MCSPI4_BASE 0x480ba100
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static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
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.num_cs = 4,
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};
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static struct resource omap2_mcspi1_resources[] = {
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{
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.start = OMAP2_MCSPI1_BASE,
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.end = OMAP2_MCSPI1_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device omap2_mcspi1 = {
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.name = "omap2_mcspi",
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.id = 1,
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.num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
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.resource = omap2_mcspi1_resources,
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.dev = {
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.platform_data = &omap2_mcspi1_config,
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},
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};
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static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
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.num_cs = 2,
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};
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static struct resource omap2_mcspi2_resources[] = {
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{
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.start = OMAP2_MCSPI2_BASE,
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.end = OMAP2_MCSPI2_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device omap2_mcspi2 = {
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.name = "omap2_mcspi",
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.id = 2,
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.num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
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.resource = omap2_mcspi2_resources,
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.dev = {
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.platform_data = &omap2_mcspi2_config,
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},
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};
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#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
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defined(CONFIG_ARCH_OMAP4)
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static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
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.num_cs = 2,
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};
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static struct resource omap2_mcspi3_resources[] = {
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{
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.start = OMAP2_MCSPI3_BASE,
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.end = OMAP2_MCSPI3_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device omap2_mcspi3 = {
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.name = "omap2_mcspi",
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.id = 3,
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.num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
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.resource = omap2_mcspi3_resources,
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.dev = {
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.platform_data = &omap2_mcspi3_config,
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},
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};
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#endif
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#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
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static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
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.num_cs = 1,
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};
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static struct resource omap2_mcspi4_resources[] = {
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{
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.start = OMAP2_MCSPI4_BASE,
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.end = OMAP2_MCSPI4_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device omap2_mcspi4 = {
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.name = "omap2_mcspi",
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.id = 4,
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.num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
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.resource = omap2_mcspi4_resources,
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.dev = {
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.platform_data = &omap2_mcspi4_config,
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},
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};
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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static inline void omap4_mcspi_fixup(void)
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{
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omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
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omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
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omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
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omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
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omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
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omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
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omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
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omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
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}
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#else
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static inline void omap4_mcspi_fixup(void)
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{
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}
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#endif
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#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
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defined(CONFIG_ARCH_OMAP4)
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static inline void omap2_mcspi3_init(void)
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{
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platform_device_register(&omap2_mcspi3);
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}
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#else
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static inline void omap2_mcspi3_init(void)
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{
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}
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#endif
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#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
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static inline void omap2_mcspi4_init(void)
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{
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platform_device_register(&omap2_mcspi4);
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}
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#else
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static inline void omap2_mcspi4_init(void)
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{
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}
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#endif
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static void omap_init_mcspi(void)
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{
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if (cpu_is_omap44xx())
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omap4_mcspi_fixup();
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platform_device_register(&omap2_mcspi1);
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platform_device_register(&omap2_mcspi2);
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if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
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omap2_mcspi3_init();
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if (cpu_is_omap343x() || cpu_is_omap44xx())
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omap2_mcspi4_init();
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}
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#else
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static inline void omap_init_mcspi(void) {}
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#endif
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static struct resource omap2_pmu_resource = {
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.start = 3,
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.end = 3,
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.flags = IORESOURCE_IRQ,
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};
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static struct resource omap3_pmu_resource = {
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.start = INT_34XX_BENCH_MPU_EMUL,
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.end = INT_34XX_BENCH_MPU_EMUL,
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.flags = IORESOURCE_IRQ,
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};
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static struct platform_device omap_pmu_device = {
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.name = "arm-pmu",
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.id = ARM_PMU_DEVICE_CPU,
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.num_resources = 1,
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};
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static void omap_init_pmu(void)
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{
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if (cpu_is_omap24xx())
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omap_pmu_device.resource = &omap2_pmu_resource;
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else if (cpu_is_omap34xx())
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omap_pmu_device.resource = &omap3_pmu_resource;
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else
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return;
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platform_device_register(&omap_pmu_device);
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|
}
|
|
|
|
|
|
#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
|
|
|
|
#ifdef CONFIG_ARCH_OMAP2
|
|
static struct resource omap2_sham_resources[] = {
|
|
{
|
|
.start = OMAP24XX_SEC_SHA1MD5_BASE,
|
|
.end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = INT_24XX_SHA1MD5,
|
|
.flags = IORESOURCE_IRQ,
|
|
}
|
|
};
|
|
static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
|
|
#else
|
|
#define omap2_sham_resources NULL
|
|
#define omap2_sham_resources_sz 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
static struct resource omap3_sham_resources[] = {
|
|
{
|
|
.start = OMAP34XX_SEC_SHA1MD5_BASE,
|
|
.end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = INT_34XX_SHA1MD52_IRQ,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = OMAP34XX_DMA_SHA1MD5_RX,
|
|
.flags = IORESOURCE_DMA,
|
|
}
|
|
};
|
|
static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
|
|
#else
|
|
#define omap3_sham_resources NULL
|
|
#define omap3_sham_resources_sz 0
|
|
#endif
|
|
|
|
static struct platform_device sham_device = {
|
|
.name = "omap-sham",
|
|
.id = -1,
|
|
};
|
|
|
|
static void omap_init_sham(void)
|
|
{
|
|
if (cpu_is_omap24xx()) {
|
|
sham_device.resource = omap2_sham_resources;
|
|
sham_device.num_resources = omap2_sham_resources_sz;
|
|
} else if (cpu_is_omap34xx()) {
|
|
sham_device.resource = omap3_sham_resources;
|
|
sham_device.num_resources = omap3_sham_resources_sz;
|
|
} else {
|
|
pr_err("%s: platform not supported\n", __func__);
|
|
return;
|
|
}
|
|
platform_device_register(&sham_device);
|
|
}
|
|
#else
|
|
static inline void omap_init_sham(void) { }
|
|
#endif
|
|
|
|
#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
|
|
|
|
#ifdef CONFIG_ARCH_OMAP2
|
|
static struct resource omap2_aes_resources[] = {
|
|
{
|
|
.start = OMAP24XX_SEC_AES_BASE,
|
|
.end = OMAP24XX_SEC_AES_BASE + 0x4C,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = OMAP24XX_DMA_AES_TX,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
{
|
|
.start = OMAP24XX_DMA_AES_RX,
|
|
.flags = IORESOURCE_DMA,
|
|
}
|
|
};
|
|
static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
|
|
#else
|
|
#define omap2_aes_resources NULL
|
|
#define omap2_aes_resources_sz 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
static struct resource omap3_aes_resources[] = {
|
|
{
|
|
.start = OMAP34XX_SEC_AES_BASE,
|
|
.end = OMAP34XX_SEC_AES_BASE + 0x4C,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = OMAP34XX_DMA_AES2_TX,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
{
|
|
.start = OMAP34XX_DMA_AES2_RX,
|
|
.flags = IORESOURCE_DMA,
|
|
}
|
|
};
|
|
static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
|
|
#else
|
|
#define omap3_aes_resources NULL
|
|
#define omap3_aes_resources_sz 0
|
|
#endif
|
|
|
|
static struct platform_device aes_device = {
|
|
.name = "omap-aes",
|
|
.id = -1,
|
|
};
|
|
|
|
static void omap_init_aes(void)
|
|
{
|
|
if (cpu_is_omap24xx()) {
|
|
aes_device.resource = omap2_aes_resources;
|
|
aes_device.num_resources = omap2_aes_resources_sz;
|
|
} else if (cpu_is_omap34xx()) {
|
|
aes_device.resource = omap3_aes_resources;
|
|
aes_device.num_resources = omap3_aes_resources_sz;
|
|
} else {
|
|
pr_err("%s: platform not supported\n", __func__);
|
|
return;
|
|
}
|
|
platform_device_register(&aes_device);
|
|
}
|
|
|
|
#else
|
|
static inline void omap_init_aes(void) { }
|
|
#endif
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
|
|
|
|
#define MMCHS_SYSCONFIG 0x0010
|
|
#define MMCHS_SYSCONFIG_SWRESET (1 << 1)
|
|
#define MMCHS_SYSSTATUS 0x0014
|
|
#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
|
|
|
|
static struct platform_device dummy_pdev = {
|
|
.dev = {
|
|
.bus = &platform_bus_type,
|
|
},
|
|
};
|
|
|
|
/**
|
|
* omap_hsmmc_reset() - Full reset of each HS-MMC controller
|
|
*
|
|
* Ensure that each MMC controller is fully reset. Controllers
|
|
* left in an unknown state (by bootloader) may prevent retention
|
|
* or OFF-mode. This is especially important in cases where the
|
|
* MMC driver is not enabled, _or_ built as a module.
|
|
*
|
|
* In order for reset to work, interface, functional and debounce
|
|
* clocks must be enabled. The debounce clock comes from func_32k_clk
|
|
* and is not under SW control, so we only enable i- and f-clocks.
|
|
**/
|
|
static void __init omap_hsmmc_reset(void)
|
|
{
|
|
u32 i, nr_controllers;
|
|
|
|
if (cpu_is_omap242x())
|
|
return;
|
|
|
|
nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
|
|
(cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
|
|
|
|
for (i = 0; i < nr_controllers; i++) {
|
|
u32 v, base = 0;
|
|
struct clk *iclk, *fclk;
|
|
struct device *dev = &dummy_pdev.dev;
|
|
|
|
switch (i) {
|
|
case 0:
|
|
base = OMAP2_MMC1_BASE;
|
|
break;
|
|
case 1:
|
|
base = OMAP2_MMC2_BASE;
|
|
break;
|
|
case 2:
|
|
base = OMAP3_MMC3_BASE;
|
|
break;
|
|
case 3:
|
|
if (!cpu_is_omap44xx())
|
|
return;
|
|
base = OMAP4_MMC4_BASE;
|
|
break;
|
|
case 4:
|
|
if (!cpu_is_omap44xx())
|
|
return;
|
|
base = OMAP4_MMC5_BASE;
|
|
break;
|
|
}
|
|
|
|
if (cpu_is_omap44xx())
|
|
base += OMAP4_MMC_REG_OFFSET;
|
|
|
|
dummy_pdev.id = i;
|
|
dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
|
|
iclk = clk_get(dev, "ick");
|
|
if (iclk && clk_enable(iclk))
|
|
iclk = NULL;
|
|
|
|
fclk = clk_get(dev, "fck");
|
|
if (fclk && clk_enable(fclk))
|
|
fclk = NULL;
|
|
|
|
if (!iclk || !fclk) {
|
|
printk(KERN_WARNING
|
|
"%s: Unable to enable clocks for MMC%d, "
|
|
"cannot reset.\n", __func__, i);
|
|
break;
|
|
}
|
|
|
|
omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
|
|
v = omap_readl(base + MMCHS_SYSSTATUS);
|
|
while (!(omap_readl(base + MMCHS_SYSSTATUS) &
|
|
MMCHS_SYSSTATUS_RESETDONE))
|
|
cpu_relax();
|
|
|
|
if (fclk) {
|
|
clk_disable(fclk);
|
|
clk_put(fclk);
|
|
}
|
|
if (iclk) {
|
|
clk_disable(iclk);
|
|
clk_put(iclk);
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
static inline void omap_hsmmc_reset(void) {}
|
|
#endif
|
|
|
|
#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
|
|
defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
|
|
|
|
static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
|
|
int controller_nr)
|
|
{
|
|
if ((mmc_controller->slots[0].switch_pin > 0) && \
|
|
(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
|
|
omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
if ((mmc_controller->slots[0].gpio_wp > 0) && \
|
|
(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
|
|
omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
|
|
if (cpu_is_omap2420() && controller_nr == 0) {
|
|
omap_mux_init_signal("sdmmc_cmd", 0);
|
|
omap_mux_init_signal("sdmmc_clki", 0);
|
|
omap_mux_init_signal("sdmmc_clko", 0);
|
|
omap_mux_init_signal("sdmmc_dat0", 0);
|
|
omap_mux_init_signal("sdmmc_dat_dir0", 0);
|
|
omap_mux_init_signal("sdmmc_cmd_dir", 0);
|
|
if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
|
|
omap_mux_init_signal("sdmmc_dat1", 0);
|
|
omap_mux_init_signal("sdmmc_dat2", 0);
|
|
omap_mux_init_signal("sdmmc_dat3", 0);
|
|
omap_mux_init_signal("sdmmc_dat_dir1", 0);
|
|
omap_mux_init_signal("sdmmc_dat_dir2", 0);
|
|
omap_mux_init_signal("sdmmc_dat_dir3", 0);
|
|
}
|
|
|
|
/*
|
|
* Use internal loop-back in MMC/SDIO Module Input Clock
|
|
* selection
|
|
*/
|
|
if (mmc_controller->slots[0].internal_clock) {
|
|
u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
|
|
v |= (1 << 24);
|
|
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
|
|
}
|
|
}
|
|
|
|
if (cpu_is_omap34xx()) {
|
|
if (controller_nr == 0) {
|
|
omap_mux_init_signal("sdmmc1_clk",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc1_cmd",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc1_dat0",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
if (mmc_controller->slots[0].caps &
|
|
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
|
|
omap_mux_init_signal("sdmmc1_dat1",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc1_dat2",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc1_dat3",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
}
|
|
if (mmc_controller->slots[0].caps &
|
|
MMC_CAP_8_BIT_DATA) {
|
|
omap_mux_init_signal("sdmmc1_dat4",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc1_dat5",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc1_dat6",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc1_dat7",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
}
|
|
}
|
|
if (controller_nr == 1) {
|
|
/* MMC2 */
|
|
omap_mux_init_signal("sdmmc2_clk",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc2_cmd",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc2_dat0",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
|
|
/*
|
|
* For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
|
|
* in the board-*.c files
|
|
*/
|
|
if (mmc_controller->slots[0].caps &
|
|
(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
|
|
omap_mux_init_signal("sdmmc2_dat1",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc2_dat2",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc2_dat3",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
}
|
|
if (mmc_controller->slots[0].caps &
|
|
MMC_CAP_8_BIT_DATA) {
|
|
omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
|
|
OMAP_PIN_INPUT_PULLUP);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* For MMC3 the pins need to be muxed in the board-*.c files
|
|
*/
|
|
}
|
|
}
|
|
|
|
void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
|
|
int nr_controllers)
|
|
{
|
|
int i;
|
|
char *name;
|
|
|
|
for (i = 0; i < nr_controllers; i++) {
|
|
unsigned long base, size;
|
|
unsigned int irq = 0;
|
|
|
|
if (!mmc_data[i])
|
|
continue;
|
|
|
|
omap2_mmc_mux(mmc_data[i], i);
|
|
|
|
switch (i) {
|
|
case 0:
|
|
base = OMAP2_MMC1_BASE;
|
|
irq = INT_24XX_MMC_IRQ;
|
|
break;
|
|
case 1:
|
|
base = OMAP2_MMC2_BASE;
|
|
irq = INT_24XX_MMC2_IRQ;
|
|
break;
|
|
case 2:
|
|
if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
|
|
return;
|
|
base = OMAP3_MMC3_BASE;
|
|
irq = INT_34XX_MMC3_IRQ;
|
|
break;
|
|
case 3:
|
|
if (!cpu_is_omap44xx())
|
|
return;
|
|
base = OMAP4_MMC4_BASE;
|
|
irq = OMAP44XX_IRQ_MMC4;
|
|
break;
|
|
case 4:
|
|
if (!cpu_is_omap44xx())
|
|
return;
|
|
base = OMAP4_MMC5_BASE;
|
|
irq = OMAP44XX_IRQ_MMC5;
|
|
break;
|
|
default:
|
|
continue;
|
|
}
|
|
|
|
if (cpu_is_omap2420()) {
|
|
size = OMAP2420_MMC_SIZE;
|
|
name = "mmci-omap";
|
|
} else if (cpu_is_omap44xx()) {
|
|
if (i < 3)
|
|
irq += OMAP44XX_IRQ_GIC_START;
|
|
size = OMAP4_HSMMC_SIZE;
|
|
name = "mmci-omap-hs";
|
|
} else {
|
|
size = OMAP3_HSMMC_SIZE;
|
|
name = "mmci-omap-hs";
|
|
}
|
|
omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
|
|
};
|
|
}
|
|
|
|
#endif
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
|
|
#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
|
|
#define OMAP_HDQ_BASE 0x480B2000
|
|
#endif
|
|
static struct resource omap_hdq_resources[] = {
|
|
{
|
|
.start = OMAP_HDQ_BASE,
|
|
.end = OMAP_HDQ_BASE + 0x1C,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = INT_24XX_HDQ_IRQ,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
static struct platform_device omap_hdq_dev = {
|
|
.name = "omap_hdq",
|
|
.id = 0,
|
|
.dev = {
|
|
.platform_data = NULL,
|
|
},
|
|
.num_resources = ARRAY_SIZE(omap_hdq_resources),
|
|
.resource = omap_hdq_resources,
|
|
};
|
|
static inline void omap_hdq_init(void)
|
|
{
|
|
(void) platform_device_register(&omap_hdq_dev);
|
|
}
|
|
#else
|
|
static inline void omap_hdq_init(void) {}
|
|
#endif
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
|
|
#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
|
|
defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
|
|
#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
|
|
static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
|
|
};
|
|
#else
|
|
static struct resource omap_vout_resource[2] = {
|
|
};
|
|
#endif
|
|
|
|
static struct platform_device omap_vout_device = {
|
|
.name = "omap_vout",
|
|
.num_resources = ARRAY_SIZE(omap_vout_resource),
|
|
.resource = &omap_vout_resource[0],
|
|
.id = -1,
|
|
};
|
|
static void omap_init_vout(void)
|
|
{
|
|
if (platform_device_register(&omap_vout_device) < 0)
|
|
printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
|
|
}
|
|
#else
|
|
static inline void omap_init_vout(void) {}
|
|
#endif
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* Inorder to avoid any assumptions from bootloader regarding WDT
|
|
* settings, WDT module is reset during init. This enables the watchdog
|
|
* timer. Hence it is required to disable the watchdog after the WDT reset
|
|
* during init. Otherwise the system would reboot as per the default
|
|
* watchdog timer registers settings.
|
|
*/
|
|
#define OMAP_WDT_WPS (0x34)
|
|
#define OMAP_WDT_SPR (0x48)
|
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static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused)
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{
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void __iomem *base;
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int ret;
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if (!oh) {
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pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
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return -EINVAL;
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}
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base = omap_hwmod_get_mpu_rt_va(oh);
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if (!base) {
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pr_err("%s: Could not get the base address for %s\n",
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oh->name, __func__);
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return -EINVAL;
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}
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/* Enable the clocks before accessing the WDT registers */
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ret = omap_hwmod_enable(oh);
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if (ret) {
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pr_err("%s: Could not enable clocks for %s\n",
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oh->name, __func__);
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return ret;
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}
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/* sequence required to disable watchdog */
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__raw_writel(0xAAAA, base + OMAP_WDT_SPR);
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while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
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cpu_relax();
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__raw_writel(0x5555, base + OMAP_WDT_SPR);
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while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
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cpu_relax();
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ret = omap_hwmod_idle(oh);
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if (ret)
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pr_err("%s: Could not disable clocks for %s\n",
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oh->name, __func__);
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return ret;
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}
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static void __init omap_disable_wdt(void)
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{
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if (cpu_class_is_omap2())
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omap_hwmod_for_each_by_class("wd_timer",
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omap2_disable_wdt, NULL);
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return;
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}
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static int __init omap2_init_devices(void)
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{
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/* please keep these calls, and their implementations above,
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* in alphabetical order so they're easier to sort through.
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*/
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omap_disable_wdt();
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omap_hsmmc_reset();
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omap_init_audio();
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omap_init_camera();
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omap_init_mbox();
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omap_init_mcspi();
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omap_init_pmu();
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omap_hdq_init();
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omap_init_sti();
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omap_init_sham();
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omap_init_aes();
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omap_init_vout();
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return 0;
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}
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arch_initcall(omap2_init_devices);
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#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
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struct omap_device_pm_latency omap_wdt_latency[] = {
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[0] = {
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.deactivate_func = omap_device_idle_hwmods,
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.activate_func = omap_device_enable_hwmods,
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.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
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},
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};
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static int __init omap_init_wdt(void)
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{
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int id = -1;
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struct omap_device *od;
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struct omap_hwmod *oh;
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char *oh_name = "wd_timer2";
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char *dev_name = "omap_wdt";
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if (!cpu_class_is_omap2())
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return 0;
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oh = omap_hwmod_lookup(oh_name);
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if (!oh) {
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pr_err("Could not look up wd_timer%d hwmod\n", id);
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return -EINVAL;
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}
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od = omap_device_build(dev_name, id, oh, NULL, 0,
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omap_wdt_latency,
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ARRAY_SIZE(omap_wdt_latency), 0);
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WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
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dev_name, oh->name);
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return 0;
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}
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subsys_initcall(omap_init_wdt);
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#endif
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