Jisheng Zhang f81393a5b2 riscv: extable: fix err reg writing in dedicated uaccess handler ... Mayuresh reported commit 20802d8d47 ("riscv: extable: add a dedicated uaccess handler") breaks the writev02 test case in LTP. This is due to the err reg isn't correctly set with the errno(-EFAULT in writev02 case). First of all, the err and zero regs are reg numbers rather than reg offsets in struct pt_regs; Secondly, regs_set_gpr() should write the regs when offset isn't zero(zero means epc) Fix it by correcting regs_set_gpr() logic and passing the correct reg offset to it. Reported-by: Mayuresh Chitale <mchitale@ventanamicro.com> Fixes: 20802d8d47 ("riscv: extable: add a dedicated uaccess handler") Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2022-02-08 17:02:47 -08:00
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cacheflush.c	RISC-V: Do not use cpumask data structure for hartid bitmap	2022-01-20 09:27:22 -08:00
context.c	riscv: Implement sv48 support	2022-01-19 17:54:09 -08:00
extable.c	riscv: extable: fix err reg writing in dedicated uaccess handler	2022-02-08 17:02:47 -08:00
fault.c	RISC-V Patches for the 5.17 Merge Window, Part 1	2022-01-19 11:38:21 +02:00
hugetlbpage.c	hugetlbfs: remove hugetlb_add_hstate() warning for existing hstate	2020-06-03 20:09:46 -07:00
init.c	riscv/mm: Add XIP_FIXUP for riscv_pfn_base	2022-02-04 13:27:23 -08:00
kasan_init.c	RISC-V: Introduce sv48 support without relocatable kernel	2022-01-19 19:37:44 -08:00
Makefile	riscv: Fixup patch_text panic in ftrace	2021-01-14 15:09:04 -08:00
pageattr.c	RISC-V Patches for the 5.11 Merge Window, Part 1	2020-12-18 10:43:07 -08:00
physaddr.c	riscv: Introduce structure that group all variables regarding kernel mapping	2021-07-05 18:04:00 -07:00
ptdump.c	riscv: Fix PTDUMP output now BPF region moved back to module region	2021-07-06 15:21:27 -07:00
tlbflush.c	RISC-V: Do not use cpumask data structure for hartid bitmap	2022-01-20 09:27:22 -08:00