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f6c86a41e1
This patch does a few simple compatibility-related changes: - change the system register access prototypes to their actual size, - homogenise mpidr accesses with unsigned long, - force the 64bit register values to unsigned long long. Note: the list registers are 64bit on GICv3, but the AArch32 vGIC driver will need to split their values into two 32bit registers: LRn and LRCn. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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.. | ||
arm-gic-acpi.h | ||
arm-gic-v3.h | ||
arm-gic.h | ||
arm-vic.h | ||
chained_irq.h | ||
ingenic.h | ||
irq-omap-intc.h | ||
irq-sa11x0.h | ||
metag-ext.h | ||
metag.h | ||
mips-gic.h | ||
mmp.h | ||
mxs.h | ||
versatile-fpga.h | ||
xtensa-mx.h | ||
xtensa-pic.h |