Philipp Zabel f7089d923e gpu: ipu-v3: limit pixel clock divider to 8-bits ... The DI pixel clock divider bit field is only 8 bits wide for the integer part, so limit the divider to the 1...255 interval before deciding whether the internal clock can be used and before writing to the register. Reported-by: Felix Mellmann <felix.mellmann@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>		2015-03-31 12:03:54 +02:00
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ipu-common.c	gpu: ipu-v3: Fix IC control register offset	2015-01-27 16:28:01 +01:00
ipu-cpmem.c	gpu: ipu-cpmem: Add ipu_cpmem_dump()	2014-09-02 14:55:55 +02:00
ipu-csi.c	[media] gpu: ipu-v3: Make use of media_bus_format enum	2014-11-14 17:55:27 -02:00
ipu-dc.c	imx-drm fixes for IPUv3 DC and i.MX5 IPUv3 IC and TVE	2015-02-11 15:35:26 +10:00
ipu-di.c	gpu: ipu-v3: limit pixel clock divider to 8-bits	2015-03-31 12:03:54 +02:00
ipu-dmfc.c
ipu-dp.c
ipu-ic.c	gpu: ipu-v3: Add Image Converter unit	2014-09-02 14:55:43 +02:00
ipu-prv.h	gpu: ipu-v3: Add ipu_idmac_buffer_is_ready()	2014-09-02 14:55:48 +02:00
ipu-smfc.c	IPUv3 fixes for v3.18	2014-10-07 14:31:14 +10:00
Kconfig	gpu: ipu-v3: Kconfig: Remove SOC_IMX6SL from IMX_IPUV3_CORE Kconfig	2014-09-24 23:50:25 +02:00
Makefile	gpu: ipu-v3: Add Image Converter unit	2014-09-02 14:55:43 +02:00