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The x86 architecture has a set of page fault error codes. These indicate things like whether the fault occurred from a write, or whether it originated in userspace. The SGX hardware architecture has its own per-page memory management metadata (EPCM) [*] and hardware which is separate from the normal x86 MMU. The architecture has a new page fault error code: PF_SGX. This new error code bit is set whenever a page fault occurs as the result of the SGX MMU. These faults occur for a variety of reasons. For instance, an access attempt to enclave memory from outside the enclave causes a PF_SGX fault. PF_SGX would also be set for permission conflicts, such as if a write to an enclave page occurs and the page is marked read-write in the x86 page tables but is read-only in the EPCM. These faults do not always indicate errors, though. SGX pages are encrypted with a key that is destroyed at hardware reset, including suspend. Throwing a SIGSEGV allows user space software to react and recover when these events occur. Include PF_SGX in the PF error codes list and throw SIGSEGV when it is encountered. [*] Intel SDM: 36.5.1 Enclave Page Cache Map (EPCM) [ bp: Add bit 15 to the comment above enum x86_pf_error_code too. ] Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Jarkko Sakkinen <jarkko@kernel.org> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Jethro Beekman <jethro@fortanix.com> Link: https://lkml.kernel.org/r/20201112220135.165028-7-jarkko@kernel.org
26 lines
709 B
C
26 lines
709 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_TRAP_PF_H
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#define _ASM_X86_TRAP_PF_H
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/*
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* Page fault error code bits:
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*
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* bit 0 == 0: no page found 1: protection fault
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* bit 1 == 0: read access 1: write access
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* bit 2 == 0: kernel-mode access 1: user-mode access
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* bit 3 == 1: use of reserved bit detected
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* bit 4 == 1: fault was an instruction fetch
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* bit 5 == 1: protection keys block access
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* bit 15 == 1: SGX MMU page-fault
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*/
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enum x86_pf_error_code {
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X86_PF_PROT = 1 << 0,
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X86_PF_WRITE = 1 << 1,
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X86_PF_USER = 1 << 2,
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X86_PF_RSVD = 1 << 3,
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X86_PF_INSTR = 1 << 4,
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X86_PF_PK = 1 << 5,
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X86_PF_SGX = 1 << 15,
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};
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#endif /* _ASM_X86_TRAP_PF_H */
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