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006c7f1844
Kevin discovered that commit c8d82ff68f
("ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod
database") broke CORE idle on OMAP3. This prevents device low power
states.
The root cause is that the 32K sync timer IP block does not support
smart-idle mode[1], and so the hwmod code keeps the IP block in
no-idle mode while it is active. This in turn prevents the WKUP
clockdomain from transitioning to idle. There is a hardcoded sleep
dependency that prevents the CORE_L3 and CORE_CM clockdomains from
transitioning to idle when the WKUP clockdomain is active[2], so the
chip cannot enter any device low power states.
It turns out that there is no need to take the 32k sync timer out of
idle. The IP block itself probably does not have any native idle
handling at all, due to its simplicity. Furthermore, the PRCM will
never request target idle for this IP block while the kernel is
running, due to the sleep dependency that prevents the WKUP
clockdomain from idling while the CORE_L3 clockdomain is active. So
we can safely leave the 32k sync timer in target-force-idle mode, even
while we continue to access it.
This workaround is implemented by defining a new clockdomain flag,
CLKDM_ACTIVE_WITH_MPU, that indicates that the clockdomain is
guaranteed to be active whenever the MPU is inactive. If an IP
block's main functional clock exists inside this clockdomain, and the
IP block does not support smart-idle modes, then the hwmod code will
place the IP block into target force-idle mode even when enabled. The
WKUP clockdomains on OMAP3/4 are marked with this flag. (On OMAP2xxx,
no OCP header existed on the 32k sync timer.) Other clockdomains also
should be marked with this flag, but those changes are deferred until
a later merge window, to create a minimal fix.
Another theoretically clean fix for this problem would be to implement
PM runtime-based control for 32k sync timer accesses. These PM
runtime calls would need to located in a custom clocksource, since the
32k sync timer is currently used as an MMIO clocksource. But in
practice, there would be little benefit to doing so; and there would
be some cost, due to the addition of unnecessary lines of code and the
additional CPU overhead of the PM runtime and hwmod code - unnecessary
in this case.
Another possible fix would have been to modify the pm34xx.c code to
force the IP block idle before entering WFI. But this would not have
been an acceptable approach: we are trying to remove this type of
centralized IP block idle control from the PM code.
This patch is a collaboration between Kevin Hilman <khilman@ti.com>
and Paul Walmsley <paul@pwsan.com>.
Thanks to Vaibhav Hiremath <hvaibhav@ti.com> for providing comments on
an earlier version of this patch. Thanks to Tero Kristo
<t-kristo@ti.com> for identifying a bug in an earlier version of this
patch. Thanks to Benoît Cousson <b-cousson@ti.com> for identifying
some bugs in several versions of this patch and for implementation
comments.
References:
1. Table 16-96 "REG_32KSYNCNT_SYSCONFIG" of the OMAP34xx TRM Rev. ZU
(SWPU223U), available from:
http://www.ti.com/pdfs/wtbu/OMAP34x_ES3.1.x_PUBLIC_TRM_vzU.zip
2. Table 4-72 "Sleep Dependencies" of the OMAP34xx TRM Rev. ZU
(SWPU223U)
3. ibid.
Cc: Tony Lindgren <tony@atomide.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
92 lines
2.6 KiB
C
92 lines
2.6 KiB
C
/*
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* OMAP2/3 clockdomain common data
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*
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* Copyright (C) 2008-2011 Texas Instruments, Inc.
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* Copyright (C) 2008-2010 Nokia Corporation
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*
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* Paul Walmsley, Jouni Högander
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*
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* This file contains clockdomains and clockdomain wakeup/sleep
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* dependencies for the OMAP2/3 chips. Some notes:
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*
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* A useful validation rule for struct clockdomain: Any clockdomain
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* referenced by a wkdep_srcs or sleepdep_srcs array must have a
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* dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just
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* software-controllable dependencies. Non-software-controllable
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* dependencies do exist, but they are not encoded below (yet).
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*
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* 24xx does not support programmable sleep dependencies (SLEEPDEP)
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*
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* The overly-specific dep_bit names are due to a bit name collision
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* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
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* value are the same for all powerdomains: 2
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*
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* XXX should dep_bit be a mask, so we can test to see if it is 0 as a
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* sanity check?
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* XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
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*/
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/*
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* To-Do List
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* -> Port the Sleep/Wakeup dependencies for the domains
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* from the Power domain framework
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include "clockdomain.h"
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#include "prm2xxx_3xxx.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-24xx.h"
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#include "cm-regbits-34xx.h"
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#include "cm-regbits-44xx.h"
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#include "prm-regbits-24xx.h"
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#include "prm-regbits-34xx.h"
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/*
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* Clockdomain dependencies for wkdeps/sleepdeps
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*
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* XXX Hardware dependencies (e.g., dependencies that cannot be
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* changed in software) are not included here yet, but should be.
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*/
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/* Wakeup dependency source arrays */
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/* 2xxx-specific possible dependencies */
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/* 2xxx PM_WKDEP_GFX: CORE, MPU, WKUP */
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struct clkdm_dep gfx_24xx_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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{ .clkdm_name = "core_l4_clkdm" },
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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/* 2xxx PM_WKDEP_DSP: CORE, MPU, WKUP */
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struct clkdm_dep dsp_24xx_wkdeps[] = {
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{ .clkdm_name = "core_l3_clkdm" },
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{ .clkdm_name = "core_l4_clkdm" },
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{ .clkdm_name = "mpu_clkdm" },
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{ .clkdm_name = "wkup_clkdm" },
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{ NULL },
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};
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/*
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* OMAP2/3-common clockdomains
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*
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* Even though the 2420 has a single PRCM module from the
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* interconnect's perspective, internally it does appear to have
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* separate PRM and CM clockdomains. The usual test case is
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* sys_clkout/sys_clkout2.
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*/
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/* This is an implicit clockdomain - it is never defined as such in TRM */
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struct clockdomain wkup_common_clkdm = {
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.name = "wkup_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.dep_bit = OMAP_EN_WKUP_SHIFT,
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.flags = CLKDM_ACTIVE_WITH_MPU,
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};
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