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ab7b2ffcf5
This gets rid of need for some exported driver APIs, and simplifies the initialization of the PRM driver. Done in preparation to make PRM a separate driver. The init data is now also passed to the SoC specific implementations, allowing future expansion to add feature flags etc. Signed-off-by: Tero Kristo <t-kristo@ti.com>
153 lines
6.5 KiB
C
153 lines
6.5 KiB
C
/*
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* OMAP3xxx Power/Reset Management (PRM) register definitions
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*
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* Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
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* Copyright (C) 2008-2010 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The PRM hardware modules on the OMAP2/3 are quite similar to each
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* other. The PRM on OMAP4 has a new register layout, and is handled
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* in a separate file.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
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#define __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
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#include "prcm-common.h"
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#include "prm.h"
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#include "prm2xxx_3xxx.h"
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#define OMAP34XX_PRM_REGADDR(module, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
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/*
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* OMAP3-specific global PRM registers
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* Use {read,write}l_relaxed() with these registers.
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*
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* With a few exceptions, these are the register names beginning with
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* PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE
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* bits.)
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*/
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#define OMAP3_PRM_REVISION_OFFSET 0x0004
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#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
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#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
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#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
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#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
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#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
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#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
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#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
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#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
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#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
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#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
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#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
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#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
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#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
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#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
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#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
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#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
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#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
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#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
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#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
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#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
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#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
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#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
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#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
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#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
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#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
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#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
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#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
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#define OMAP3_PRM_RSTST_OFFSET 0x0058
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#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
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#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
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#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
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#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
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#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
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#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
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#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
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#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
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#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
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#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
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#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
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#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
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#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
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#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
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#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
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#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
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#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
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#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
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#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
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#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
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#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
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#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
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#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
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#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
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#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
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#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
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#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
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#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
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#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
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#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
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#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
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#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
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#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
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#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
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#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
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#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
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#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
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#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
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#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
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#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
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#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
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#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
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#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
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#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
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#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
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/* OMAP3 specific register offsets */
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#define OMAP3430ES2_PM_WKEN3 0x00f0
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#define OMAP3430ES2_PM_WKST3 0x00b8
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#define OMAP3430_PM_MPUGRPSEL 0x00a4
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#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
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#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
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#define OMAP3430_PM_IVAGRPSEL 0x00a8
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#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
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#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
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#define OMAP3430_PM_PREPWSTST 0x00e8
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#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
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#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
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#ifndef __ASSEMBLER__
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/*
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* OMAP3 access functions for voltage controller (VC) and
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* voltage proccessor (VP) in the PRM.
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*/
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extern u32 omap3_prm_vcvp_read(u8 offset);
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extern void omap3_prm_vcvp_write(u32 val, u8 offset);
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extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
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int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data);
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void omap3xxx_prm_iva_idle(void);
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void omap3_prm_reset_modem(void);
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int omap3xxx_prm_clear_global_cold_reset(void);
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void omap3_prm_save_scratchpad_contents(u32 *ptr);
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void omap3_prm_init_pm(bool has_uart4, bool has_iva);
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#endif /* __ASSEMBLER */
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#endif
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