mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-30 16:07:39 +00:00
39c5b2f6f2
Add toprgu reset-controller header file for MT8195 platform. Signed-off-by: Christine Zhu <Christine.Zhu@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20210726122901.12195-3-Christine.Zhu@mediatek.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
29 lines
1.1 KiB
C
29 lines
1.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/
|
|
/*
|
|
* Copyright (c) 2021 MediaTek Inc.
|
|
* Author: Christine Zhu <christine.zhu@mediatek.com>
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
|
|
#define _DT_BINDINGS_RESET_CONTROLLER_MT8195
|
|
|
|
#define MT8195_TOPRGU_CONN_MCU_SW_RST 0
|
|
#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1
|
|
#define MT8195_TOPRGU_APU_SW_RST 2
|
|
#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6
|
|
#define MT8195_TOPRGU_MMSYS_SW_RST 7
|
|
#define MT8195_TOPRGU_MFG_SW_RST 8
|
|
#define MT8195_TOPRGU_VENC_SW_RST 9
|
|
#define MT8195_TOPRGU_VDEC_SW_RST 10
|
|
#define MT8195_TOPRGU_IMG_SW_RST 11
|
|
#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13
|
|
#define MT8195_TOPRGU_AUDIO_SW_RST 14
|
|
#define MT8195_TOPRGU_CAMSYS_SW_RST 15
|
|
#define MT8195_TOPRGU_EDPTX_SW_RST 16
|
|
#define MT8195_TOPRGU_ADSPSYS_SW_RST 21
|
|
#define MT8195_TOPRGU_DPTX_SW_RST 22
|
|
#define MT8195_TOPRGU_SPMI_MST_SW_RST 23
|
|
|
|
#define MT8195_TOPRGU_SW_RST_NUM 16
|
|
|
|
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
|