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452e69b58c
Allocating and enabling a flush queue is in fact something we can reasonably do while a DMA domain is active, without having to rebuild it from scratch. Thus we can allow a strict -> non-strict transition from sysfs without requiring to unbind the device's driver, which is of particular interest to users who want to make selective relaxations to critical devices like the one serving their root filesystem. Disabling and draining a queue also seems technically possible to achieve without rebuilding the whole domain, but would certainly be more involved. Furthermore there's not such a clear use-case for tightening up security *after* the device may already have done whatever it is that you don't trust it not to do, so we only consider the relaxation case. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/d652966348c78457c38bf18daf369272a4ebc2c9.1628682049.git.robin.murphy@arm.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
93 lines
2.2 KiB
C
93 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014-2015 ARM Ltd.
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*/
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#ifndef __DMA_IOMMU_H
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#define __DMA_IOMMU_H
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#include <linux/errno.h>
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#include <linux/types.h>
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#ifdef CONFIG_IOMMU_DMA
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#include <linux/dma-mapping.h>
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#include <linux/iommu.h>
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#include <linux/msi.h>
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/* Domain management interface for IOMMU drivers */
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int iommu_get_dma_cookie(struct iommu_domain *domain);
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int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base);
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void iommu_put_dma_cookie(struct iommu_domain *domain);
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/* Setup call for arch DMA mapping code */
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void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 dma_limit);
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int iommu_dma_init_fq(struct iommu_domain *domain);
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/* The DMA API isn't _quite_ the whole story, though... */
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/*
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* iommu_dma_prepare_msi() - Map the MSI page in the IOMMU device
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*
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* The MSI page will be stored in @desc.
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*
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* Return: 0 on success otherwise an error describing the failure.
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*/
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int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr);
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/* Update the MSI message if required. */
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void iommu_dma_compose_msi_msg(struct msi_desc *desc,
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struct msi_msg *msg);
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void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list);
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void iommu_dma_free_cpu_cached_iovas(unsigned int cpu,
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struct iommu_domain *domain);
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extern bool iommu_dma_forcedac;
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#else /* CONFIG_IOMMU_DMA */
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struct iommu_domain;
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struct msi_desc;
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struct msi_msg;
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struct device;
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static inline void iommu_setup_dma_ops(struct device *dev, u64 dma_base,
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u64 dma_limit)
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{
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}
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static inline int iommu_dma_init_fq(struct iommu_domain *domain)
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{
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return -EINVAL;
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}
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static inline int iommu_get_dma_cookie(struct iommu_domain *domain)
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{
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return -ENODEV;
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}
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static inline int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
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{
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return -ENODEV;
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}
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static inline void iommu_put_dma_cookie(struct iommu_domain *domain)
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{
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}
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static inline int iommu_dma_prepare_msi(struct msi_desc *desc,
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phys_addr_t msi_addr)
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{
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return 0;
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}
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static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc,
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struct msi_msg *msg)
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{
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}
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static inline void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list)
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{
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}
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#endif /* CONFIG_IOMMU_DMA */
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#endif /* __DMA_IOMMU_H */
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