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52beb1fc23
qcom_scm_set_cold/warm_boot_addr() currently take a cpumask parameter, but it's not very useful because at the end we always set the same entry address for all CPUs. This also allows speeding up probe of cpuidle-qcom-spm a bit because only one SCM call needs to be made to the TrustZone firmware, instead of one per CPU. The main reason for this change is that it allows implementing the "multi-cluster" variant of the set_boot_addr() call more easily without having to rely on functions that break in certain build configurations or that are not exported to modules. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201130505.257379-4-stephan@gerhold.net
127 lines
4.1 KiB
C
127 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
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* Copyright (C) 2015 Linaro Ltd.
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*/
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#ifndef __QCOM_SCM_H
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#define __QCOM_SCM_H
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#include <linux/err.h>
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#include <linux/types.h>
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#include <linux/cpumask.h>
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#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
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#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
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#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
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#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
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struct qcom_scm_hdcp_req {
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u32 addr;
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u32 val;
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};
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struct qcom_scm_vmperm {
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int vmid;
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int perm;
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};
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enum qcom_scm_ocmem_client {
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QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
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QCOM_SCM_OCMEM_GRAPHICS_ID,
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QCOM_SCM_OCMEM_VIDEO_ID,
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QCOM_SCM_OCMEM_LP_AUDIO_ID,
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QCOM_SCM_OCMEM_SENSORS_ID,
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QCOM_SCM_OCMEM_OTHER_OS_ID,
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QCOM_SCM_OCMEM_DEBUG_ID,
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};
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enum qcom_scm_sec_dev_id {
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QCOM_SCM_MDSS_DEV_ID = 1,
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QCOM_SCM_OCMEM_DEV_ID = 5,
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QCOM_SCM_PCIE0_DEV_ID = 11,
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QCOM_SCM_PCIE1_DEV_ID = 12,
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QCOM_SCM_GFX_DEV_ID = 18,
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QCOM_SCM_UFS_DEV_ID = 19,
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QCOM_SCM_ICE_DEV_ID = 20,
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};
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enum qcom_scm_ice_cipher {
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QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,
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QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,
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QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,
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QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,
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};
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#define QCOM_SCM_VMID_HLOS 0x3
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#define QCOM_SCM_VMID_MSS_MSA 0xF
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#define QCOM_SCM_VMID_WLAN 0x18
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#define QCOM_SCM_VMID_WLAN_CE 0x19
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#define QCOM_SCM_PERM_READ 0x4
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#define QCOM_SCM_PERM_WRITE 0x2
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#define QCOM_SCM_PERM_EXEC 0x1
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#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
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#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
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extern bool qcom_scm_is_available(void);
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extern int qcom_scm_set_cold_boot_addr(void *entry);
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extern int qcom_scm_set_warm_boot_addr(void *entry);
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extern void qcom_scm_cpu_power_down(u32 flags);
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extern int qcom_scm_set_remote_state(u32 state, u32 id);
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struct qcom_scm_pas_metadata {
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void *ptr;
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dma_addr_t phys;
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ssize_t size;
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};
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extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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size_t size,
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struct qcom_scm_pas_metadata *ctx);
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void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
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extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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phys_addr_t size);
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extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
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extern int qcom_scm_pas_shutdown(u32 peripheral);
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extern bool qcom_scm_pas_supported(u32 peripheral);
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extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
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extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
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extern bool qcom_scm_restore_sec_cfg_available(void);
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extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
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extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
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extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
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extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);
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extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
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u32 cp_nonpixel_start,
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u32 cp_nonpixel_size);
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extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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unsigned int *src,
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const struct qcom_scm_vmperm *newvm,
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unsigned int dest_cnt);
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extern bool qcom_scm_ocmem_lock_available(void);
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extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
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u32 size, u32 mode);
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extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
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u32 size);
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extern bool qcom_scm_ice_available(void);
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extern int qcom_scm_ice_invalidate_key(u32 index);
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extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
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enum qcom_scm_ice_cipher cipher,
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u32 data_unit_size);
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extern bool qcom_scm_hdcp_available(void);
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extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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u32 *resp);
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extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
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extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
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extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
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u64 limit_node, u32 node_id, u64 version);
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extern int qcom_scm_lmh_profile_change(u32 profile_id);
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extern bool qcom_scm_lmh_dcvsh_available(void);
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#endif
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