linux-stable/drivers/soc/tegra
Dmitry Osipenko f880ee9e96 soc/tegra: pmc: Add core power domain
NVIDIA Tegra SoCs have multiple power domains, each domain corresponds
to an external SoC power rail. Core power domain covers vast majority of
hardware blocks within a Tegra SoC. The voltage of a power domain should
be set to a level which satisfies all devices within the power domain.
Add support for the core power domain which controls voltage state of the
domain. This allows us to support system-wide DVFS on Tegra20-210 SoCs.
The PMC powergate domains now are sub-domains of the core domain, this
requires device-tree updating, older DTBs are unaffected and will continue
to work as before.

Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
[treding@nvidia.com: squash lockdep class removal patch]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-02 10:58:42 +02:00
..
fuse soc/tegra: Changes for v5.11-rc1 2020-11-27 17:56:10 +01:00
common.c soc/tegra: Add devm_tegra_core_dev_init_opp_table() 2021-06-01 12:14:59 +02:00
flowctrl.c remove ioremap_nocache and devm_ioremap_nocache 2020-01-06 09:45:59 +01:00
Kconfig soc/tegra: pmc: Add core power domain 2021-06-02 10:58:42 +02:00
Makefile soc/tegra: regulators: Add regulators coupler for Tegra30 2019-10-29 14:02:59 +01:00
pmc.c soc/tegra: pmc: Add core power domain 2021-06-02 10:58:42 +02:00
powergate-bpmp.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 2019-06-05 17:36:37 +02:00
regulators-tegra20.c soc/tegra: regulators: Bump voltages on system reboot 2021-06-01 12:14:22 +02:00
regulators-tegra30.c soc/tegra: regulators: Bump voltages on system reboot 2021-06-01 12:14:22 +02:00