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![Wolfram Sang](/assets/img/avatar_default.png)
The core will do this for us now. Signed-off-by: Wolfram Sang <wsa-dev@sang-engineering.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Peter Korsgaard <peter@korsgaard.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Neil Horman <nhorman@tuxdriver.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Ray Jui <ray.jui@broadcom.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
562 lines
13 KiB
C
562 lines
13 KiB
C
/*
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* I2C bus driver for the SH7760 I2C Interfaces.
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*
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* (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
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*
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* licensed under the terms outlined in the file COPYING.
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*
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*/
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <asm/clock.h>
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#include <asm/i2c-sh7760.h>
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/* register offsets */
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#define I2CSCR 0x0 /* slave ctrl */
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#define I2CMCR 0x4 /* master ctrl */
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#define I2CSSR 0x8 /* slave status */
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#define I2CMSR 0xC /* master status */
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#define I2CSIER 0x10 /* slave irq enable */
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#define I2CMIER 0x14 /* master irq enable */
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#define I2CCCR 0x18 /* clock dividers */
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#define I2CSAR 0x1c /* slave address */
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#define I2CMAR 0x20 /* master address */
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#define I2CRXTX 0x24 /* data port */
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#define I2CFCR 0x28 /* fifo control */
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#define I2CFSR 0x2C /* fifo status */
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#define I2CFIER 0x30 /* fifo irq enable */
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#define I2CRFDR 0x34 /* rx fifo count */
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#define I2CTFDR 0x38 /* tx fifo count */
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#define REGSIZE 0x3C
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#define MCR_MDBS 0x80 /* non-fifo mode switch */
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#define MCR_FSCL 0x40 /* override SCL pin */
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#define MCR_FSDA 0x20 /* override SDA pin */
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#define MCR_OBPC 0x10 /* override pins */
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#define MCR_MIE 0x08 /* master if enable */
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#define MCR_TSBE 0x04
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#define MCR_FSB 0x02 /* force stop bit */
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#define MCR_ESG 0x01 /* en startbit gen. */
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#define MSR_MNR 0x40 /* nack received */
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#define MSR_MAL 0x20 /* arbitration lost */
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#define MSR_MST 0x10 /* sent a stop */
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#define MSR_MDE 0x08
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#define MSR_MDT 0x04
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#define MSR_MDR 0x02
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#define MSR_MAT 0x01 /* slave addr xfer done */
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#define MIE_MNRE 0x40 /* nack irq en */
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#define MIE_MALE 0x20 /* arblos irq en */
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#define MIE_MSTE 0x10 /* stop irq en */
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#define MIE_MDEE 0x08
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#define MIE_MDTE 0x04
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#define MIE_MDRE 0x02
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#define MIE_MATE 0x01 /* address sent irq en */
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#define FCR_RFRST 0x02 /* reset rx fifo */
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#define FCR_TFRST 0x01 /* reset tx fifo */
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#define FSR_TEND 0x04 /* last byte sent */
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#define FSR_RDF 0x02 /* rx fifo trigger */
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#define FSR_TDFE 0x01 /* tx fifo empty */
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#define FIER_TEIE 0x04 /* tx fifo empty irq en */
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#define FIER_RXIE 0x02 /* rx fifo trig irq en */
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#define FIER_TXIE 0x01 /* tx fifo trig irq en */
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#define FIFO_SIZE 16
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struct cami2c {
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void __iomem *iobase;
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struct i2c_adapter adap;
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/* message processing */
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struct i2c_msg *msg;
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#define IDF_SEND 1
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#define IDF_RECV 2
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#define IDF_STOP 4
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int flags;
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#define IDS_DONE 1
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#define IDS_ARBLOST 2
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#define IDS_NACK 4
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int status;
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struct completion xfer_done;
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int irq;
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struct resource *ioarea;
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};
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static inline void OUT32(struct cami2c *cam, int reg, unsigned long val)
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{
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__raw_writel(val, (unsigned long)cam->iobase + reg);
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}
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static inline unsigned long IN32(struct cami2c *cam, int reg)
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{
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return __raw_readl((unsigned long)cam->iobase + reg);
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}
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static irqreturn_t sh7760_i2c_irq(int irq, void *ptr)
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{
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struct cami2c *id = ptr;
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struct i2c_msg *msg = id->msg;
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char *data = msg->buf;
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unsigned long msr, fsr, fier, len;
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msr = IN32(id, I2CMSR);
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fsr = IN32(id, I2CFSR);
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/* arbitration lost */
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if (msr & MSR_MAL) {
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OUT32(id, I2CMCR, 0);
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OUT32(id, I2CSCR, 0);
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OUT32(id, I2CSAR, 0);
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id->status |= IDS_DONE | IDS_ARBLOST;
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goto out;
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}
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if (msr & MSR_MNR) {
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/* NACK handling is very screwed up. After receiving a
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* NAK IRQ one has to wait a bit before writing to any
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* registers, or the ctl will lock up. After that delay
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* do a normal i2c stop. Then wait at least 1 ms before
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* attempting another transfer or ctl will stop working
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*/
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udelay(100); /* wait or risk ctl hang */
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OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
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OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
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OUT32(id, I2CFIER, 0);
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OUT32(id, I2CMIER, MIE_MSTE);
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OUT32(id, I2CSCR, 0);
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OUT32(id, I2CSAR, 0);
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id->status |= IDS_NACK;
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msr &= ~MSR_MAT;
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fsr = 0;
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/* In some cases the MST bit is also set. */
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}
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/* i2c-stop was sent */
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if (msr & MSR_MST) {
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id->status |= IDS_DONE;
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goto out;
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}
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/* i2c slave addr was sent; set to "normal" operation */
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if (msr & MSR_MAT)
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OUT32(id, I2CMCR, MCR_MIE);
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fier = IN32(id, I2CFIER);
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if (fsr & FSR_RDF) {
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len = IN32(id, I2CRFDR);
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if (msg->len <= len) {
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if (id->flags & IDF_STOP) {
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OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
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OUT32(id, I2CFIER, 0);
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/* manual says: wait >= 0.5 SCL times */
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udelay(5);
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/* next int should be MST */
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} else {
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id->status |= IDS_DONE;
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/* keep the RDF bit: ctrl holds SCL low
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* until the setup for the next i2c_msg
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* clears this bit.
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*/
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fsr &= ~FSR_RDF;
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}
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}
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while (msg->len && len) {
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*data++ = IN32(id, I2CRXTX);
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msg->len--;
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len--;
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}
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if (msg->len) {
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len = (msg->len >= FIFO_SIZE) ? FIFO_SIZE - 1
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: msg->len - 1;
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OUT32(id, I2CFCR, FCR_TFRST | ((len & 0xf) << 4));
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}
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} else if (id->flags & IDF_SEND) {
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if ((fsr & FSR_TEND) && (msg->len < 1)) {
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if (id->flags & IDF_STOP) {
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OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
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} else {
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id->status |= IDS_DONE;
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/* keep the TEND bit: ctl holds SCL low
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* until the setup for the next i2c_msg
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* clears this bit.
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*/
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fsr &= ~FSR_TEND;
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}
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}
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if (fsr & FSR_TDFE) {
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while (msg->len && (IN32(id, I2CTFDR) < FIFO_SIZE)) {
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OUT32(id, I2CRXTX, *data++);
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msg->len--;
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}
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if (msg->len < 1) {
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fier &= ~FIER_TXIE;
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OUT32(id, I2CFIER, fier);
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} else {
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len = (msg->len >= FIFO_SIZE) ? 2 : 0;
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OUT32(id, I2CFCR,
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FCR_RFRST | ((len & 3) << 2));
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}
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}
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}
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out:
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if (id->status & IDS_DONE) {
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OUT32(id, I2CMIER, 0);
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OUT32(id, I2CFIER, 0);
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id->msg = NULL;
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complete(&id->xfer_done);
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}
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/* clear status flags and ctrl resumes work */
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OUT32(id, I2CMSR, ~msr);
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OUT32(id, I2CFSR, ~fsr);
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OUT32(id, I2CSSR, 0);
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return IRQ_HANDLED;
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}
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/* prepare and start a master receive operation */
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static void sh7760_i2c_mrecv(struct cami2c *id)
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{
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int len;
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id->flags |= IDF_RECV;
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/* set the slave addr reg; otherwise rcv wont work! */
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OUT32(id, I2CSAR, 0xfe);
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OUT32(id, I2CMAR, (id->msg->addr << 1) | 1);
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/* adjust rx fifo trigger */
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if (id->msg->len >= FIFO_SIZE)
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len = FIFO_SIZE - 1; /* trigger at fifo full */
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else
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len = id->msg->len - 1; /* trigger before all received */
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OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
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OUT32(id, I2CFCR, FCR_TFRST | ((len & 0xF) << 4));
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OUT32(id, I2CMSR, 0);
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OUT32(id, I2CMCR, MCR_MIE | MCR_ESG);
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OUT32(id, I2CMIER, MIE_MNRE | MIE_MALE | MIE_MSTE | MIE_MATE);
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OUT32(id, I2CFIER, FIER_RXIE);
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}
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/* prepare and start a master send operation */
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static void sh7760_i2c_msend(struct cami2c *id)
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{
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int len;
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id->flags |= IDF_SEND;
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/* set the slave addr reg; otherwise xmit wont work! */
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OUT32(id, I2CSAR, 0xfe);
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OUT32(id, I2CMAR, (id->msg->addr << 1) | 0);
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/* adjust tx fifo trigger */
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if (id->msg->len >= FIFO_SIZE)
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len = 2; /* trig: 2 bytes left in TX fifo */
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else
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len = 0; /* trig: 8 bytes left in TX fifo */
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OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
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OUT32(id, I2CFCR, FCR_RFRST | ((len & 3) << 2));
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while (id->msg->len && IN32(id, I2CTFDR) < FIFO_SIZE) {
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OUT32(id, I2CRXTX, *(id->msg->buf));
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(id->msg->len)--;
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(id->msg->buf)++;
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}
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OUT32(id, I2CMSR, 0);
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OUT32(id, I2CMCR, MCR_MIE | MCR_ESG);
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OUT32(id, I2CFSR, 0);
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OUT32(id, I2CMIER, MIE_MNRE | MIE_MALE | MIE_MSTE | MIE_MATE);
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OUT32(id, I2CFIER, FIER_TEIE | (id->msg->len ? FIER_TXIE : 0));
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}
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static inline int sh7760_i2c_busy_check(struct cami2c *id)
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{
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return (IN32(id, I2CMCR) & MCR_FSDA);
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}
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static int sh7760_i2c_master_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msgs,
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int num)
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{
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struct cami2c *id = adap->algo_data;
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int i, retr;
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if (sh7760_i2c_busy_check(id)) {
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dev_err(&adap->dev, "sh7760-i2c%d: bus busy!\n", adap->nr);
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return -EBUSY;
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}
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i = 0;
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while (i < num) {
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retr = adap->retries;
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retry:
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id->flags = ((i == (num-1)) ? IDF_STOP : 0);
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id->status = 0;
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id->msg = msgs;
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init_completion(&id->xfer_done);
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if (msgs->flags & I2C_M_RD)
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sh7760_i2c_mrecv(id);
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else
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sh7760_i2c_msend(id);
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wait_for_completion(&id->xfer_done);
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if (id->status == 0) {
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num = -EIO;
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break;
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}
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if (id->status & IDS_NACK) {
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/* wait a bit or i2c module stops working */
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mdelay(1);
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num = -EREMOTEIO;
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break;
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}
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if (id->status & IDS_ARBLOST) {
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if (retr--) {
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mdelay(2);
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goto retry;
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}
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num = -EREMOTEIO;
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break;
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}
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msgs++;
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i++;
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}
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id->msg = NULL;
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id->flags = 0;
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id->status = 0;
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OUT32(id, I2CMCR, 0);
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OUT32(id, I2CMSR, 0);
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OUT32(id, I2CMIER, 0);
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OUT32(id, I2CFIER, 0);
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/* reset slave module registers too: master mode enables slave
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* module for receive ops (ack, data). Without this reset,
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* eternal bus activity might be reported after NACK / ARBLOST.
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*/
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OUT32(id, I2CSCR, 0);
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OUT32(id, I2CSAR, 0);
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OUT32(id, I2CSSR, 0);
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return num;
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}
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static u32 sh7760_i2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
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}
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static const struct i2c_algorithm sh7760_i2c_algo = {
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.master_xfer = sh7760_i2c_master_xfer,
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.functionality = sh7760_i2c_func,
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};
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/* calculate CCR register setting for a desired scl clock. SCL clock is
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* derived from I2C module clock (iclk) which in turn is derived from
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* peripheral module clock (mclk, usually around 33MHz):
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* iclk = mclk/(CDF + 1). iclk must be < 20MHz.
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* scl = iclk/(SCGD*8 + 20).
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*/
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static int calc_CCR(unsigned long scl_hz)
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{
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struct clk *mclk;
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unsigned long mck, m1, dff, odff, iclk;
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signed char cdf, cdfm;
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int scgd, scgdm, scgds;
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mclk = clk_get(NULL, "peripheral_clk");
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if (IS_ERR(mclk)) {
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return PTR_ERR(mclk);
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} else {
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mck = mclk->rate;
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clk_put(mclk);
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}
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odff = scl_hz;
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scgdm = cdfm = m1 = 0;
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for (cdf = 3; cdf >= 0; cdf--) {
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iclk = mck / (1 + cdf);
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if (iclk >= 20000000)
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continue;
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scgds = ((iclk / scl_hz) - 20) >> 3;
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for (scgd = scgds; (scgd < 63) && scgd <= scgds + 1; scgd++) {
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m1 = iclk / (20 + (scgd << 3));
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dff = abs(scl_hz - m1);
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if (dff < odff) {
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odff = dff;
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cdfm = cdf;
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scgdm = scgd;
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}
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}
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}
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/* fail if more than 25% off of requested SCL */
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if (odff > (scl_hz >> 2))
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return -EINVAL;
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/* create a CCR register value */
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return ((scgdm << 2) | cdfm);
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}
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static int sh7760_i2c_probe(struct platform_device *pdev)
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{
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struct sh7760_i2c_platdata *pd;
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struct resource *res;
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struct cami2c *id;
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int ret;
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pd = dev_get_platdata(&pdev->dev);
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if (!pd) {
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dev_err(&pdev->dev, "no platform_data!\n");
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ret = -ENODEV;
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goto out0;
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}
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id = kzalloc(sizeof(struct cami2c), GFP_KERNEL);
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if (!id) {
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dev_err(&pdev->dev, "no mem for private data\n");
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ret = -ENOMEM;
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goto out0;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "no mmio resources\n");
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ret = -ENODEV;
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goto out1;
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}
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id->ioarea = request_mem_region(res->start, REGSIZE, pdev->name);
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if (!id->ioarea) {
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dev_err(&pdev->dev, "mmio already reserved\n");
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ret = -EBUSY;
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goto out1;
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}
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id->iobase = ioremap(res->start, REGSIZE);
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if (!id->iobase) {
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dev_err(&pdev->dev, "cannot ioremap\n");
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|
ret = -ENODEV;
|
|
goto out2;
|
|
}
|
|
|
|
id->irq = platform_get_irq(pdev, 0);
|
|
|
|
id->adap.nr = pdev->id;
|
|
id->adap.algo = &sh7760_i2c_algo;
|
|
id->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
|
|
id->adap.retries = 3;
|
|
id->adap.algo_data = id;
|
|
id->adap.dev.parent = &pdev->dev;
|
|
snprintf(id->adap.name, sizeof(id->adap.name),
|
|
"SH7760 I2C at %08lx", (unsigned long)res->start);
|
|
|
|
OUT32(id, I2CMCR, 0);
|
|
OUT32(id, I2CMSR, 0);
|
|
OUT32(id, I2CMIER, 0);
|
|
OUT32(id, I2CMAR, 0);
|
|
OUT32(id, I2CSIER, 0);
|
|
OUT32(id, I2CSAR, 0);
|
|
OUT32(id, I2CSCR, 0);
|
|
OUT32(id, I2CSSR, 0);
|
|
OUT32(id, I2CFIER, 0);
|
|
OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
|
|
OUT32(id, I2CFSR, 0);
|
|
|
|
ret = calc_CCR(pd->speed_khz * 1000);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "invalid SCL clock: %dkHz\n",
|
|
pd->speed_khz);
|
|
goto out3;
|
|
}
|
|
OUT32(id, I2CCCR, ret);
|
|
|
|
if (request_irq(id->irq, sh7760_i2c_irq, 0,
|
|
SH7760_I2C_DEVNAME, id)) {
|
|
dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
|
|
ret = -EBUSY;
|
|
goto out3;
|
|
}
|
|
|
|
ret = i2c_add_numbered_adapter(&id->adap);
|
|
if (ret < 0)
|
|
goto out4;
|
|
|
|
platform_set_drvdata(pdev, id);
|
|
|
|
dev_info(&pdev->dev, "%d kHz mmio %08x irq %d\n",
|
|
pd->speed_khz, res->start, id->irq);
|
|
|
|
return 0;
|
|
|
|
out4:
|
|
free_irq(id->irq, id);
|
|
out3:
|
|
iounmap(id->iobase);
|
|
out2:
|
|
release_resource(id->ioarea);
|
|
kfree(id->ioarea);
|
|
out1:
|
|
kfree(id);
|
|
out0:
|
|
return ret;
|
|
}
|
|
|
|
static int sh7760_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct cami2c *id = platform_get_drvdata(pdev);
|
|
|
|
i2c_del_adapter(&id->adap);
|
|
free_irq(id->irq, id);
|
|
iounmap(id->iobase);
|
|
release_resource(id->ioarea);
|
|
kfree(id->ioarea);
|
|
kfree(id);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sh7760_i2c_drv = {
|
|
.driver = {
|
|
.name = SH7760_I2C_DEVNAME,
|
|
},
|
|
.probe = sh7760_i2c_probe,
|
|
.remove = sh7760_i2c_remove,
|
|
};
|
|
|
|
module_platform_driver(sh7760_i2c_drv);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("SH7760 I2C bus driver");
|
|
MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>");
|