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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Fabio Estevam](/assets/img/avatar_default.png)
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
358 lines
12 KiB
C
358 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2016 Freescale Semiconductor, Inc.
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// Copyright 2017-2018 NXP.
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-imx.h"
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enum imx6sll_pads {
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MX6SLL_PAD_RESERVE0 = 0,
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MX6SLL_PAD_RESERVE1 = 1,
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MX6SLL_PAD_RESERVE2 = 2,
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MX6SLL_PAD_RESERVE3 = 3,
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MX6SLL_PAD_RESERVE4 = 4,
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MX6SLL_PAD_WDOG_B = 5,
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MX6SLL_PAD_REF_CLK_24M = 6,
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MX6SLL_PAD_REF_CLK_32K = 7,
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MX6SLL_PAD_PWM1 = 8,
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MX6SLL_PAD_KEY_COL0 = 9,
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MX6SLL_PAD_KEY_ROW0 = 10,
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MX6SLL_PAD_KEY_COL1 = 11,
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MX6SLL_PAD_KEY_ROW1 = 12,
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MX6SLL_PAD_KEY_COL2 = 13,
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MX6SLL_PAD_KEY_ROW2 = 14,
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MX6SLL_PAD_KEY_COL3 = 15,
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MX6SLL_PAD_KEY_ROW3 = 16,
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MX6SLL_PAD_KEY_COL4 = 17,
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MX6SLL_PAD_KEY_ROW4 = 18,
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MX6SLL_PAD_KEY_COL5 = 19,
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MX6SLL_PAD_KEY_ROW5 = 20,
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MX6SLL_PAD_KEY_COL6 = 21,
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MX6SLL_PAD_KEY_ROW6 = 22,
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MX6SLL_PAD_KEY_COL7 = 23,
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MX6SLL_PAD_KEY_ROW7 = 24,
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MX6SLL_PAD_EPDC_DATA00 = 25,
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MX6SLL_PAD_EPDC_DATA01 = 26,
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MX6SLL_PAD_EPDC_DATA02 = 27,
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MX6SLL_PAD_EPDC_DATA03 = 28,
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MX6SLL_PAD_EPDC_DATA04 = 29,
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MX6SLL_PAD_EPDC_DATA05 = 30,
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MX6SLL_PAD_EPDC_DATA06 = 31,
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MX6SLL_PAD_EPDC_DATA07 = 32,
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MX6SLL_PAD_EPDC_DATA08 = 33,
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MX6SLL_PAD_EPDC_DATA09 = 34,
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MX6SLL_PAD_EPDC_DATA10 = 35,
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MX6SLL_PAD_EPDC_DATA11 = 36,
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MX6SLL_PAD_EPDC_DATA12 = 37,
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MX6SLL_PAD_EPDC_DATA13 = 38,
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MX6SLL_PAD_EPDC_DATA14 = 39,
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MX6SLL_PAD_EPDC_DATA15 = 40,
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MX6SLL_PAD_EPDC_SDCLK = 41,
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MX6SLL_PAD_EPDC_SDLE = 42,
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MX6SLL_PAD_EPDC_SDOE = 43,
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MX6SLL_PAD_EPDC_SDSHR = 44,
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MX6SLL_PAD_EPDC_SDCE0 = 45,
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MX6SLL_PAD_EPDC_SDCE1 = 46,
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MX6SLL_PAD_EPDC_SDCE2 = 47,
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MX6SLL_PAD_EPDC_SDCE3 = 48,
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MX6SLL_PAD_EPDC_GDCLK = 49,
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MX6SLL_PAD_EPDC_GDOE = 50,
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MX6SLL_PAD_EPDC_GDRL = 51,
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MX6SLL_PAD_EPDC_GDSP = 52,
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MX6SLL_PAD_EPDC_VCOM0 = 53,
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MX6SLL_PAD_EPDC_VCOM1 = 54,
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MX6SLL_PAD_EPDC_BDR0 = 55,
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MX6SLL_PAD_EPDC_BDR1 = 56,
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MX6SLL_PAD_EPDC_PWR_CTRL0 = 57,
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MX6SLL_PAD_EPDC_PWR_CTRL1 = 58,
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MX6SLL_PAD_EPDC_PWR_CTRL2 = 59,
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MX6SLL_PAD_EPDC_PWR_CTRL3 = 60,
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MX6SLL_PAD_EPDC_PWR_COM = 61,
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MX6SLL_PAD_EPDC_PWR_INT = 62,
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MX6SLL_PAD_EPDC_PWR_STAT = 63,
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MX6SLL_PAD_EPDC_PWR_WAKE = 64,
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MX6SLL_PAD_LCD_CLK = 65,
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MX6SLL_PAD_LCD_ENABLE = 66,
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MX6SLL_PAD_LCD_HSYNC = 67,
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MX6SLL_PAD_LCD_VSYNC = 68,
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MX6SLL_PAD_LCD_RESET = 69,
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MX6SLL_PAD_LCD_DATA00 = 70,
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MX6SLL_PAD_LCD_DATA01 = 71,
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MX6SLL_PAD_LCD_DATA02 = 72,
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MX6SLL_PAD_LCD_DATA03 = 73,
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MX6SLL_PAD_LCD_DATA04 = 74,
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MX6SLL_PAD_LCD_DATA05 = 75,
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MX6SLL_PAD_LCD_DATA06 = 76,
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MX6SLL_PAD_LCD_DATA07 = 77,
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MX6SLL_PAD_LCD_DATA08 = 78,
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MX6SLL_PAD_LCD_DATA09 = 79,
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MX6SLL_PAD_LCD_DATA10 = 80,
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MX6SLL_PAD_LCD_DATA11 = 81,
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MX6SLL_PAD_LCD_DATA12 = 82,
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MX6SLL_PAD_LCD_DATA13 = 83,
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MX6SLL_PAD_LCD_DATA14 = 84,
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MX6SLL_PAD_LCD_DATA15 = 85,
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MX6SLL_PAD_LCD_DATA16 = 86,
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MX6SLL_PAD_LCD_DATA17 = 87,
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MX6SLL_PAD_LCD_DATA18 = 88,
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MX6SLL_PAD_LCD_DATA19 = 89,
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MX6SLL_PAD_LCD_DATA20 = 90,
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MX6SLL_PAD_LCD_DATA21 = 91,
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MX6SLL_PAD_LCD_DATA22 = 92,
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MX6SLL_PAD_LCD_DATA23 = 93,
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MX6SLL_PAD_AUD_RXFS = 94,
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MX6SLL_PAD_AUD_RXC = 95,
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MX6SLL_PAD_AUD_RXD = 96,
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MX6SLL_PAD_AUD_TXC = 97,
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MX6SLL_PAD_AUD_TXFS = 98,
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MX6SLL_PAD_AUD_TXD = 99,
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MX6SLL_PAD_AUD_MCLK = 100,
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MX6SLL_PAD_UART1_RXD = 101,
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MX6SLL_PAD_UART1_TXD = 102,
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MX6SLL_PAD_I2C1_SCL = 103,
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MX6SLL_PAD_I2C1_SDA = 104,
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MX6SLL_PAD_I2C2_SCL = 105,
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MX6SLL_PAD_I2C2_SDA = 106,
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MX6SLL_PAD_ECSPI1_SCLK = 107,
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MX6SLL_PAD_ECSPI1_MOSI = 108,
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MX6SLL_PAD_ECSPI1_MISO = 109,
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MX6SLL_PAD_ECSPI1_SS0 = 110,
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MX6SLL_PAD_ECSPI2_SCLK = 111,
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MX6SLL_PAD_ECSPI2_MOSI = 112,
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MX6SLL_PAD_ECSPI2_MISO = 113,
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MX6SLL_PAD_ECSPI2_SS0 = 114,
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MX6SLL_PAD_SD1_CLK = 115,
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MX6SLL_PAD_SD1_CMD = 116,
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MX6SLL_PAD_SD1_DATA0 = 117,
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MX6SLL_PAD_SD1_DATA1 = 118,
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MX6SLL_PAD_SD1_DATA2 = 119,
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MX6SLL_PAD_SD1_DATA3 = 120,
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MX6SLL_PAD_SD1_DATA4 = 121,
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MX6SLL_PAD_SD1_DATA5 = 122,
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MX6SLL_PAD_SD1_DATA6 = 123,
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MX6SLL_PAD_SD1_DATA7 = 124,
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MX6SLL_PAD_SD2_RESET = 125,
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MX6SLL_PAD_SD2_CLK = 126,
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MX6SLL_PAD_SD2_CMD = 127,
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MX6SLL_PAD_SD2_DATA0 = 128,
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MX6SLL_PAD_SD2_DATA1 = 129,
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MX6SLL_PAD_SD2_DATA2 = 130,
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MX6SLL_PAD_SD2_DATA3 = 131,
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MX6SLL_PAD_SD2_DATA4 = 132,
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MX6SLL_PAD_SD2_DATA5 = 133,
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MX6SLL_PAD_SD2_DATA6 = 134,
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MX6SLL_PAD_SD2_DATA7 = 135,
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MX6SLL_PAD_SD3_CLK = 136,
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MX6SLL_PAD_SD3_CMD = 137,
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MX6SLL_PAD_SD3_DATA0 = 138,
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MX6SLL_PAD_SD3_DATA1 = 139,
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MX6SLL_PAD_SD3_DATA2 = 140,
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MX6SLL_PAD_SD3_DATA3 = 141,
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MX6SLL_PAD_GPIO4_IO20 = 142,
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MX6SLL_PAD_GPIO4_IO21 = 143,
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MX6SLL_PAD_GPIO4_IO19 = 144,
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MX6SLL_PAD_GPIO4_IO25 = 145,
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MX6SLL_PAD_GPIO4_IO18 = 146,
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MX6SLL_PAD_GPIO4_IO24 = 147,
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MX6SLL_PAD_GPIO4_IO23 = 148,
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MX6SLL_PAD_GPIO4_IO17 = 149,
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MX6SLL_PAD_GPIO4_IO22 = 150,
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MX6SLL_PAD_GPIO4_IO16 = 151,
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MX6SLL_PAD_GPIO4_IO26 = 152,
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};
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc imx6sll_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE0),
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IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE1),
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IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE2),
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IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE3),
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IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE4),
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IMX_PINCTRL_PIN(MX6SLL_PAD_WDOG_B),
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IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_24M),
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IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_32K),
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IMX_PINCTRL_PIN(MX6SLL_PAD_PWM1),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL0),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW0),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL1),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW1),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL2),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW2),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL3),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW3),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL4),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW4),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL5),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW5),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL6),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW6),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL7),
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IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW7),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA00),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA01),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA02),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA03),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA04),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA05),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA06),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA07),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA08),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA09),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA10),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA11),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA12),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA13),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA14),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA15),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCLK),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDLE),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDOE),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDSHR),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE0),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE1),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE2),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE3),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDCLK),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDOE),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDRL),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDSP),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM0),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM1),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR0),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR1),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL0),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL1),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL2),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL3),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_COM),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_INT),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_STAT),
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IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_WAKE),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_CLK),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_ENABLE),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_HSYNC),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_VSYNC),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_RESET),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA00),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA01),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA02),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA03),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA04),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA05),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA06),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA07),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA08),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA09),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA10),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA11),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA12),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA13),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA14),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA15),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA16),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA17),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA18),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA19),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA20),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA21),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA22),
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IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA23),
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IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXFS),
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IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXC),
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IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXD),
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IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXC),
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IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXFS),
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IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXD),
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IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_MCLK),
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IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_RXD),
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IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_TXD),
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IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SCL),
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IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SDA),
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IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SCL),
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IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SDA),
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IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SCLK),
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IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MOSI),
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IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MISO),
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IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SS0),
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IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SCLK),
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IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MOSI),
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IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MISO),
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IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SS0),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CLK),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CMD),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA0),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA1),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA2),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA3),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA4),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA5),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA6),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA7),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_RESET),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CLK),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CMD),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA0),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA1),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA2),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA3),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA4),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA5),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA6),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA7),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CLK),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CMD),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA0),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA1),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA2),
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IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA3),
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IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO20),
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IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO21),
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IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO19),
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|
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO25),
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|
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO18),
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|
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO24),
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|
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO23),
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|
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO17),
|
|
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO22),
|
|
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO16),
|
|
IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO26),
|
|
};
|
|
|
|
static const struct imx_pinctrl_soc_info imx6sll_pinctrl_info = {
|
|
.pins = imx6sll_pinctrl_pads,
|
|
.npins = ARRAY_SIZE(imx6sll_pinctrl_pads),
|
|
.gpr_compatible = "fsl,imx6sll-iomuxc-gpr",
|
|
};
|
|
|
|
static const struct of_device_id imx6sll_pinctrl_of_match[] = {
|
|
{ .compatible = "fsl,imx6sll-iomuxc", .data = &imx6sll_pinctrl_info, },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static int imx6sll_pinctrl_probe(struct platform_device *pdev)
|
|
{
|
|
return imx_pinctrl_probe(pdev, &imx6sll_pinctrl_info);
|
|
}
|
|
|
|
static struct platform_driver imx6sll_pinctrl_driver = {
|
|
.driver = {
|
|
.name = "imx6sll-pinctrl",
|
|
.of_match_table = of_match_ptr(imx6sll_pinctrl_of_match),
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = imx6sll_pinctrl_probe,
|
|
};
|
|
|
|
static int __init imx6sll_pinctrl_init(void)
|
|
{
|
|
return platform_driver_register(&imx6sll_pinctrl_driver);
|
|
}
|
|
arch_initcall(imx6sll_pinctrl_init);
|