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![Qianggui Song](/assets/img/avatar_default.png)
Meson A1 SoC share the same register layout of pinmux with previous Meson-G12A, however there is difference for gpio and pin config register in A1. The main difference is that registers before A1 are grouped by function while those of A1 are by bank. The new register layout is as below: /* first bank */ /* addr */ - P_PADCTRL_GPIOP_I base + 0x00 << 2 - P_PADCTRL_GPIOP_O base + 0x01 << 2 - P_PADCTRL_GPIOP_OEN base + 0x02 << 2 - P_PADCTRL_GPIOP_PULL_EN base + 0x03 << 2 - P_PADCTRL_GPIOP_PULL_UP base + 0x04 << 2 - P_PADCTRL_GPIOP_DS base + 0x05 << 2 /* second bank */ - P_PADCTRL_GPIOB_I base + 0x10 << 2 - P_PADCTRL_GPIOB_O base + 0x11 << 2 - P_PADCTRL_GPIOB_OEN base + 0x12 << 2 - P_PADCTRL_GPIOB_PULL_EN base + 0x13 << 2 - P_PADCTRL_GPIOB_PULL_UP base + 0x14 << 2 - P_PADCTRL_GPIOB_DS base + 0x15 << 2 Each bank contains at least 6 registers to be configured, if one bank has more than 16 gpios, an extra P_PADCTRL_GPIO[X]_DS_EXT is included. Between two adjacent P_PADCTRL_GPIO[X]_I, there is an offset 0x10, that is to say, for third bank, the offsets will be 0x20,0x21,0x22,0x23,0x24 ,0x25 according to above register layout. For previous chips, registers are grouped according to their functions while registers of A1 are according to bank.Also note that there is no AO bank any more in A1. Current Meson pinctrl driver can cover such change by using base address of GPIO as that of drive-strength. While simply giving reg_ds = reg_pullen make wrong value to reg_ds for Socs that do not support drive-strength like AXG.To make things simple, add an extra dt parser function for a1 and remain the old dt parser function for only reg parsing. Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Link: https://lore.kernel.org/r/1573819429-6937-3-git-send-email-qianggui.song@amlogic.com Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
180 lines
4.5 KiB
C
180 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Pin controller and GPIO driver for Amlogic Meson SoCs
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*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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*/
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#include <linux/gpio/driver.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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struct meson_pinctrl;
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/**
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* struct meson_pmx_group - a pinmux group
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*
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* @name: group name
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* @pins: pins in the group
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* @num_pins: number of pins in the group
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* @is_gpio: whether the group is a single GPIO group
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* @reg: register offset for the group in the domain mux registers
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* @bit bit index enabling the group
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* @domain: index of the domain this group belongs to
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*/
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struct meson_pmx_group {
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const char *name;
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const unsigned int *pins;
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unsigned int num_pins;
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const void *data;
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};
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/**
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* struct meson_pmx_func - a pinmux function
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*
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* @name: function name
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* @groups: groups in the function
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* @num_groups: number of groups in the function
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*/
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struct meson_pmx_func {
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const char *name;
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const char * const *groups;
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unsigned int num_groups;
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};
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/**
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* struct meson_reg_desc - a register descriptor
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*
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* @reg: register offset in the regmap
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* @bit: bit index in register
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*
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* The structure describes the information needed to control pull,
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* pull-enable, direction, etc. for a single pin
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*/
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struct meson_reg_desc {
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unsigned int reg;
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unsigned int bit;
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};
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/**
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* enum meson_reg_type - type of registers encoded in @meson_reg_desc
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*/
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enum meson_reg_type {
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REG_PULLEN,
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REG_PULL,
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REG_DIR,
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REG_OUT,
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REG_IN,
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REG_DS,
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NUM_REG,
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};
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/**
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* enum meson_pinconf_drv - value of drive-strength supported
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*/
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enum meson_pinconf_drv {
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MESON_PINCONF_DRV_500UA,
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MESON_PINCONF_DRV_2500UA,
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MESON_PINCONF_DRV_3000UA,
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MESON_PINCONF_DRV_4000UA,
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};
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/**
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* struct meson bank
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*
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* @name: bank name
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* @first: first pin of the bank
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* @last: last pin of the bank
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* @irq: hwirq base number of the bank
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* @regs: array of register descriptors
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*
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* A bank represents a set of pins controlled by a contiguous set of
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* bits in the domain registers. The structure specifies which bits in
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* the regmap control the different functionalities. Each member of
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* the @regs array refers to the first pin of the bank.
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*/
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struct meson_bank {
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const char *name;
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unsigned int first;
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unsigned int last;
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int irq_first;
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int irq_last;
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struct meson_reg_desc regs[NUM_REG];
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};
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struct meson_pinctrl_data {
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const char *name;
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const struct pinctrl_pin_desc *pins;
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struct meson_pmx_group *groups;
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struct meson_pmx_func *funcs;
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unsigned int num_pins;
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unsigned int num_groups;
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unsigned int num_funcs;
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struct meson_bank *banks;
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unsigned int num_banks;
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const struct pinmux_ops *pmx_ops;
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void *pmx_data;
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int (*parse_dt)(struct meson_pinctrl *pc);
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};
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struct meson_pinctrl {
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struct device *dev;
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struct pinctrl_dev *pcdev;
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struct pinctrl_desc desc;
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struct meson_pinctrl_data *data;
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struct regmap *reg_mux;
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struct regmap *reg_pullen;
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struct regmap *reg_pull;
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struct regmap *reg_gpio;
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struct regmap *reg_ds;
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struct gpio_chip chip;
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struct device_node *of_node;
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};
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#define FUNCTION(fn) \
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{ \
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.name = #fn, \
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.groups = fn ## _groups, \
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.num_groups = ARRAY_SIZE(fn ## _groups), \
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}
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#define BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, \
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dsr, dsb) \
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{ \
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.name = n, \
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.first = f, \
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.last = l, \
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.irq_first = fi, \
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.irq_last = li, \
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.regs = { \
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[REG_PULLEN] = { per, peb }, \
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[REG_PULL] = { pr, pb }, \
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[REG_DIR] = { dr, db }, \
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[REG_OUT] = { or, ob }, \
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[REG_IN] = { ir, ib }, \
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[REG_DS] = { dsr, dsb }, \
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}, \
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}
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#define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
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BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0)
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#define MESON_PIN(x) PINCTRL_PIN(x, #x)
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/* Common pmx functions */
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int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev);
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const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
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unsigned selector);
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int meson_pmx_get_groups(struct pinctrl_dev *pcdev,
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unsigned selector,
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const char * const **groups,
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unsigned * const num_groups);
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/* Common probe function */
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int meson_pinctrl_probe(struct platform_device *pdev);
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/* Common ao groups extra dt parse function for SoCs before g12a */
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int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc);
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/* Common extra dt parse function for SoCs like A1 */
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int meson_a1_parse_dt_extra(struct meson_pinctrl *pc);
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