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In consideration of UFS host driver uses parameters of struct ufs_dev_desc, move its parameters to struct ufs_dev_info, delete struct ufs_dev_desc. Link: https://lore.kernel.org/r/20200120130820.1737-3-huobean@gmail.com Reviewed-by: Bart Van Assche <bvanassche@acm.org> Reviewed-by: Asutosh Das <asutoshd@codeaurora.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Stanley Chu <stanley.chu@mediatek.com> Signed-off-by: Bean Huo <beanhuo@micron.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
569 lines
13 KiB
C
569 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 MediaTek Inc.
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* Authors:
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* Stanley Chu <stanley.chu@mediatek.com>
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* Peter Wang <peter.wang@mediatek.com>
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*/
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#include <linux/arm-smccc.h>
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#include <linux/bitfield.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/soc/mediatek/mtk_sip_svc.h>
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#include "ufshcd.h"
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#include "ufshcd-pltfrm.h"
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#include "ufs_quirks.h"
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#include "unipro.h"
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#include "ufs-mediatek.h"
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#define ufs_mtk_smc(cmd, val, res) \
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arm_smccc_smc(MTK_SIP_UFS_CONTROL, \
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cmd, val, 0, 0, 0, 0, 0, &(res))
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#define ufs_mtk_ref_clk_notify(on, res) \
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ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, on, res)
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#define ufs_mtk_device_reset_ctrl(high, res) \
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ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, high, res)
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static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
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{
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u32 tmp;
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if (enable) {
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ufshcd_dme_get(hba,
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UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
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tmp = tmp |
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(1 << RX_SYMBOL_CLK_GATE_EN) |
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(1 << SYS_CLK_GATE_EN) |
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(1 << TX_CLK_GATE_EN);
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ufshcd_dme_set(hba,
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UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
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ufshcd_dme_get(hba,
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UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
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tmp = tmp & ~(1 << TX_SYMBOL_CLK_REQ_FORCE);
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ufshcd_dme_set(hba,
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UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
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} else {
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ufshcd_dme_get(hba,
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UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
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tmp = tmp & ~((1 << RX_SYMBOL_CLK_GATE_EN) |
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(1 << SYS_CLK_GATE_EN) |
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(1 << TX_CLK_GATE_EN));
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ufshcd_dme_set(hba,
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UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
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ufshcd_dme_get(hba,
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UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
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tmp = tmp | (1 << TX_SYMBOL_CLK_REQ_FORCE);
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ufshcd_dme_set(hba,
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UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
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}
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}
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static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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struct device *dev = hba->dev;
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struct device_node *np = dev->of_node;
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int err = 0;
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host->mphy = devm_of_phy_get_by_index(dev, np, 0);
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if (host->mphy == ERR_PTR(-EPROBE_DEFER)) {
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/*
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* UFS driver might be probed before the phy driver does.
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* In that case we would like to return EPROBE_DEFER code.
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*/
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err = -EPROBE_DEFER;
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dev_info(dev,
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"%s: required phy hasn't probed yet. err = %d\n",
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__func__, err);
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} else if (IS_ERR(host->mphy)) {
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err = PTR_ERR(host->mphy);
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dev_info(dev, "%s: PHY get failed %d\n", __func__, err);
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}
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if (err)
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host->mphy = NULL;
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return err;
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}
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static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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struct arm_smccc_res res;
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unsigned long timeout;
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u32 value;
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if (host->ref_clk_enabled == on)
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return 0;
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if (on) {
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ufs_mtk_ref_clk_notify(on, res);
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ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL);
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} else {
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ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
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}
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/* Wait for ack */
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timeout = jiffies + msecs_to_jiffies(REFCLK_REQ_TIMEOUT_MS);
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do {
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value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
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/* Wait until ack bit equals to req bit */
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if (((value & REFCLK_ACK) >> 1) == (value & REFCLK_REQUEST))
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goto out;
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usleep_range(100, 200);
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} while (time_before(jiffies, timeout));
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dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
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ufs_mtk_ref_clk_notify(host->ref_clk_enabled, res);
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return -ETIMEDOUT;
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out:
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host->ref_clk_enabled = on;
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if (!on)
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ufs_mtk_ref_clk_notify(on, res);
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return 0;
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}
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/**
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* ufs_mtk_setup_clocks - enables/disable clocks
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* @hba: host controller instance
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* @on: If true, enable clocks else disable them.
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* @status: PRE_CHANGE or POST_CHANGE notify
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*
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* Returns 0 on success, non-zero on failure.
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*/
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static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
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enum ufs_notify_change_status status)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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int ret = -EINVAL;
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/*
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* In case ufs_mtk_init() is not yet done, simply ignore.
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* This ufs_mtk_setup_clocks() shall be called from
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* ufs_mtk_init() after init is done.
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*/
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if (!host)
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return 0;
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switch (status) {
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case PRE_CHANGE:
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if (!on) {
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ufs_mtk_setup_ref_clk(hba, on);
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ret = phy_power_off(host->mphy);
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}
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break;
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case POST_CHANGE:
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if (on) {
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ret = phy_power_on(host->mphy);
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ufs_mtk_setup_ref_clk(hba, on);
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}
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break;
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}
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return ret;
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}
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/**
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* ufs_mtk_init - find other essential mmio bases
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* @hba: host controller instance
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*
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* Binds PHY with controller and powers up PHY enabling clocks
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* and regulators.
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*
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* Returns -EPROBE_DEFER if binding fails, returns negative error
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* on phy power up failure and returns zero on success.
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*/
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static int ufs_mtk_init(struct ufs_hba *hba)
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{
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struct ufs_mtk_host *host;
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struct device *dev = hba->dev;
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int err = 0;
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host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
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if (!host) {
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err = -ENOMEM;
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dev_info(dev, "%s: no memory for mtk ufs host\n", __func__);
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goto out;
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}
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host->hba = hba;
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ufshcd_set_variant(hba, host);
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err = ufs_mtk_bind_mphy(hba);
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if (err)
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goto out_variant_clear;
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/* Enable runtime autosuspend */
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hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
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/* Enable clock-gating */
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hba->caps |= UFSHCD_CAP_CLK_GATING;
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/*
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* ufshcd_vops_init() is invoked after
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* ufshcd_setup_clock(true) in ufshcd_hba_init() thus
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* phy clock setup is skipped.
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*
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* Enable phy clocks specifically here.
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*/
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ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
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goto out;
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out_variant_clear:
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ufshcd_set_variant(hba, NULL);
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out:
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return err;
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}
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static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
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struct ufs_pa_layer_attr *dev_max_params,
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struct ufs_pa_layer_attr *dev_req_params)
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{
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struct ufs_dev_params host_cap;
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int ret;
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host_cap.tx_lanes = UFS_MTK_LIMIT_NUM_LANES_TX;
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host_cap.rx_lanes = UFS_MTK_LIMIT_NUM_LANES_RX;
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host_cap.hs_rx_gear = UFS_MTK_LIMIT_HSGEAR_RX;
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host_cap.hs_tx_gear = UFS_MTK_LIMIT_HSGEAR_TX;
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host_cap.pwm_rx_gear = UFS_MTK_LIMIT_PWMGEAR_RX;
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host_cap.pwm_tx_gear = UFS_MTK_LIMIT_PWMGEAR_TX;
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host_cap.rx_pwr_pwm = UFS_MTK_LIMIT_RX_PWR_PWM;
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host_cap.tx_pwr_pwm = UFS_MTK_LIMIT_TX_PWR_PWM;
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host_cap.rx_pwr_hs = UFS_MTK_LIMIT_RX_PWR_HS;
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host_cap.tx_pwr_hs = UFS_MTK_LIMIT_TX_PWR_HS;
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host_cap.hs_rate = UFS_MTK_LIMIT_HS_RATE;
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host_cap.desired_working_mode =
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UFS_MTK_LIMIT_DESIRED_MODE;
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ret = ufshcd_get_pwr_dev_param(&host_cap,
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dev_max_params,
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dev_req_params);
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if (ret) {
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pr_info("%s: failed to determine capabilities\n",
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__func__);
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}
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return ret;
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}
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static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status stage,
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struct ufs_pa_layer_attr *dev_max_params,
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struct ufs_pa_layer_attr *dev_req_params)
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{
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int ret = 0;
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switch (stage) {
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case PRE_CHANGE:
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ret = ufs_mtk_pre_pwr_change(hba, dev_max_params,
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dev_req_params);
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break;
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case POST_CHANGE:
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int ufs_mtk_pre_link(struct ufs_hba *hba)
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{
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int ret;
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u32 tmp;
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/* disable deep stall */
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ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
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if (ret)
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return ret;
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tmp &= ~(1 << 6);
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ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
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return ret;
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}
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static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
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{
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unsigned long flags;
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u32 ah_ms;
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if (ufshcd_is_clkgating_allowed(hba)) {
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if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit)
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ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
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hba->ahit);
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else
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ah_ms = 10;
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spin_lock_irqsave(hba->host->host_lock, flags);
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hba->clk_gating.delay_ms = ah_ms + 5;
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spin_unlock_irqrestore(hba->host->host_lock, flags);
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}
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}
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static int ufs_mtk_post_link(struct ufs_hba *hba)
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{
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/* disable device LCC */
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ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
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/* enable unipro clock gating feature */
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ufs_mtk_cfg_unipro_cg(hba, true);
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/* configure auto-hibern8 timer to 10ms */
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if (ufshcd_is_auto_hibern8_supported(hba)) {
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ufshcd_auto_hibern8_update(hba,
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FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 10) |
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FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3));
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}
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ufs_mtk_setup_clk_gating(hba);
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return 0;
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}
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static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status stage)
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{
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int ret = 0;
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switch (stage) {
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case PRE_CHANGE:
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ret = ufs_mtk_pre_link(hba);
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break;
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case POST_CHANGE:
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ret = ufs_mtk_post_link(hba);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static void ufs_mtk_device_reset(struct ufs_hba *hba)
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{
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struct arm_smccc_res res;
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ufs_mtk_device_reset_ctrl(0, res);
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/*
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* The reset signal is active low. UFS devices shall detect
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* more than or equal to 1us of positive or negative RST_n
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* pulse width.
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*
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* To be on safe side, keep the reset low for at least 10us.
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*/
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usleep_range(10, 15);
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ufs_mtk_device_reset_ctrl(1, res);
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/* Some devices may need time to respond to rst_n */
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usleep_range(10000, 15000);
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dev_info(hba->dev, "device reset done\n");
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}
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static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
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{
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int err;
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err = ufshcd_hba_enable(hba);
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if (err)
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return err;
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err = ufshcd_dme_set(hba,
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UIC_ARG_MIB_SEL(VS_UNIPROPOWERDOWNCONTROL, 0),
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0);
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if (err)
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return err;
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err = ufshcd_uic_hibern8_exit(hba);
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if (!err)
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ufshcd_set_link_active(hba);
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else
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return err;
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err = ufshcd_make_hba_operational(hba);
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if (err)
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return err;
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return 0;
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}
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static int ufs_mtk_link_set_lpm(struct ufs_hba *hba)
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{
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int err;
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err = ufshcd_dme_set(hba,
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UIC_ARG_MIB_SEL(VS_UNIPROPOWERDOWNCONTROL, 0),
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1);
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if (err) {
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/* Resume UniPro state for following error recovery */
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ufshcd_dme_set(hba,
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UIC_ARG_MIB_SEL(VS_UNIPROPOWERDOWNCONTROL, 0),
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0);
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return err;
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}
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return 0;
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}
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static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
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{
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int err;
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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if (ufshcd_is_link_hibern8(hba)) {
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err = ufs_mtk_link_set_lpm(hba);
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if (err)
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return -EAGAIN;
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phy_power_off(host->mphy);
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ufs_mtk_setup_ref_clk(hba, false);
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}
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return 0;
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}
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static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
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{
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struct ufs_mtk_host *host = ufshcd_get_variant(hba);
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int err;
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if (ufshcd_is_link_hibern8(hba)) {
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ufs_mtk_setup_ref_clk(hba, true);
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phy_power_on(host->mphy);
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err = ufs_mtk_link_set_hpm(hba);
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if (err)
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return err;
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}
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return 0;
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}
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static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba)
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{
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ufshcd_dump_regs(hba, REG_UFS_REFCLK_CTRL, 0x4, "Ref-Clk Ctrl ");
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ufshcd_dump_regs(hba, REG_UFS_EXTREG, 0x4, "Ext Reg ");
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ufshcd_dump_regs(hba, REG_UFS_MPHYCTRL,
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REG_UFS_REJECT_MON - REG_UFS_MPHYCTRL + 4,
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"MPHY Ctrl ");
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/* Direct debugging information to REG_MTK_PROBE */
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ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
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ufshcd_dump_regs(hba, REG_UFS_PROBE, 0x4, "Debug Probe ");
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}
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static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
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{
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struct ufs_dev_info *dev_info = &hba->dev_info;
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|
|
if (dev_info->wmanufacturerid == UFS_VENDOR_SAMSUNG)
|
|
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* struct ufs_hba_mtk_vops - UFS MTK specific variant operations
|
|
*
|
|
* The variant operations configure the necessary controller and PHY
|
|
* handshake during initialization.
|
|
*/
|
|
static struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
|
|
.name = "mediatek.ufshci",
|
|
.init = ufs_mtk_init,
|
|
.setup_clocks = ufs_mtk_setup_clocks,
|
|
.link_startup_notify = ufs_mtk_link_startup_notify,
|
|
.pwr_change_notify = ufs_mtk_pwr_change_notify,
|
|
.apply_dev_quirks = ufs_mtk_apply_dev_quirks,
|
|
.suspend = ufs_mtk_suspend,
|
|
.resume = ufs_mtk_resume,
|
|
.dbg_register_dump = ufs_mtk_dbg_register_dump,
|
|
.device_reset = ufs_mtk_device_reset,
|
|
};
|
|
|
|
/**
|
|
* ufs_mtk_probe - probe routine of the driver
|
|
* @pdev: pointer to Platform device handle
|
|
*
|
|
* Return zero for success and non-zero for failure
|
|
*/
|
|
static int ufs_mtk_probe(struct platform_device *pdev)
|
|
{
|
|
int err;
|
|
struct device *dev = &pdev->dev;
|
|
|
|
/* perform generic probe */
|
|
err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
|
|
if (err)
|
|
dev_info(dev, "probe failed %d\n", err);
|
|
|
|
return err;
|
|
}
|
|
|
|
/**
|
|
* ufs_mtk_remove - set driver_data of the device to NULL
|
|
* @pdev: pointer to platform device handle
|
|
*
|
|
* Always return 0
|
|
*/
|
|
static int ufs_mtk_remove(struct platform_device *pdev)
|
|
{
|
|
struct ufs_hba *hba = platform_get_drvdata(pdev);
|
|
|
|
pm_runtime_get_sync(&(pdev)->dev);
|
|
ufshcd_remove(hba);
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id ufs_mtk_of_match[] = {
|
|
{ .compatible = "mediatek,mt8183-ufshci"},
|
|
{},
|
|
};
|
|
|
|
static const struct dev_pm_ops ufs_mtk_pm_ops = {
|
|
.suspend = ufshcd_pltfrm_suspend,
|
|
.resume = ufshcd_pltfrm_resume,
|
|
.runtime_suspend = ufshcd_pltfrm_runtime_suspend,
|
|
.runtime_resume = ufshcd_pltfrm_runtime_resume,
|
|
.runtime_idle = ufshcd_pltfrm_runtime_idle,
|
|
};
|
|
|
|
static struct platform_driver ufs_mtk_pltform = {
|
|
.probe = ufs_mtk_probe,
|
|
.remove = ufs_mtk_remove,
|
|
.shutdown = ufshcd_pltfrm_shutdown,
|
|
.driver = {
|
|
.name = "ufshcd-mtk",
|
|
.pm = &ufs_mtk_pm_ops,
|
|
.of_match_table = ufs_mtk_of_match,
|
|
},
|
|
};
|
|
|
|
MODULE_AUTHOR("Stanley Chu <stanley.chu@mediatek.com>");
|
|
MODULE_AUTHOR("Peter Wang <peter.wang@mediatek.com>");
|
|
MODULE_DESCRIPTION("MediaTek UFS Host Driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
module_platform_driver(ufs_mtk_pltform);
|