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efeeaefe9b
Introduces a driver for the LogiCVC display controller, a programmable logic controller optimized for use in Xilinx Zynq-7000 SoCs and other Xilinx FPGAs. The controller is mostly configured at logic synthesis time so only a subset of configuration is left for the driver to handle. The following features are implemented and tested: - LVDS 4-bit interface; - RGB565 pixel formats; - Multiple layers and hardware composition; - Layer-wide alpha mode; The following features are implemented but untested: - Other RGB pixel formats; - Layer framebuffer configuration for version 4; - Lowest-layer used as background color; - Per-pixel alpha mode. The following features are not implemented: - YUV pixel formats; - DVI, LVDS 3-bit, ITU656 and camera link interfaces; - External parallel input for layer; - Color-keying; - LUT-based alpha modes. Additional implementation-specific notes: - Panels are only enabled after the first page flip to avoid flashing a white screen. - Depth used in context of the LogiCVC driver only counts color components to match the definition of the synthesis parameters. Support is implemented for both version 3 and 4 of the controller. With version 3, framebuffers are stored in a dedicated contiguous memory area, with a base address hardcoded for each layer. This requires using a dedicated CMA pool registered at the base address and tweaking a few offset-related registers to try to use any buffer allocated from the pool. This is done on a best-effort basis to have the hardware cope with the DRM framebuffer allocation model and there is no guarantee that each buffer allocated by GEM CMA can be used for any layer. In particular, buffers allocated below the base address for a layer are guaranteed not to be configurable for that layer. See the implementation of logicvc_layer_buffer_find_setup for specifics. Version 4 allows configuring each buffer address directly, which guarantees that any buffer can be configured. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220520141555.1429041-2-paul.kocialkowski@bootlin.com
64 lines
1.5 KiB
C
64 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019-2022 Bootlin
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* Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
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*/
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#ifndef _LOGICVC_LAYER_H_
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#define _LOGICVC_LAYER_H_
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#include <linux/of.h>
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#include <linux/types.h>
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#include <drm/drm_plane.h>
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#define LOGICVC_LAYER_COLORSPACE_RGB 0
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#define LOGICVC_LAYER_COLORSPACE_YUV 1
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#define LOGICVC_LAYER_ALPHA_LAYER 0
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#define LOGICVC_LAYER_ALPHA_PIXEL 1
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struct logicvc_layer_buffer_setup {
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u8 buffer_sel;
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u16 voffset;
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u16 hoffset;
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};
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struct logicvc_layer_config {
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u32 colorspace;
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u32 depth;
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u32 alpha_mode;
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u32 base_offset;
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u32 buffer_offset;
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bool primary;
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};
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struct logicvc_layer_formats {
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u32 colorspace;
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u32 depth;
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bool alpha;
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uint32_t *formats;
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};
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struct logicvc_layer {
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struct logicvc_layer_config config;
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struct logicvc_layer_formats *formats;
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struct device_node *of_node;
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struct drm_plane drm_plane;
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struct list_head list;
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u32 index;
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};
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int logicvc_layer_buffer_find_setup(struct logicvc_drm *logicvc,
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struct logicvc_layer *layer,
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struct drm_plane_state *state,
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struct logicvc_layer_buffer_setup *setup);
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struct logicvc_layer *logicvc_layer_get_from_index(struct logicvc_drm *logicvc,
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u32 index);
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struct logicvc_layer *logicvc_layer_get_from_type(struct logicvc_drm *logicvc,
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enum drm_plane_type type);
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struct logicvc_layer *logicvc_layer_get_primary(struct logicvc_drm *logicvc);
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void logicvc_layers_attach_crtc(struct logicvc_drm *logicvc);
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int logicvc_layers_init(struct logicvc_drm *logicvc);
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#endif
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