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Introduces a driver for the LogiCVC display controller, a programmable logic controller optimized for use in Xilinx Zynq-7000 SoCs and other Xilinx FPGAs. The controller is mostly configured at logic synthesis time so only a subset of configuration is left for the driver to handle. The following features are implemented and tested: - LVDS 4-bit interface; - RGB565 pixel formats; - Multiple layers and hardware composition; - Layer-wide alpha mode; The following features are implemented but untested: - Other RGB pixel formats; - Layer framebuffer configuration for version 4; - Lowest-layer used as background color; - Per-pixel alpha mode. The following features are not implemented: - YUV pixel formats; - DVI, LVDS 3-bit, ITU656 and camera link interfaces; - External parallel input for layer; - Color-keying; - LUT-based alpha modes. Additional implementation-specific notes: - Panels are only enabled after the first page flip to avoid flashing a white screen. - Depth used in context of the LogiCVC driver only counts color components to match the definition of the synthesis parameters. Support is implemented for both version 3 and 4 of the controller. With version 3, framebuffers are stored in a dedicated contiguous memory area, with a base address hardcoded for each layer. This requires using a dedicated CMA pool registered at the base address and tweaking a few offset-related registers to try to use any buffer allocated from the pool. This is done on a best-effort basis to have the hardware cope with the DRM framebuffer allocation model and there is no guarantee that each buffer allocated by GEM CMA can be used for any layer. In particular, buffers allocated below the base address for a layer are guaranteed not to be configurable for that layer. See the implementation of logicvc_layer_buffer_find_setup for specifics. Version 4 allows configuring each buffer address directly, which guarantees that any buffer can be configured. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220520141555.1429041-2-paul.kocialkowski@bootlin.com
46 lines
1.2 KiB
C
46 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019-2022 Bootlin
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* Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
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*/
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#ifndef _LOGICVC_OF_H_
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#define _LOGICVC_OF_H_
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enum logicvc_of_property_index {
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LOGICVC_OF_PROPERTY_DISPLAY_INTERFACE = 0,
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LOGICVC_OF_PROPERTY_DISPLAY_COLORSPACE,
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LOGICVC_OF_PROPERTY_DISPLAY_DEPTH,
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LOGICVC_OF_PROPERTY_ROW_STRIDE,
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LOGICVC_OF_PROPERTY_DITHERING,
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LOGICVC_OF_PROPERTY_BACKGROUND_LAYER,
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LOGICVC_OF_PROPERTY_LAYERS_CONFIGURABLE,
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LOGICVC_OF_PROPERTY_LAYERS_COUNT,
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LOGICVC_OF_PROPERTY_LAYER_DEPTH,
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LOGICVC_OF_PROPERTY_LAYER_COLORSPACE,
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LOGICVC_OF_PROPERTY_LAYER_ALPHA_MODE,
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LOGICVC_OF_PROPERTY_LAYER_BASE_OFFSET,
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LOGICVC_OF_PROPERTY_LAYER_BUFFER_OFFSET,
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LOGICVC_OF_PROPERTY_LAYER_PRIMARY,
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LOGICVC_OF_PROPERTY_MAXIMUM,
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};
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struct logicvc_of_property_sv {
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const char *string;
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u32 value;
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};
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struct logicvc_of_property {
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char *name;
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bool optional;
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struct logicvc_of_property_sv *sv;
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u32 range[2];
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};
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int logicvc_of_property_parse_u32(struct device_node *of_node,
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unsigned int index, u32 *target);
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void logicvc_of_property_parse_bool(struct device_node *of_node,
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unsigned int index, bool *target);
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bool logicvc_of_node_is_layer(struct device_node *of_node);
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#endif
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