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64db601a95
This patch adds encoding support for the YUV420 output from the Amlogic Meson SoCs Video Processing Unit to the HDMI Controller. The YUV420 is obtained by generating a YUV444 pixel stream like the classic HDMI display modes, but then the Video Encoder output can be configured to down-sample the YUV444 pixel stream to a YUV420 stream. In addition if pixel stream down-sampling, the Y Cb Cr components must also be mapped differently to align with the HDMI2.0 specifications. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jernej Škrabec <jernej.skrabec@siol.net> Link: https://patchwork.freedesktop.org/patch/msgid/20200304104052.17196-10-narmstrong@baylibre.com
73 lines
2.1 KiB
C
73 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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/*
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* Video Encoders
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* - ENCI : Interlace Video Encoder
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* - ENCI_DVI : Interlace Video Encoder for DVI/HDMI
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* - ENCP : Progressive Video Encoder
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*/
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#ifndef __MESON_VENC_H
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#define __MESON_VENC_H
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struct drm_display_mode;
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enum {
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MESON_VENC_MODE_NONE = 0,
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MESON_VENC_MODE_CVBS_PAL,
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MESON_VENC_MODE_CVBS_NTSC,
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MESON_VENC_MODE_HDMI,
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};
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struct meson_cvbs_enci_mode {
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unsigned int mode_tag;
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unsigned int hso_begin; /* HSO begin position */
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unsigned int hso_end; /* HSO end position */
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unsigned int vso_even; /* VSO even line */
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unsigned int vso_odd; /* VSO odd line */
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unsigned int macv_max_amp; /* Macrovision max amplitude */
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unsigned int video_prog_mode;
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unsigned int video_mode;
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unsigned int sch_adjust;
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unsigned int yc_delay;
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unsigned int pixel_start;
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unsigned int pixel_end;
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unsigned int top_field_line_start;
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unsigned int top_field_line_end;
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unsigned int bottom_field_line_start;
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unsigned int bottom_field_line_end;
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unsigned int video_saturation;
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unsigned int video_contrast;
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unsigned int video_brightness;
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unsigned int video_hue;
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unsigned int analog_sync_adj;
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};
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/* HDMI Clock parameters */
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enum drm_mode_status
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meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode);
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bool meson_venc_hdmi_supported_vic(int vic);
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bool meson_venc_hdmi_venc_repeat(int vic);
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/* CVBS Timings and Parameters */
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extern struct meson_cvbs_enci_mode meson_cvbs_enci_pal;
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extern struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc;
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void meson_venci_cvbs_mode_set(struct meson_drm *priv,
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struct meson_cvbs_enci_mode *mode);
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void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
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unsigned int ycrcb_map,
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bool yuv420_mode,
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const struct drm_display_mode *mode);
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unsigned int meson_venci_get_field(struct meson_drm *priv);
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void meson_venc_enable_vsync(struct meson_drm *priv);
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void meson_venc_disable_vsync(struct meson_drm *priv);
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void meson_venc_init(struct meson_drm *priv);
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#endif /* __MESON_VENC_H */
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