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linux-stable/drivers/gpu
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Zhenyu Wang f8f235e5bb agp/intel: Fix cache control for Sandybridge 
Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC, so we need to extend the mask
function to respect the new bits.

And set cache control to always LLC only by default on Gen6.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-07 11:16:43 +01:00
..
drm agp/intel: Fix cache control for Sandybridge 2010-09-07 11:16:43 +01:00
vga vgaarb: use MIT license 2010-06-03 13:13:34 +10:00
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