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efecba3c9f
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-3-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
16 lines
420 B
C
16 lines
420 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_PCS_V6_H_
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#define QCOM_PHY_QMP_PCS_V6_H_
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/* Only for QMP V6 PHY - USB/PCIe PCS registers */
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#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1 0xdc
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#define QPHY_V6_PCS_RX_SIGDET_LVL 0x188
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#define QPHY_V6_PCS_RATE_SLEW_CNTRL1 0x198
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#define QPHY_V6_PCS_EQ_CONFIG2 0x1e0
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#define QPHY_V6_PCS_PCS_TX_RX_CONFIG 0x1d0
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#endif
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