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![Paul Cercueil](/assets/img/avatar_default.png)
The function dma_controller_irq() locks up the exact same spinlock we
locked before calling it, which obviously resulted in a deadlock when
CONFIG_SMP was enabled. This flew under the radar as none of the boards
supported by this driver needs SMP.
Fixes: 57aadb46bd
("usb: musb: jz4740: Add support for DMA")
Cc: stable@vger.kernel.org
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Bin Liu <b-liu@ti.com>
Link: https://lore.kernel.org/r/20200525025049.3400-6-b-liu@ti.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
297 lines
7.7 KiB
C
297 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Ingenic JZ4740 "glue layer"
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*
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* Copyright (C) 2013, Apelete Seketeli <apelete@seketeli.net>
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*/
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/usb/role.h>
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#include <linux/usb/usb_phy_generic.h>
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#include "musb_core.h"
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struct jz4740_glue {
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struct platform_device *pdev;
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struct musb *musb;
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struct clk *clk;
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struct usb_role_switch *role_sw;
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};
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static irqreturn_t jz4740_musb_interrupt(int irq, void *__hci)
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{
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unsigned long flags;
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irqreturn_t retval = IRQ_NONE, retval_dma = IRQ_NONE;
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struct musb *musb = __hci;
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if (IS_ENABLED(CONFIG_USB_INVENTRA_DMA) && musb->dma_controller)
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retval_dma = dma_controller_irq(irq, musb->dma_controller);
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spin_lock_irqsave(&musb->lock, flags);
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musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
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musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
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musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
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/*
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* The controller is gadget only, the state of the host mode IRQ bits is
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* undefined. Mask them to make sure that the musb driver core will
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* never see them set
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*/
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musb->int_usb &= MUSB_INTR_SUSPEND | MUSB_INTR_RESUME |
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MUSB_INTR_RESET | MUSB_INTR_SOF;
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if (musb->int_usb || musb->int_tx || musb->int_rx)
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retval = musb_interrupt(musb);
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spin_unlock_irqrestore(&musb->lock, flags);
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if (retval == IRQ_HANDLED || retval_dma == IRQ_HANDLED)
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return IRQ_HANDLED;
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return IRQ_NONE;
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}
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static struct musb_fifo_cfg jz4740_musb_fifo_cfg[] = {
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{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
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{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
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{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 64, },
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};
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static const struct musb_hdrc_config jz4740_musb_config = {
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/* Silicon does not implement USB OTG. */
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.multipoint = 0,
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/* Max EPs scanned, driver will decide which EP can be used. */
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.num_eps = 4,
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/* RAMbits needed to configure EPs from table */
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.ram_bits = 9,
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.fifo_cfg = jz4740_musb_fifo_cfg,
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.fifo_cfg_size = ARRAY_SIZE(jz4740_musb_fifo_cfg),
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};
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static int jz4740_musb_role_switch_set(struct usb_role_switch *sw,
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enum usb_role role)
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{
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struct jz4740_glue *glue = usb_role_switch_get_drvdata(sw);
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struct usb_phy *phy = glue->musb->xceiv;
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switch (role) {
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case USB_ROLE_NONE:
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atomic_notifier_call_chain(&phy->notifier, USB_EVENT_NONE, phy);
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break;
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case USB_ROLE_DEVICE:
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atomic_notifier_call_chain(&phy->notifier, USB_EVENT_VBUS, phy);
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break;
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case USB_ROLE_HOST:
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atomic_notifier_call_chain(&phy->notifier, USB_EVENT_ID, phy);
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break;
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}
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return 0;
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}
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static int jz4740_musb_init(struct musb *musb)
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{
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struct device *dev = musb->controller->parent;
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struct jz4740_glue *glue = dev_get_drvdata(dev);
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struct usb_role_switch_desc role_sw_desc = {
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.set = jz4740_musb_role_switch_set,
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.driver_data = glue,
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.fwnode = dev_fwnode(dev),
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};
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int err;
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glue->musb = musb;
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if (dev->of_node)
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musb->xceiv = devm_usb_get_phy_by_phandle(dev, "phys", 0);
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else
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musb->xceiv = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
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if (IS_ERR(musb->xceiv)) {
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err = PTR_ERR(musb->xceiv);
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if (err != -EPROBE_DEFER)
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dev_err(dev, "No transceiver configured: %d", err);
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return err;
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}
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glue->role_sw = usb_role_switch_register(dev, &role_sw_desc);
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if (IS_ERR(glue->role_sw)) {
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dev_err(dev, "Failed to register USB role switch");
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return PTR_ERR(glue->role_sw);
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}
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/*
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* Silicon does not implement ConfigData register.
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* Set dyn_fifo to avoid reading EP config from hardware.
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*/
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musb->dyn_fifo = true;
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musb->isr = jz4740_musb_interrupt;
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return 0;
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}
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static int jz4740_musb_exit(struct musb *musb)
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{
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struct jz4740_glue *glue = dev_get_drvdata(musb->controller->parent);
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usb_role_switch_unregister(glue->role_sw);
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return 0;
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}
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static const struct musb_platform_ops jz4740_musb_ops = {
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.quirks = MUSB_DMA_INVENTRA | MUSB_INDEXED_EP,
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.fifo_mode = 2,
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.init = jz4740_musb_init,
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.exit = jz4740_musb_exit,
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#ifdef CONFIG_USB_INVENTRA_DMA
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.dma_init = musbhs_dma_controller_create_noirq,
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.dma_exit = musbhs_dma_controller_destroy,
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#endif
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};
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static const struct musb_hdrc_platform_data jz4740_musb_pdata = {
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.mode = MUSB_PERIPHERAL,
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.config = &jz4740_musb_config,
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.platform_ops = &jz4740_musb_ops,
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};
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static struct musb_fifo_cfg jz4770_musb_fifo_cfg[] = {
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{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
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{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
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{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
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{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
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{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
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{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
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{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
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{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
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{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
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{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
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};
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static struct musb_hdrc_config jz4770_musb_config = {
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.multipoint = 1,
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.num_eps = 11,
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.ram_bits = 11,
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.fifo_cfg = jz4770_musb_fifo_cfg,
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.fifo_cfg_size = ARRAY_SIZE(jz4770_musb_fifo_cfg),
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};
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static const struct musb_hdrc_platform_data jz4770_musb_pdata = {
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.mode = MUSB_PERIPHERAL, /* TODO: support OTG */
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.config = &jz4770_musb_config,
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.platform_ops = &jz4740_musb_ops,
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};
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static int jz4740_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct musb_hdrc_platform_data *pdata;
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struct platform_device *musb;
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struct jz4740_glue *glue;
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struct clk *clk;
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int ret;
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glue = devm_kzalloc(dev, sizeof(*glue), GFP_KERNEL);
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if (!glue)
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return -ENOMEM;
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pdata = of_device_get_match_data(dev);
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if (!pdata) {
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dev_err(dev, "missing platform data");
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return -EINVAL;
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}
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musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
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if (!musb) {
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dev_err(dev, "failed to allocate musb device");
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return -ENOMEM;
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}
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clk = devm_clk_get(dev, "udc");
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if (IS_ERR(clk)) {
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dev_err(dev, "failed to get clock");
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ret = PTR_ERR(clk);
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goto err_platform_device_put;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_err(dev, "failed to enable clock");
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goto err_platform_device_put;
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}
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musb->dev.parent = dev;
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musb->dev.dma_mask = &musb->dev.coherent_dma_mask;
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musb->dev.coherent_dma_mask = DMA_BIT_MASK(32);
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glue->pdev = musb;
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glue->clk = clk;
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platform_set_drvdata(pdev, glue);
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ret = platform_device_add_resources(musb, pdev->resource,
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pdev->num_resources);
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if (ret) {
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dev_err(dev, "failed to add resources");
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goto err_clk_disable;
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}
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ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
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if (ret) {
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dev_err(dev, "failed to add platform_data");
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goto err_clk_disable;
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}
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ret = platform_device_add(musb);
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if (ret) {
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dev_err(dev, "failed to register musb device");
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goto err_clk_disable;
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}
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return 0;
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err_clk_disable:
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clk_disable_unprepare(clk);
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err_platform_device_put:
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platform_device_put(musb);
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return ret;
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}
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static int jz4740_remove(struct platform_device *pdev)
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{
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struct jz4740_glue *glue = platform_get_drvdata(pdev);
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platform_device_unregister(glue->pdev);
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clk_disable_unprepare(glue->clk);
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return 0;
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}
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static const struct of_device_id jz4740_musb_of_match[] = {
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{ .compatible = "ingenic,jz4740-musb", .data = &jz4740_musb_pdata },
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{ .compatible = "ingenic,jz4770-musb", .data = &jz4770_musb_pdata },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, jz4740_musb_of_match);
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static struct platform_driver jz4740_driver = {
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.probe = jz4740_probe,
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.remove = jz4740_remove,
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.driver = {
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.name = "musb-jz4740",
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.of_match_table = jz4740_musb_of_match,
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},
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};
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MODULE_DESCRIPTION("JZ4740 MUSB Glue Layer");
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MODULE_AUTHOR("Apelete Seketeli <apelete@seketeli.net>");
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MODULE_LICENSE("GPL v2");
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module_platform_driver(jz4740_driver);
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