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![Min Guo](/assets/img/avatar_default.png)
Delete the const attribute of addr parameter in readb/w/l hooks, these changes are for implementing clearing W1C registers. Replace musb_readb/w with musb_clearb/w to clear the interrupt status. While at here, change some unsigned type to u32 to fix checkpatch.pl warnings. Signed-off-by: Min Guo <min.guo@mediatek.com> [b-liu@ti.com: fix checkpatch.pl warnings.] Signed-off-by: Bin Liu <b-liu@ti.com> Link: https://lore.kernel.org/r/20200115132547.364-23-b-liu@ti.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
837 lines
23 KiB
C
837 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Allwinner sun4i MUSB Glue Layer
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*
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* Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
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*
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* Based on code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/extcon.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy-sun4i-usb.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/soc/sunxi/sunxi_sram.h>
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#include <linux/usb/musb.h>
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#include <linux/usb/of.h>
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#include <linux/usb/usb_phy_generic.h>
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#include <linux/workqueue.h>
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#include "musb_core.h"
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/*
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* Register offsets, note sunxi musb has a different layout then most
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* musb implementations, we translate the layout in musb_readb & friends.
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*/
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#define SUNXI_MUSB_POWER 0x0040
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#define SUNXI_MUSB_DEVCTL 0x0041
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#define SUNXI_MUSB_INDEX 0x0042
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#define SUNXI_MUSB_VEND0 0x0043
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#define SUNXI_MUSB_INTRTX 0x0044
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#define SUNXI_MUSB_INTRRX 0x0046
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#define SUNXI_MUSB_INTRTXE 0x0048
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#define SUNXI_MUSB_INTRRXE 0x004a
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#define SUNXI_MUSB_INTRUSB 0x004c
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#define SUNXI_MUSB_INTRUSBE 0x0050
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#define SUNXI_MUSB_FRAME 0x0054
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#define SUNXI_MUSB_TXFIFOSZ 0x0090
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#define SUNXI_MUSB_TXFIFOADD 0x0092
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#define SUNXI_MUSB_RXFIFOSZ 0x0094
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#define SUNXI_MUSB_RXFIFOADD 0x0096
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#define SUNXI_MUSB_FADDR 0x0098
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#define SUNXI_MUSB_TXFUNCADDR 0x0098
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#define SUNXI_MUSB_TXHUBADDR 0x009a
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#define SUNXI_MUSB_TXHUBPORT 0x009b
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#define SUNXI_MUSB_RXFUNCADDR 0x009c
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#define SUNXI_MUSB_RXHUBADDR 0x009e
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#define SUNXI_MUSB_RXHUBPORT 0x009f
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#define SUNXI_MUSB_CONFIGDATA 0x00c0
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/* VEND0 bits */
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#define SUNXI_MUSB_VEND0_PIO_MODE 0
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/* flags */
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#define SUNXI_MUSB_FL_ENABLED 0
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#define SUNXI_MUSB_FL_HOSTMODE 1
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#define SUNXI_MUSB_FL_HOSTMODE_PEND 2
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#define SUNXI_MUSB_FL_VBUS_ON 3
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#define SUNXI_MUSB_FL_PHY_ON 4
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#define SUNXI_MUSB_FL_HAS_SRAM 5
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#define SUNXI_MUSB_FL_HAS_RESET 6
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#define SUNXI_MUSB_FL_NO_CONFIGDATA 7
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#define SUNXI_MUSB_FL_PHY_MODE_PEND 8
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/* Our read/write methods need access and do not get passed in a musb ref :| */
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static struct musb *sunxi_musb;
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struct sunxi_glue {
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struct device *dev;
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struct musb *musb;
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struct platform_device *musb_pdev;
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struct clk *clk;
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struct reset_control *rst;
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struct phy *phy;
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struct platform_device *usb_phy;
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struct usb_phy *xceiv;
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enum phy_mode phy_mode;
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unsigned long flags;
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struct work_struct work;
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struct extcon_dev *extcon;
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struct notifier_block host_nb;
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};
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/* phy_power_on / off may sleep, so we use a workqueue */
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static void sunxi_musb_work(struct work_struct *work)
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{
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struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work);
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bool vbus_on, phy_on;
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if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
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return;
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if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) {
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struct musb *musb = glue->musb;
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unsigned long flags;
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u8 devctl;
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spin_lock_irqsave(&musb->lock, flags);
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devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL);
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if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) {
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set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
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musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
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MUSB_HST_MODE(musb);
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devctl |= MUSB_DEVCTL_SESSION;
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} else {
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clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
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musb->xceiv->otg->state = OTG_STATE_B_IDLE;
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MUSB_DEV_MODE(musb);
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devctl &= ~MUSB_DEVCTL_SESSION;
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}
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writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL);
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
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phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
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if (phy_on != vbus_on) {
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if (vbus_on) {
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phy_power_on(glue->phy);
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set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
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} else {
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phy_power_off(glue->phy);
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clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
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}
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}
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if (test_and_clear_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags))
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phy_set_mode(glue->phy, glue->phy_mode);
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}
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static void sunxi_musb_set_vbus(struct musb *musb, int is_on)
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{
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struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
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if (is_on) {
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set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
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musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
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} else {
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clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
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}
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schedule_work(&glue->work);
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}
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static void sunxi_musb_pre_root_reset_end(struct musb *musb)
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{
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struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
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sun4i_usb_phy_set_squelch_detect(glue->phy, false);
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}
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static void sunxi_musb_post_root_reset_end(struct musb *musb)
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{
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struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
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sun4i_usb_phy_set_squelch_detect(glue->phy, true);
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}
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static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
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{
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struct musb *musb = __hci;
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unsigned long flags;
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spin_lock_irqsave(&musb->lock, flags);
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musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB);
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if (musb->int_usb)
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writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB);
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if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
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/* ep0 FADDR must be 0 when (re)entering peripheral mode */
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musb_ep_select(musb->mregs, 0);
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musb_writeb(musb->mregs, MUSB_FADDR, 0);
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}
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musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX);
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if (musb->int_tx)
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writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX);
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musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX);
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if (musb->int_rx)
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writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX);
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musb_interrupt(musb);
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spin_unlock_irqrestore(&musb->lock, flags);
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return IRQ_HANDLED;
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}
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static int sunxi_musb_host_notifier(struct notifier_block *nb,
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unsigned long event, void *ptr)
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{
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struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb);
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if (event)
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set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
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else
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clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
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set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags);
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schedule_work(&glue->work);
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return NOTIFY_DONE;
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}
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static int sunxi_musb_init(struct musb *musb)
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{
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struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
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int ret;
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sunxi_musb = musb;
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musb->phy = glue->phy;
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musb->xceiv = glue->xceiv;
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if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) {
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ret = sunxi_sram_claim(musb->controller->parent);
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if (ret)
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return ret;
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}
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ret = clk_prepare_enable(glue->clk);
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if (ret)
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goto error_sram_release;
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if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
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ret = reset_control_deassert(glue->rst);
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if (ret)
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goto error_clk_disable;
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}
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writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0);
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/* Register notifier before calling phy_init() */
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ret = devm_extcon_register_notifier(glue->dev, glue->extcon,
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EXTCON_USB_HOST, &glue->host_nb);
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if (ret)
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goto error_reset_assert;
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ret = phy_init(glue->phy);
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if (ret)
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goto error_reset_assert;
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musb->isr = sunxi_musb_interrupt;
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/* Stop the musb-core from doing runtime pm (not supported on sunxi) */
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pm_runtime_get(musb->controller);
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return 0;
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error_reset_assert:
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if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
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reset_control_assert(glue->rst);
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error_clk_disable:
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clk_disable_unprepare(glue->clk);
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error_sram_release:
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if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
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sunxi_sram_release(musb->controller->parent);
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return ret;
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}
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static int sunxi_musb_exit(struct musb *musb)
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{
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struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
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pm_runtime_put(musb->controller);
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cancel_work_sync(&glue->work);
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if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags))
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phy_power_off(glue->phy);
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phy_exit(glue->phy);
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if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
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reset_control_assert(glue->rst);
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clk_disable_unprepare(glue->clk);
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if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
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sunxi_sram_release(musb->controller->parent);
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devm_usb_put_phy(glue->dev, glue->xceiv);
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return 0;
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}
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static void sunxi_musb_enable(struct musb *musb)
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{
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struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
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glue->musb = musb;
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/* musb_core does not call us in a balanced manner */
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if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
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return;
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schedule_work(&glue->work);
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}
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static void sunxi_musb_disable(struct musb *musb)
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{
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struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
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clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags);
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}
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static struct dma_controller *
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sunxi_musb_dma_controller_create(struct musb *musb, void __iomem *base)
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{
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return NULL;
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}
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static void sunxi_musb_dma_controller_destroy(struct dma_controller *c)
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{
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}
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static int sunxi_musb_set_mode(struct musb *musb, u8 mode)
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{
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struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
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enum phy_mode new_mode;
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switch (mode) {
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case MUSB_HOST:
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new_mode = PHY_MODE_USB_HOST;
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break;
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case MUSB_PERIPHERAL:
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new_mode = PHY_MODE_USB_DEVICE;
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break;
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case MUSB_OTG:
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new_mode = PHY_MODE_USB_OTG;
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break;
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default:
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dev_err(musb->controller->parent,
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"Error requested mode not supported by this kernel\n");
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return -EINVAL;
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}
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if (glue->phy_mode == new_mode)
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return 0;
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if (musb->port_mode != MUSB_OTG) {
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dev_err(musb->controller->parent,
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"Error changing modes is only supported in dual role mode\n");
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return -EINVAL;
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}
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if (musb->port1_status & USB_PORT_STAT_ENABLE)
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musb_root_disconnect(musb);
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/*
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* phy_set_mode may sleep, and we're called with a spinlock held,
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* so let sunxi_musb_work deal with it.
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*/
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glue->phy_mode = new_mode;
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set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags);
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schedule_work(&glue->work);
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return 0;
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}
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static int sunxi_musb_recover(struct musb *musb)
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{
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struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
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/*
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* Schedule a phy_set_mode with the current glue->phy_mode value,
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* this will force end the current session.
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*/
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set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags);
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schedule_work(&glue->work);
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return 0;
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}
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/*
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* sunxi musb register layout
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* 0x00 - 0x17 fifo regs, 1 long per fifo
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* 0x40 - 0x57 generic control regs (power - frame)
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* 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed)
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* 0x90 - 0x97 fifo control regs (indexed)
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* 0x98 - 0x9f multipoint / busctl regs (indexed)
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* 0xc0 configdata reg
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*/
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static u32 sunxi_musb_fifo_offset(u8 epnum)
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{
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return (epnum * 4);
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}
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static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset)
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{
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WARN_ONCE(offset != 0,
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"sunxi_musb_ep_offset called with non 0 offset\n");
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return 0x80; /* indexed, so ignore epnum */
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}
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static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset)
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{
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return SUNXI_MUSB_TXFUNCADDR + offset;
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}
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static u8 sunxi_musb_readb(void __iomem *addr, u32 offset)
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{
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struct sunxi_glue *glue;
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if (addr == sunxi_musb->mregs) {
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/* generic control or fifo control reg access */
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switch (offset) {
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case MUSB_FADDR:
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return readb(addr + SUNXI_MUSB_FADDR);
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case MUSB_POWER:
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return readb(addr + SUNXI_MUSB_POWER);
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case MUSB_INTRUSB:
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return readb(addr + SUNXI_MUSB_INTRUSB);
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case MUSB_INTRUSBE:
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return readb(addr + SUNXI_MUSB_INTRUSBE);
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case MUSB_INDEX:
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return readb(addr + SUNXI_MUSB_INDEX);
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case MUSB_TESTMODE:
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return 0; /* No testmode on sunxi */
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case MUSB_DEVCTL:
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return readb(addr + SUNXI_MUSB_DEVCTL);
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case MUSB_TXFIFOSZ:
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return readb(addr + SUNXI_MUSB_TXFIFOSZ);
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case MUSB_RXFIFOSZ:
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return readb(addr + SUNXI_MUSB_RXFIFOSZ);
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case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */
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glue = dev_get_drvdata(sunxi_musb->controller->parent);
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/* A33 saves a reg, and we get to hardcode this */
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if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA,
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&glue->flags))
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return 0xde;
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return readb(addr + SUNXI_MUSB_CONFIGDATA);
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/* Offset for these is fixed by sunxi_musb_busctl_offset() */
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case SUNXI_MUSB_TXFUNCADDR:
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case SUNXI_MUSB_TXHUBADDR:
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case SUNXI_MUSB_TXHUBPORT:
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case SUNXI_MUSB_RXFUNCADDR:
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case SUNXI_MUSB_RXHUBADDR:
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case SUNXI_MUSB_RXHUBPORT:
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/* multipoint / busctl reg access */
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return readb(addr + offset);
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default:
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dev_err(sunxi_musb->controller->parent,
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"Error unknown readb offset %u\n", offset);
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return 0;
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}
|
|
} else if (addr == (sunxi_musb->mregs + 0x80)) {
|
|
/* ep control reg access */
|
|
/* sunxi has a 2 byte hole before the txtype register */
|
|
if (offset >= MUSB_TXTYPE)
|
|
offset += 2;
|
|
return readb(addr + offset);
|
|
}
|
|
|
|
dev_err(sunxi_musb->controller->parent,
|
|
"Error unknown readb at 0x%x bytes offset\n",
|
|
(int)(addr - sunxi_musb->mregs));
|
|
return 0;
|
|
}
|
|
|
|
static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
|
|
{
|
|
if (addr == sunxi_musb->mregs) {
|
|
/* generic control or fifo control reg access */
|
|
switch (offset) {
|
|
case MUSB_FADDR:
|
|
return writeb(data, addr + SUNXI_MUSB_FADDR);
|
|
case MUSB_POWER:
|
|
return writeb(data, addr + SUNXI_MUSB_POWER);
|
|
case MUSB_INTRUSB:
|
|
return writeb(data, addr + SUNXI_MUSB_INTRUSB);
|
|
case MUSB_INTRUSBE:
|
|
return writeb(data, addr + SUNXI_MUSB_INTRUSBE);
|
|
case MUSB_INDEX:
|
|
return writeb(data, addr + SUNXI_MUSB_INDEX);
|
|
case MUSB_TESTMODE:
|
|
if (data)
|
|
dev_warn(sunxi_musb->controller->parent,
|
|
"sunxi-musb does not have testmode\n");
|
|
return;
|
|
case MUSB_DEVCTL:
|
|
return writeb(data, addr + SUNXI_MUSB_DEVCTL);
|
|
case MUSB_TXFIFOSZ:
|
|
return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ);
|
|
case MUSB_RXFIFOSZ:
|
|
return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ);
|
|
/* Offset for these is fixed by sunxi_musb_busctl_offset() */
|
|
case SUNXI_MUSB_TXFUNCADDR:
|
|
case SUNXI_MUSB_TXHUBADDR:
|
|
case SUNXI_MUSB_TXHUBPORT:
|
|
case SUNXI_MUSB_RXFUNCADDR:
|
|
case SUNXI_MUSB_RXHUBADDR:
|
|
case SUNXI_MUSB_RXHUBPORT:
|
|
/* multipoint / busctl reg access */
|
|
return writeb(data, addr + offset);
|
|
default:
|
|
dev_err(sunxi_musb->controller->parent,
|
|
"Error unknown writeb offset %u\n", offset);
|
|
return;
|
|
}
|
|
} else if (addr == (sunxi_musb->mregs + 0x80)) {
|
|
/* ep control reg access */
|
|
if (offset >= MUSB_TXTYPE)
|
|
offset += 2;
|
|
return writeb(data, addr + offset);
|
|
}
|
|
|
|
dev_err(sunxi_musb->controller->parent,
|
|
"Error unknown writeb at 0x%x bytes offset\n",
|
|
(int)(addr - sunxi_musb->mregs));
|
|
}
|
|
|
|
static u16 sunxi_musb_readw(void __iomem *addr, u32 offset)
|
|
{
|
|
if (addr == sunxi_musb->mregs) {
|
|
/* generic control or fifo control reg access */
|
|
switch (offset) {
|
|
case MUSB_INTRTX:
|
|
return readw(addr + SUNXI_MUSB_INTRTX);
|
|
case MUSB_INTRRX:
|
|
return readw(addr + SUNXI_MUSB_INTRRX);
|
|
case MUSB_INTRTXE:
|
|
return readw(addr + SUNXI_MUSB_INTRTXE);
|
|
case MUSB_INTRRXE:
|
|
return readw(addr + SUNXI_MUSB_INTRRXE);
|
|
case MUSB_FRAME:
|
|
return readw(addr + SUNXI_MUSB_FRAME);
|
|
case MUSB_TXFIFOADD:
|
|
return readw(addr + SUNXI_MUSB_TXFIFOADD);
|
|
case MUSB_RXFIFOADD:
|
|
return readw(addr + SUNXI_MUSB_RXFIFOADD);
|
|
case MUSB_HWVERS:
|
|
return 0; /* sunxi musb version is not known */
|
|
default:
|
|
dev_err(sunxi_musb->controller->parent,
|
|
"Error unknown readw offset %u\n", offset);
|
|
return 0;
|
|
}
|
|
} else if (addr == (sunxi_musb->mregs + 0x80)) {
|
|
/* ep control reg access */
|
|
return readw(addr + offset);
|
|
}
|
|
|
|
dev_err(sunxi_musb->controller->parent,
|
|
"Error unknown readw at 0x%x bytes offset\n",
|
|
(int)(addr - sunxi_musb->mregs));
|
|
return 0;
|
|
}
|
|
|
|
static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data)
|
|
{
|
|
if (addr == sunxi_musb->mregs) {
|
|
/* generic control or fifo control reg access */
|
|
switch (offset) {
|
|
case MUSB_INTRTX:
|
|
return writew(data, addr + SUNXI_MUSB_INTRTX);
|
|
case MUSB_INTRRX:
|
|
return writew(data, addr + SUNXI_MUSB_INTRRX);
|
|
case MUSB_INTRTXE:
|
|
return writew(data, addr + SUNXI_MUSB_INTRTXE);
|
|
case MUSB_INTRRXE:
|
|
return writew(data, addr + SUNXI_MUSB_INTRRXE);
|
|
case MUSB_FRAME:
|
|
return writew(data, addr + SUNXI_MUSB_FRAME);
|
|
case MUSB_TXFIFOADD:
|
|
return writew(data, addr + SUNXI_MUSB_TXFIFOADD);
|
|
case MUSB_RXFIFOADD:
|
|
return writew(data, addr + SUNXI_MUSB_RXFIFOADD);
|
|
default:
|
|
dev_err(sunxi_musb->controller->parent,
|
|
"Error unknown writew offset %u\n", offset);
|
|
return;
|
|
}
|
|
} else if (addr == (sunxi_musb->mregs + 0x80)) {
|
|
/* ep control reg access */
|
|
return writew(data, addr + offset);
|
|
}
|
|
|
|
dev_err(sunxi_musb->controller->parent,
|
|
"Error unknown writew at 0x%x bytes offset\n",
|
|
(int)(addr - sunxi_musb->mregs));
|
|
}
|
|
|
|
static const struct musb_platform_ops sunxi_musb_ops = {
|
|
.quirks = MUSB_INDEXED_EP,
|
|
.init = sunxi_musb_init,
|
|
.exit = sunxi_musb_exit,
|
|
.enable = sunxi_musb_enable,
|
|
.disable = sunxi_musb_disable,
|
|
.fifo_offset = sunxi_musb_fifo_offset,
|
|
.ep_offset = sunxi_musb_ep_offset,
|
|
.busctl_offset = sunxi_musb_busctl_offset,
|
|
.readb = sunxi_musb_readb,
|
|
.writeb = sunxi_musb_writeb,
|
|
.readw = sunxi_musb_readw,
|
|
.writew = sunxi_musb_writew,
|
|
.dma_init = sunxi_musb_dma_controller_create,
|
|
.dma_exit = sunxi_musb_dma_controller_destroy,
|
|
.set_mode = sunxi_musb_set_mode,
|
|
.recover = sunxi_musb_recover,
|
|
.set_vbus = sunxi_musb_set_vbus,
|
|
.pre_root_reset_end = sunxi_musb_pre_root_reset_end,
|
|
.post_root_reset_end = sunxi_musb_post_root_reset_end,
|
|
};
|
|
|
|
/* Allwinner OTG supports up to 5 endpoints */
|
|
#define SUNXI_MUSB_MAX_EP_NUM 6
|
|
#define SUNXI_MUSB_RAM_BITS 11
|
|
|
|
static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
|
|
MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
|
|
MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
|
|
MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
|
|
MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
|
|
MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
|
|
MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
|
|
MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
|
|
MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
|
|
MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
|
|
MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
|
|
};
|
|
|
|
/* H3/V3s OTG supports only 4 endpoints */
|
|
#define SUNXI_MUSB_MAX_EP_NUM_H3 5
|
|
|
|
static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = {
|
|
MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
|
|
MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
|
|
MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
|
|
MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
|
|
MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
|
|
MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
|
|
MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
|
|
MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
|
|
};
|
|
|
|
static const struct musb_hdrc_config sunxi_musb_hdrc_config = {
|
|
.fifo_cfg = sunxi_musb_mode_cfg,
|
|
.fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
|
|
.multipoint = true,
|
|
.dyn_fifo = true,
|
|
.num_eps = SUNXI_MUSB_MAX_EP_NUM,
|
|
.ram_bits = SUNXI_MUSB_RAM_BITS,
|
|
};
|
|
|
|
static struct musb_hdrc_config sunxi_musb_hdrc_config_h3 = {
|
|
.fifo_cfg = sunxi_musb_mode_cfg_h3,
|
|
.fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_h3),
|
|
.multipoint = true,
|
|
.dyn_fifo = true,
|
|
.num_eps = SUNXI_MUSB_MAX_EP_NUM_H3,
|
|
.ram_bits = SUNXI_MUSB_RAM_BITS,
|
|
};
|
|
|
|
|
|
static int sunxi_musb_probe(struct platform_device *pdev)
|
|
{
|
|
struct musb_hdrc_platform_data pdata;
|
|
struct platform_device_info pinfo;
|
|
struct sunxi_glue *glue;
|
|
struct device_node *np = pdev->dev.of_node;
|
|
int ret;
|
|
|
|
if (!np) {
|
|
dev_err(&pdev->dev, "Error no device tree node found\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
|
|
if (!glue)
|
|
return -ENOMEM;
|
|
|
|
memset(&pdata, 0, sizeof(pdata));
|
|
switch (usb_get_dr_mode(&pdev->dev)) {
|
|
#if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST
|
|
case USB_DR_MODE_HOST:
|
|
pdata.mode = MUSB_HOST;
|
|
glue->phy_mode = PHY_MODE_USB_HOST;
|
|
break;
|
|
#endif
|
|
#if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_GADGET
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
pdata.mode = MUSB_PERIPHERAL;
|
|
glue->phy_mode = PHY_MODE_USB_DEVICE;
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_USB_MUSB_DUAL_ROLE
|
|
case USB_DR_MODE_OTG:
|
|
pdata.mode = MUSB_OTG;
|
|
glue->phy_mode = PHY_MODE_USB_OTG;
|
|
break;
|
|
#endif
|
|
default:
|
|
dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n");
|
|
return -EINVAL;
|
|
}
|
|
pdata.platform_ops = &sunxi_musb_ops;
|
|
if (!of_device_is_compatible(np, "allwinner,sun8i-h3-musb"))
|
|
pdata.config = &sunxi_musb_hdrc_config;
|
|
else
|
|
pdata.config = &sunxi_musb_hdrc_config_h3;
|
|
|
|
glue->dev = &pdev->dev;
|
|
INIT_WORK(&glue->work, sunxi_musb_work);
|
|
glue->host_nb.notifier_call = sunxi_musb_host_notifier;
|
|
|
|
if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
|
|
set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
|
|
|
|
if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
|
|
set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
|
|
|
|
if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
|
|
of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
|
|
set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
|
|
set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
|
|
}
|
|
|
|
glue->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(glue->clk)) {
|
|
dev_err(&pdev->dev, "Error getting clock: %ld\n",
|
|
PTR_ERR(glue->clk));
|
|
return PTR_ERR(glue->clk);
|
|
}
|
|
|
|
if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
|
|
glue->rst = devm_reset_control_get(&pdev->dev, NULL);
|
|
if (IS_ERR(glue->rst)) {
|
|
if (PTR_ERR(glue->rst) == -EPROBE_DEFER)
|
|
return -EPROBE_DEFER;
|
|
dev_err(&pdev->dev, "Error getting reset %ld\n",
|
|
PTR_ERR(glue->rst));
|
|
return PTR_ERR(glue->rst);
|
|
}
|
|
}
|
|
|
|
glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0);
|
|
if (IS_ERR(glue->extcon)) {
|
|
if (PTR_ERR(glue->extcon) == -EPROBE_DEFER)
|
|
return -EPROBE_DEFER;
|
|
dev_err(&pdev->dev, "Invalid or missing extcon\n");
|
|
return PTR_ERR(glue->extcon);
|
|
}
|
|
|
|
glue->phy = devm_phy_get(&pdev->dev, "usb");
|
|
if (IS_ERR(glue->phy)) {
|
|
if (PTR_ERR(glue->phy) == -EPROBE_DEFER)
|
|
return -EPROBE_DEFER;
|
|
dev_err(&pdev->dev, "Error getting phy %ld\n",
|
|
PTR_ERR(glue->phy));
|
|
return PTR_ERR(glue->phy);
|
|
}
|
|
|
|
glue->usb_phy = usb_phy_generic_register();
|
|
if (IS_ERR(glue->usb_phy)) {
|
|
dev_err(&pdev->dev, "Error registering usb-phy %ld\n",
|
|
PTR_ERR(glue->usb_phy));
|
|
return PTR_ERR(glue->usb_phy);
|
|
}
|
|
|
|
glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
|
|
if (IS_ERR(glue->xceiv)) {
|
|
ret = PTR_ERR(glue->xceiv);
|
|
dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret);
|
|
goto err_unregister_usb_phy;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, glue);
|
|
|
|
memset(&pinfo, 0, sizeof(pinfo));
|
|
pinfo.name = "musb-hdrc";
|
|
pinfo.id = PLATFORM_DEVID_AUTO;
|
|
pinfo.parent = &pdev->dev;
|
|
pinfo.fwnode = of_fwnode_handle(pdev->dev.of_node);
|
|
pinfo.of_node_reused = true;
|
|
pinfo.res = pdev->resource;
|
|
pinfo.num_res = pdev->num_resources;
|
|
pinfo.data = &pdata;
|
|
pinfo.size_data = sizeof(pdata);
|
|
|
|
glue->musb_pdev = platform_device_register_full(&pinfo);
|
|
if (IS_ERR(glue->musb_pdev)) {
|
|
ret = PTR_ERR(glue->musb_pdev);
|
|
dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret);
|
|
goto err_unregister_usb_phy;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_unregister_usb_phy:
|
|
usb_phy_generic_unregister(glue->usb_phy);
|
|
return ret;
|
|
}
|
|
|
|
static int sunxi_musb_remove(struct platform_device *pdev)
|
|
{
|
|
struct sunxi_glue *glue = platform_get_drvdata(pdev);
|
|
struct platform_device *usb_phy = glue->usb_phy;
|
|
|
|
platform_device_unregister(glue->musb_pdev);
|
|
usb_phy_generic_unregister(usb_phy);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id sunxi_musb_match[] = {
|
|
{ .compatible = "allwinner,sun4i-a10-musb", },
|
|
{ .compatible = "allwinner,sun6i-a31-musb", },
|
|
{ .compatible = "allwinner,sun8i-a33-musb", },
|
|
{ .compatible = "allwinner,sun8i-h3-musb", },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sunxi_musb_match);
|
|
|
|
static struct platform_driver sunxi_musb_driver = {
|
|
.probe = sunxi_musb_probe,
|
|
.remove = sunxi_musb_remove,
|
|
.driver = {
|
|
.name = "musb-sunxi",
|
|
.of_match_table = sunxi_musb_match,
|
|
},
|
|
};
|
|
module_platform_driver(sunxi_musb_driver);
|
|
|
|
MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer");
|
|
MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
|
|
MODULE_LICENSE("GPL v2");
|